CN108493113A - A kind of manufacturing method of low resistance Flouride-resistani acid phesphatase VDMOS chip - Google Patents
A kind of manufacturing method of low resistance Flouride-resistani acid phesphatase VDMOS chip Download PDFInfo
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- CN108493113A CN108493113A CN201810288611.9A CN201810288611A CN108493113A CN 108493113 A CN108493113 A CN 108493113A CN 201810288611 A CN201810288611 A CN 201810288611A CN 108493113 A CN108493113 A CN 108493113A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 36
- 239000002253 acid Substances 0.000 title claims abstract description 20
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 26
- 229910052796 boron Inorganic materials 0.000 claims abstract description 20
- 238000001259 photo etching Methods 0.000 claims abstract description 20
- 238000002347 injection Methods 0.000 claims abstract description 11
- 239000007924 injection Substances 0.000 claims abstract description 11
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 42
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 40
- 229910052710 silicon Inorganic materials 0.000 claims description 40
- 239000010703 silicon Substances 0.000 claims description 40
- 229910052751 metal Inorganic materials 0.000 claims description 19
- 239000002184 metal Substances 0.000 claims description 19
- 239000000377 silicon dioxide Substances 0.000 claims description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 17
- 238000005530 etching Methods 0.000 claims description 15
- 229920005591 polysilicon Polymers 0.000 claims description 14
- 238000002513 implantation Methods 0.000 claims description 12
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 claims description 10
- 238000005468 ion implantation Methods 0.000 claims description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 8
- 238000000137 annealing Methods 0.000 claims description 7
- 238000009792 diffusion process Methods 0.000 claims description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 6
- 235000012239 silicon dioxide Nutrition 0.000 claims description 6
- 239000010936 titanium Substances 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 239000004411 aluminium Substances 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical group [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- 230000015556 catabolic process Effects 0.000 claims description 3
- 238000004140 cleaning Methods 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 238000000407 epitaxy Methods 0.000 claims description 2
- 229910003978 SiClx Inorganic materials 0.000 claims 1
- 229910052785 arsenic Inorganic materials 0.000 claims 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims 1
- 230000003071 parasitic effect Effects 0.000 abstract description 14
- 238000000034 method Methods 0.000 abstract description 8
- 238000005516 engineering process Methods 0.000 abstract description 7
- 239000002245 particle Substances 0.000 abstract description 6
- 230000005855 radiation Effects 0.000 abstract description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- 235000010210 aluminium Nutrition 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000000873 masking effect Effects 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000001413 cellular effect Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- XHXFXVLFKHQFAL-UHFFFAOYSA-N phosphoryl trichloride Chemical compound ClP(Cl)(Cl)=O XHXFXVLFKHQFAL-UHFFFAOYSA-N 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- MOFOBJHOKRNACT-UHFFFAOYSA-N nickel silver Chemical compound [Ni].[Ag] MOFOBJHOKRNACT-UHFFFAOYSA-N 0.000 description 1
- 239000010956 nickel silver Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
Abstract
The present invention provides a kind of manufacturing method of low resistance Flouride-resistani acid phesphatase VDMOS chip, reduces the conducting resistance of VDMOS device, while improving the Radiation hardness of device.The present invention does not need photoetching when forming the areas P+ of VDMOS device structure, but is sheltered using silicon nitride spacer, carries out the autoregistration injection of dense boron.The present invention is suitable for manufacturing the device of small characteristic size, is conducive to increase current density, reduces conducting resistance；Meanwhile the present invention can effectively reduce the base area lateral resistance of device inside parasitic triode, be conducive to that parasitic triode is inhibited to open, the anti-single particle for improving VDMOS device burns ability.The method of the present invention is compatible with traditional manufacturing technology of VDMOS chip, and processing step is simple, can be used for manufacturing highly reliable, efficient VDMOS chip.
Description
Technical field
The present invention relates to a kind of manufacturing methods of low resistance Flouride-resistani acid phesphatase VDMOS chip, belong to field of manufacturing semiconductor devices.
Background technology
Power VDMOSFET field-effect transistor is the New Type Power Devices that last century the eighties develop rapidly.Due to
It has many advantages, such as that switching speed is fast, input resistance is high, frequency characteristic is good, driving capability is high, transconductance linearity degree is high, extensive use
In electronic equipment of various.The electric current vertical devices surface flow of VDMOS device, it is in parallel by many identical unit components
Composition, each unit are known as " cellular ".
In order to realize that high efficiency, the high reliability of power electronic equipment, device have to the switch speed being getting faster
Degree, higher and higher reliability.When VDMOS device is connected, ohmically power attenuation can influence power output, in order to reduce device
The power attenuation of part itself improves switching speed, needs the conducting resistance for reducing device as far as possible.
In addition, being operated in the electronic device in space system, also suffers from a large amount of charged particle and universe in space and penetrate
The influence of line causes single event burnout effect (SEB), and the parameter of device and performance is made to occur to degenerate or fail.In device inside,
There are a parasitic NPN triode structure, wherein n+ source regions are equivalent to the emitter region of parasitic triode, and p-well region, which is equivalent to, to be posted
The base area of raw triode, n- epitaxial layers are equivalent to the collecting zone of parasitic triode.Since the n+ source regions of VDMOS device and the areas P+ are short
It connects, it is usually the case that parasitic triode will not be opened.When device surface is bombarded by single-particle, it is empty that inside generates electronics
Cave pair, electronics flow direction drain electrode movement, hole flows to source electrode movement.It is generated laterally in p-well region when wherein hole flows to source electrode movement
Pressure drop can lead to the unlatching of parasitic triode, go forward side by side when lateral pressure drop is more than the cut-in voltage of device inside parasitic triode
One step causes carrier avalanche multiplication by positive feedback effect, finally device is made to fail because burning.
Invention content
Present invention solves the technical problem that being：To overcome the shortcomings of the existing technology, providing a kind of low resistance Flouride-resistani acid phesphatase VDMOS cores
The manufacturing method of piece improves the Radiation hardness of device to reduce the conducting resistance of device.
Technical solution of the invention is：
A kind of manufacturing method of low resistance Flouride-resistani acid phesphatase VDMOS chip, the specific steps are：
(1) N-type silicon epitaxial wafer is chosen, thermal oxide is carried out after cleaning treatment, forms layer of silicon dioxide gate oxide, then
One layer of polysilicon is deposited in the front side of silicon wafer with silica gate oxide；
(2) it forms front side of silicon wafer in step 1 and carries out photoetching according to the figure in reticle, and etch away the more of corresponding position
Crystal silicon and silica form p-well injection region, inject boron ion in front side of silicon wafer, high temperature promotes to form p-well region；
(3) one layer of silicon nitride is deposited to the front side of silicon wafer with p-well region of step 2, nitridation is fallen by anisotropic etching
Silicon, silicon nitride spacer is formed at the edge of silica and polysilicon, injects the boron ion of high dose in front side of silicon wafer, etching is gone
Silicon nitride side wall, and carry out high temperature and promote to form the areas P+, the areas P+ diffusion depth is compared with the p-well region diffusion depth formed in step 2
It is shallow；
(4) photoetching is carried out to the front side of silicon wafer that step 3 is formed, is then injected into high dose arsenic ion, and carry out high annealing
Arsenic ion is activated, heavy doping N+ source regions are formed in the both sides P+；
(5) front side of silicon wafer obtained in step 4 deposits layer of silicon dioxide dielectric layer, then by photoetching, etching, in P+
Source contact openings are formed above area；
(6) source electrode is formed in front side of silicon wafer deposit metal, forms drain electrode in silicon chip back side deposit metal, completes chip
Manufacture.
In step 1 epitaxy layer thickness of N-type silicon epitaxial wafer be 10-50um, resistivity be 5-10 Ω cm, specific thickness and
Resistivity value is determined by the breakdown voltage of requirement on devices.
The thickness of silica gate oxide is in step 1Polysilicon thickness is
Boron ion Implantation Energy is 80KeV-100MeV, implantation dosage 5E13-3E14cm in step 2-2, promote temperature be
1100 DEG C -1250 DEG C, the propulsion time is 100-1000min.
Silicon nitride thickness is in step 3
The width of the silicon nitride spacer formed in step 3 is 0.3~0.5um.
Boron ion Implantation Energy is 80KeV-100MeV in step 3, and implantation dosage is 7E14~2E15cm-2, promote temperature
It it is 950 DEG C~1050 DEG C, the propulsion time is 100-1000min.
Arsenic ion Implantation Energy is 50-150KeV, implantation dosage 1E15-1E16cm in step 4-2, annealing temperature is
500-1000℃。
The thickness of silica dioxide medium layer is in step 5
The metal of front deposit is aluminium, thickness 2.0-5.0um in 6 in step；The back side deposit metal be followed successively by titanium,
Nickel, silver metal layer, thickness are 1.0~3.0um.
Compared with the prior art, the invention has the advantages that：
(1) when the present invention forms the P+ plot structures of VDMOS device, photoetching is needed not move through, but utilizes silicon nitride spacer
It shelters, realizes that the autoregistration of dense boron injects to be formed, reduce photoetching number, simplify manufacturing process；
(2) when the present invention forms the P+ plot structures of VDMOS device, photoetching is needed not move through, but utilizes silicon nitride spacer
It shelters, realizes that the autoregistration of dense boron injects to be formed, which is conducive to eliminate the set between photoresist thickness and multiple photoetching
The influence of quasi- error is suitable for manufacturing the device of small characteristic size, to make device that can be integrated in unit area more
Cellular quantity reduces conducting resistance；
(3) routine VDMOS manufacturing technologies do covering for the dense boron ion injection in the areas P+ with photoresist using the areas P+ are lithographically formed
It covers, register partial difference is influenced between by the thickness and multiple reticle of photoresist, and parasitic triode base area transverse width cannot be done
It is too narrow, the present invention forms P+ areas using self-aligned technology, is sheltered with silicon nitride spacer, and there is no the alignments between reticle
Problem, and the width of silicon nitride spacer can be made narrow, be conducive to the base area transverse width for reducing parasitic triode, also
It is lateral pressure drop of the hole stream in base area for reducing irradiation generation, to inhibit parasitic triode to be connected, improves the anti-of device
Single particle radiation ability；
(4) present invention process is simple, compatible with traditional VDMOS manufacturing process.
Description of the drawings
Fig. 1 show the manufacturing flow chart of VDMOS chip of the present invention；
Fig. 2 show the sectional structure chart of VDMOS chip of the present invention；
Fig. 3 show the diagrammatic cross-section after gate oxidation and depositing polysilicon；
Fig. 4 show the sectional structure chart after forming p-well region；
Etching shown in Fig. 5 forms the sectional structure chart after silicon nitride spacer；
Fig. 6 show the sectional structure chart after forming the areas P+；
Fig. 7 show the sectional structure chart after forming source region；
Fig. 8 show the sectional structure chart after etching contact hole；
Fig. 9 show the present invention and completes the sectional structure chart after metallization；
Wherein respectively mark meaning as follows in attached drawing：1 be N+ substrates, 2 be N- epitaxial layers, 3 be silica gate oxide, 4
It is p-well region for polysilicon gate, 5,6 be silicon nitride spacer, and 7 be the areas P+, and 8 be heavy doping N+ source regions, and 9 be isolating oxide layer, and 10 are
Source metal electrode, 11 be drain metal electrode.
Specific implementation mode
The present invention is described further below in conjunction with the accompanying drawings.
A kind of manufacturing method of low resistance Flouride-resistani acid phesphatase VDMOS chip, as shown in Figure 1, the specific steps are：
(1) N-type silicon epitaxial wafer is chosen, thermal oxide is carried out after cleaning treatment, forms layer of silicon dioxide gate oxide, then
One layer of polysilicon is deposited in the front side of silicon wafer with silica gate oxide, as shown in Fig. 2, the epitaxial layer of N-type silicon epitaxial wafer
Thickness is 10-50um, and resistivity is 5-10 Ω cm, and specific thickness and resistivity value are determined by the breakdown voltage of requirement on devices
Fixed, the thickness of silica gate oxide is Polysilicon thickness is
(2) it forms front side of silicon wafer in step 1 and carries out photoetching according to the figure in reticle, and etch away the more of corresponding position
Crystal silicon and silica form p-well injection region, as shown in figure 3, injecting boron ion in front side of silicon wafer, high temperature promotes to form p-well
Area, as shown in figure 4, boron ion Implantation Energy is 80KeV-100MeV, implantation dosage 5E13-3E14cm-2, promote temperature be
1100 DEG C -1250 DEG C, the propulsion time is 100-1000min；
(3) one layer of silicon nitride is deposited to the front side of silicon wafer with p-well region of step 2, nitridation is fallen by anisotropic etching
Silicon forms silicon nitride spacer at the edge of silica and polysilicon, as shown in figure 5, injecting the boron of high dose in front side of silicon wafer
Ion, etching removal silicon nitride spacer, and carry out high temperature and promote to form the areas P+, the areas P+ diffusion depth is compared with the p-well formed in step 2
Area's diffusion depth is shallow, as shown in fig. 6, silicon nitride thickness isThe width of the silicon nitride spacer of formation is 0.3
~0.5um.Boron ion Implantation Energy is 80KeV-100MeV, and implantation dosage is 7E14~2E15cm-2, it is 950 DEG C to promote temperature
~1050 DEG C, the propulsion time is 100-1000min；
(4) photoetching is carried out to the front side of silicon wafer that step 3 is formed, is then injected into high dose arsenic ion, and carry out high annealing
Arsenic ion is activated, heavy doping N+ source regions are formed in the both sides P+, as shown in fig. 7, arsenic ion Implantation Energy is 50-150KeV, note
It is 1E15-1E16cm to enter dosage-2, annealing temperature is 500-1000 DEG C；
(5) front side of silicon wafer obtained in step 4 deposits layer of silicon dioxide dielectric layer, then by photoetching, etching, in P+
Source contact openings are formed above area, as shown in figure 8, the thickness of silica dioxide medium layer is
(6) source electrode is formed in front side of silicon wafer deposit metal, drain electrode is formed in silicon chip back side deposit metal, such as Fig. 9 institutes
Show, the metal of front deposit is aluminium, thickness 2.0-5.0um；The metal of back side deposit is followed successively by titanium, nickel, silver metal layer, thickness
For 1.0~3.0um, chip manufacturing is completed.
The manufacturing process for technology that the present invention will be described in detail by taking the VDMOS manufactures of 200V Flouride-resistani acid phesphatases as an example, specific implementation step is such as
Under：
(1) gate oxidation：It chooses<100>Crystal orientation, the silicon epitaxial wafer that structure is N+N-, N- high resistant layer resistivities are 5 Ω cm,
Thickness is 17 μm.1000 DEG C of thermal oxides are carried out, are formedSilica gate oxide 3, as shown in Figure 3.
(2) polysilicon gate：DepositThen polysilicon carries out phosphorus oxychloride diffusion, then carry out polysilicon gate light
It carves, polysilicon gate 4 is formed finally by dry etch process；
(3) p-well region is formed：P-well region photoetching is carried out, boron ion injection, Implantation Energy 100KeV are then carried out, dosage is
2E14cm-2, then 1150 DEG C of progress, 150min high temperature promote to form p-well region 5；
(4) silicon nitride spacer is formed：DepositThen silicon nitride forms silicon nitride spacer 6 by dry etching,
0.3~0.5 μm of width；
(5) areas P+ are formed：Carry out boron ion injection, Implantation Energy 100KeV, dosage 2E15cm-2, then carry out 950
DEG C, 150min high temperature promotes to form the areas P+ 7；
(6) source region is formed：Source region photoetching is carried out, is then injected into arsenic ion, Implantation Energy 100KeV, implantation dosage is
5E15cm-2, and 950 DEG C of high annealings are carried out, arsenic ion is activated, heavy doping N+ source regions 8 are formed；
(7) contact hole is formed：Front depositThen silica isolating oxide layer 9 is formed by photoetching, etching
Contact hole；
(8) it metallizes：3um metallic aluminiums are evaporated in front side of silicon wafer, then photoetching, corrosion metal, form source metal electrode
10.Then silicon chip is thinned to the thickness of 350um in the faces N+, the faces the N+ deposition thickness of the disk after being thinned is respectivelyTitanium/nickel silver metal layer, formed drain metal electrode 11.
The VDMOS chip manufactured using the method for the present invention, the areas P+ are formed using self-aligned technology, are suitable for manufacturing low conducting
Resistance device；The method of the present invention is conducive to reduce the base area lateral resistance of device inside parasitic triode simultaneously, and device is made to have
Better Radiation hardness.Therefore, the reliability and speed of VDMOS chip can be greatly improved using the present invention.
The present invention is improved on the basis of conventional VDMOS manufacturing process, to manufacture the highly reliable VDMOS cores of low resistance
Piece.Concrete principle is：In conventional VDMOS manufacturing process, generally use is lithographically formed the areas device architecture Zhong P+, with photoresist
Masking as the injection of dense boron ion.The shadow of the position in the areas P+ register partial difference between by the thickness and multiple reticle of photoresist
It rings.
The present invention provides a kind of manufacturing method of low resistance Flouride-resistani acid phesphatase VDMOS chip.This method is using silicon epitaxial wafer as substrate
Material includes mainly gate oxidation, polycrystalline silicon deposit and etching, p-well region injection and promotes, etching forms silicon nitride spacer, the areas P+
Injection and propulsion, removal side wall, source region is injected and the processes such as propulsion, contact hole etching, front-side metallization and back metal.It adopts
Use side wall to replace the masking layer that is injected as the areas P+ of photoresist, eliminate photoresist thickness and multiple photoetching between register
The influence of error.Using VDMOS device produced by the present invention while improvement anti-single particle burns ability, there is lower lead
Be powered resistance.
The present invention does not need photoetching, but silicon nitride spacer is used to replace light when forming the areas P+ of VDMOS device structure
Photoresist does masking layer, carries out the autoregistration injection of dense boron ion.
The present invention is injected using autoregistration, and the overlay error eliminated between the thickness of photoresist and multiple reticle is brought
Influence, be suitable for manufacture the device of small characteristic size, be conducive to increase current density, reduction conducting resistance；Meanwhile Ke Yiyou
The base area lateral resistance of the reduction parasitic triode of effect, is conducive to that parasitic triode is inhibited to open, improves the anti-single particle of device
Burn ability.
A kind of manufacturing method of low resistance Flouride-resistani acid phesphatase VDMOS chip of the present invention is only intended to help to illustrate the present invention,
It is not used as the specific implementation mode of the limitation present invention, many modifications and variations, all ownership can be carried out according to actual needs
It in the principle of the present invention and practical application, is all included in the scope of protection of the present invention, it is ability that content, which is not disclosed, in the present invention
Field technique personnel's common knowledge.
Claims (10)
1. a kind of manufacturing method of low resistance Flouride-resistani acid phesphatase VDMOS chip, which is characterized in that the specific steps are：
(1) N-type silicon epitaxial wafer is chosen, thermal oxide is carried out after cleaning treatment, layer of silicon dioxide gate oxide is formed, then in band
There is the front side of silicon wafer of silica gate oxide to deposit one layer of polysilicon；
(2) it forms front side of silicon wafer in step 1 and carries out photoetching according to the figure in reticle, and etch away the polysilicon of corresponding position
And silica, p-well injection region is formed, injects boron ion in front side of silicon wafer, high temperature promotes to form p-well region；
(3) one layer of silicon nitride is deposited to the front side of silicon wafer with p-well region of step 2, silicon nitride is fallen by anisotropic etching,
The edge of silica and polysilicon forms silicon nitride spacer, injects the boron ion of high dose in front side of silicon wafer, etching goes to denitrogenate
SiClx side wall, and carry out high temperature and promote to form the areas P+, the areas P+ diffusion depth is shallow compared with the p-well region diffusion depth formed in step 2；
(4) photoetching is carried out to the front side of silicon wafer that step 3 is formed, is then injected into high dose arsenic ion, and carry out high annealing by arsenic
It is ion-activated, form heavy doping N+ source regions in the both sides P+；
(5) front side of silicon wafer obtained in step 4 deposits layer of silicon dioxide dielectric layer, then by photoetching, etching, in the areas P+
It is rectangular at source contact openings；
(6) source electrode is formed in front side of silicon wafer deposit metal, forms drain electrode in silicon chip back side deposit metal, completes chip system
It makes.
2. a kind of manufacturing method of low resistance Flouride-resistani acid phesphatase VDMOS chip as described in claim 1, which is characterized in that in step 1
The epitaxy layer thickness of N-type silicon epitaxial wafer is 10-50um, and resistivity is 5-10 Ω cm, and specific thickness and resistivity value are by device
The breakdown voltage that part requires determines.
3. a kind of manufacturing method of low resistance Flouride-resistani acid phesphatase VDMOS chip as described in claim 1, which is characterized in that in step 1
The thickness of silica gate oxide isPolysilicon thickness is
4. a kind of manufacturing method of low resistance Flouride-resistani acid phesphatase VDMOS chip as described in claim 1, which is characterized in that in step 2
Boron ion Implantation Energy is 80KeV-100MeV, implantation dosage 5E13-3E14cm-2, it is 1100 DEG C -1250 DEG C to promote temperature,
The propulsion time is 100-1000min.
5. a kind of manufacturing method of low resistance Flouride-resistani acid phesphatase VDMOS chip as described in claim 1, which is characterized in that in step 3
Silicon nitride thickness is
6. a kind of manufacturing method of low resistance Flouride-resistani acid phesphatase VDMOS chip as described in claim 1, which is characterized in that in step 3
The width of the silicon nitride spacer of formation is 0.3~0.5um.
7. a kind of manufacturing method of low resistance Flouride-resistani acid phesphatase VDMOS chip as described in claim 1, which is characterized in that in step 3
Boron ion Implantation Energy is 80KeV-100MeV, and implantation dosage is 7E14~2E15cm-2, it is 950 DEG C~1050 DEG C to promote temperature,
The propulsion time is 100-1000min.
8. a kind of manufacturing method of low resistance Flouride-resistani acid phesphatase VDMOS chip as described in claim 1, which is characterized in that in step 4
Arsenic ion Implantation Energy is 50-150KeV, implantation dosage 1E15-1E16cm-2, annealing temperature is 500-1000 DEG C.
9. a kind of manufacturing method of low resistance Flouride-resistani acid phesphatase VDMOS chip as described in claim 1, which is characterized in that in step 5
The thickness of silica dioxide medium layer is
10. a kind of manufacturing method of low resistance Flouride-resistani acid phesphatase VDMOS chip as described in claim 1, which is characterized in that in step
The metal of front deposit is aluminium, thickness 2.0-5.0um in 6；The metal of back side deposit is followed successively by titanium, nickel, silver metal layer, thickness
For 1.0~3.0um.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810288611.9A CN108493113A (en) | 2018-03-30 | 2018-03-30 | A kind of manufacturing method of low resistance Flouride-resistani acid phesphatase VDMOS chip |
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| CN201810288611.9A CN108493113A (en) | 2018-03-30 | 2018-03-30 | A kind of manufacturing method of low resistance Flouride-resistani acid phesphatase VDMOS chip |
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| CN108493113A true CN108493113A (en) | 2018-09-04 |
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| CN201810288611.9A Pending CN108493113A (en) | 2018-03-30 | 2018-03-30 | A kind of manufacturing method of low resistance Flouride-resistani acid phesphatase VDMOS chip |
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Cited By (1)
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| CN109559992A (en) * | 2018-10-16 | 2019-04-02 | 江苏万邦微电子有限公司 | A kind of manufacturing method of low resistance Flouride-resistani acid phesphatase VDMOS chip |
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