CN1147934C - Silicide full-automatic aligned chennel gate isolated gate bipolar transistor design and its preparation process - Google Patents
Silicide full-automatic aligned chennel gate isolated gate bipolar transistor design and its preparation processInfo
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- CN1147934C CN1147934C CNB021146748A CN02114674A CN1147934C CN 1147934 C CN1147934 C CN 1147934C CN B021146748 A CNB021146748 A CN B021146748A CN 02114674 A CN02114674 A CN 02114674A CN 1147934 C CN1147934 C CN 1147934C
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Abstract
The present invention discloses a technique for designing and manufacturing an insulating grid bipolar transistor (IGBT) of a full-automatic alignment groove grid. All the rest of photoetching is omitted except the photoetching of a P<+> plate and a groove grid plate in the whole set of the technique, namely to finish the device manufacture of the IGBT only by using twice photoetching. Besides, a registration photoetching relationship does not exist between twice photoetching, which avoids registration photoetching errors, enhances technique yields and reduces plate-making cost and manufacture cost. An IGBT multiple channel short circuit structure which is designed by the present invention efficiently prevents the IGBT from latching. Polysilicon etching and metal contact full-automatic alignment are realized by using an oxide layer hard mask and an advanced silicide technique, which makes a motokane dimension reduced to 2 mu m or even more smaller, increases the motokane density and the channel width of the unit area of the IGBT chip and enhances a current flow.
Description
One, technical field
The invention belongs to device architecture, layout design and manufacturing and the very lagre scale integrated circuit (VLSIC) technical study field of insulated gate semiconductor fieldtron, further relate to the preparation method that a kind of employing silicide fully self aligned prepares chennel gate isolated gate bipolar transistor (IGBT).
Two, background technology
Semiconductor power device is the main switching component of world today's field of power electronics, and igbt (IGBT) is wherein most important a member (hereinafter to be referred as IGBT).IGBT integrates bipolar and the two advantage of MOSFET, has both overcome the big shortcoming of MOSFET conducting resistance, the advantage that has kept its grid voltage to drive again.Because the special performance of IGBT never was interrupted the optimization research to its device architecture, designs and manufacturing process.Divide from the manufacturing process of IGBT, roughly be divided into planar technique and groove grid technique two big classes.Planar technique IGBT structure be occur the earliest, also be a kind of traditional structure that is most widely used till now, its manufacturing process and very lagre scale integrated circuit (VLSIC) are compatible fully, but its weak point is that unit's bag size is big, and are difficult for realizing the fully self aligned manufacturing.For this reason, groove grid IGBT occurred and the trend that progressively replaces planar structure has been arranged, the great advantage of groove grid IGBT is to have eliminated some ghost effect that is difficult to eliminate of planar structure such as J-FET effect, but early stage its yuan of groove grid IGBT bag size reduces and unit's bag density increases the restriction that is subjected to repeatedly photoetching and lithography registration.So, optimize the manufacturing process of groove grid IGBT, reduce reticle quantity and eliminate alignment between the figure, rather important to improving the IGBT fabrication yield.
Three, summary of the invention
Defective or deficiency according to above-mentioned prior art existence, the objective of the invention is to rely on the advanced manufacturing technology of very lagre scale integrated circuit (VLSIC), develop a kind of silicide fully self aligned groove grid IGBT design and preparation technology who has only Twi-lithography and do not have alignment, finish IGBT with minimum release and make.Like this, owing to eliminated the influence of repeatedly photoetching and alignment, thus the performance of IGBT is improved.
The present invention utilizes MOS device substrate ground connection to realize the structure of the multiple raceway groove short circuit of IGBT simultaneously in design, and this structure can be eliminated the latch-up of IGBT device effectively.
To achieve these goals, the technical solution used in the present invention is: a kind of preparation method of silicide fully self aligned chennel gate isolated gate bipolar transistor is characterized in that: may further comprise the steps:
1) chooses n type monocrystalline silicon as base material;
2) form p type silicon and n+ type silicon in the front of n type monocrystalline silicon respectively by twice material modification;
3) material modification of a plurality of local work of the n+ of photoetching for the first time type silicon becomes p+ type silicon; P+ type silicon is communicated with p type silicon at vertical p+ type silicon laterally being the equidistant strip figure of arranging;
4) adopt the low-pressure chemical vapor phase deposition oxide layer on the surface of n type silicon;
5) photoetching groove grid for the second time, the groove grid laterally also are being the equidistant strip figure of arranging, and with p+ type silicon quadrature;
6) utilize very lagre scale integrated circuit (VLSIC) plasma anisotropic etching technology to form remaining sio then at silicon chip surface step place
2Oxide sidewall spacers; When oxide sidewall spacers formed, the oxide layer on silicon and the polysilicon was also removed clean fully, and directly the contact hole as next step uses;
7) utilize the silicide technology of very lagre scale integrated circuit (VLSIC), by the oxide sidewall spacers of previous step form grid automatically, the source connects; After oxide sidewall spacers forms, at silicon chip surface large tracts of land depositing metal titanium Ti, at N
2Pyrolytic reaction in the atmosphere makes the place of silicon and polysilicon form C49 TiSi
2The high resistant silicide layer, and Ti and oxide sidewall spacers do not react;
8) remove unreacted metal Ti with the wet chemical selective etching; The high resistant silicide layer is carried out high annealing promptly be transformed into C54 TiSi
2The low resistance silicide metal connecting layer, its resistivity is about 14 μ Ω cm～18 μ Ω cm.
Other characteristics of the present invention are that described Twi-lithography carries out according to the following steps:
1). reticle is that two secondary ions inject on the basis of silicon materials in front for the first time, and the p+ silicon layer is injected in photoetching p+ district selectively, and this p+ silicon layer is communicated with the p silicon layer that injects for the first time, realizes the substrate ground connection of fully self aligned chennel gate isolated gate bipolar transistor device; After the groove grid vertical with p+ silicon layer figure form, form the multiple short-circuit structure of fully self aligned chennel gate isolated gate bipolar transistor raceway groove in the place of all p+ silicon layers and the connection of P silicon layer;
2). the groove of photoetching for the second time gate figure, the hard mask that utilizes the low-pressure chemical vapor phase deposition oxide layer to anti-carve, the no photoetching etching of realization polysilicon gate as polysilicon gate; This figure does not have alignment with litho pattern is vertical each other for the first time.
The method of described twice material modification is:
1) after modes such as process High temperature diffusion or ion injection were mixed the boron triad for the first time, silicon was hole conduction, and after mixing the phosphorus pentad, silicon is electron conduction;
2) for the second time silicon chip is carried out large-area material modification twice, adopt slot grid structure, in fully self aligned chennel gate isolated gate bipolar transistor device preparation process, the top layer implanted dopant boron of n type silicon face 1.5-2.0 μ m is become P type silicon, the top layer implanted dopant arsenic of more surperficial 0.5-1.0 μ m is become n type silicon.
Tool advance of the present invention, exploitativeness and practicality are in one, and a complete set of technology is except P
+Beyond version and two versions of groove grid version, all the other all photoetching all are removed, and have eliminated all alignment relations, thereby IGBT unit bag size is reduced greatly, have increased the unit's bag density and the channel width of unit are, have reduced the conducting resistance of device.As can be seen, because oxide sidewall spacers has formed grid, source articulamentum automatically.
Material modification of the present invention is according to semi-conductive conductivity principle, 1) mix the impurity of certain type through modes such as High temperature diffusion or ion injections after, resistivity obviously reduces, but becomes electric conducting material; According to the impurity difference of mixing in the silicon materials, the conduction type of silicon is also different, and after mixing triad such as boron, silicon is hole conduction, is called P type silicon, and after mixing pentad such as phosphorus, silicon is electron conduction, is called n type silicon; 2) silicon chip is carried out large-area material modification twice, adopt slot grid structure, in IGBT device preparation process, the top layer implanted dopant boron of the about 1.5-2.0 μ of n type silicon face m is become P type silicon, again the top layer implanted dopant arsenic of surface about 0.5-1.0 μ m is become n type silicon; 3) change the conduction type of silicon face thin layer twice, all need not carry out photoetching.
Owing to the present invention proposes the new construction of a kind of groove grid IGBT, only finished the manufacturing of IGBT device with two and the reticle of not having an alignment, whole manufacturing process all realizes autoregistration, reduced artificial factor in the device manufacturing processes, greatly optimized the manufacturing process of IGBT, simultaneously unit's bag size is contracted to 2 μ m, this reduces cost most important to increase IGBT single-chip current capacity, raising rate of finished products.
Four, description of drawings
Fig. 1 is groove grid IGBT top view of the present invention and schematic cross-section, and wherein 6 is silicon wafer top views of finishing after twice no photoetching mixed, and the sectional view corresponding with it is (d-d '), p
+Be communicated with section (c-c ') with p, corresponding raceway groove section after the cutting (a-a '), raceway groove short circuit section (b-b ');
Fig. 2 is that polysilicon of the present invention anti-carves, oxide sidewall spacers and silicide connection diagram.Fig. 2-a: polysilicon anti-carves, Fig. 2-b: remove hard mask oxide layer, Fig. 2-c: make side wall, Fig. 2-d: metal deposit, Fig. 2-e: form silicide.
Five, embodiment
For a more clear understanding of the present invention, the present invention is described in further detail below in conjunction with accompanying drawing and concrete execution mode.
Embodiment: referring to Fig. 1, Fig. 2, according to technical scheme of the present invention, the design and the preparation technology of silicide fully self aligned chennel gate isolated gate bipolar transistor of the present invention (IGBT) may further comprise the steps:
1) select n type silicon 1 as base material;
2) form p type silicon 2 and n+ type silicon 3 in the front of n type silicon 1 respectively by twice material modification, p type silicon 2 and n+ type silicon 3 be the surface 6 of whole base material laterally, at vertical sectional view referring to Fig. 1 (d-d ').
3) a plurality of parts of n+ type silicon 3 being remake a material modification becomes p+ type silicon 4, and p+ type silicon 4 is communicated with p type silicon 2 at vertical p+ type silicon 4 laterally be the equidistant strip figure of arranging, referring to the sectional view of Fig. 1 (c-c ').
4) in the surperficial low-pressure chemical vapor phase deposition deposited oxide layer 7 of n type silicon 1.
5) positive cutting 5, groove 5 laterally also is being the equidistant strip figure of arranging, and with p+ type silicon 4 quadratures, vertically seeing sectional view (a-a ') or (b-b ').
Its technical process is:
1. on n type monocrystalline silicon 1, inject formation p type layer 2 and n by two secondary ions
+Layer 3 corresponds respectively to substrate zone and the source area of IGBT, and it all is directly to carry out on silicon chip that this two secondary ion injects, without litho pattern.The surface 6 of base material is to finish the top view that above-mentioned two secondary ions inject the back silicon wafer, and its profile structure is shown in (d-d ') sectional view of Fig. 1;
2. first reticle is that two secondary ions inject on the basis of silicon wafer in front, photoetching p
+P is injected in district 4 selectively
+Layer.This p
+Layer is communicated with the p layer 2 (substrate of IGBT device) that injects for the first time, promptly realizes the substrate ground connection of IGBT device, and it is exactly to work as and p that p+ type silicon 4 also has an important function
+After the groove grid 5 that figure is vertical formed, every channel region 13 that has p+ type silicon 4 to be communicated with formed the multiple raceway groove short-circuit structure of so-called IGBT.This MOS of utilization device substrate ground connection is realized the structure of the multiple raceway groove short circuit of IGBT simultaneously, and this structure can be eliminated the latch-up of IGBT device effectively.
3. the hard mask that utilizes low-pressure chemical vapor phase deposition deposited oxide layer 7 to anti-carve as polysilicon gate, the no photoetching etching of realization polysilicon gate;
4. second reticle is exactly photoetching groove gate figure 5, and this figure is with for the first time litho pattern 4 is vertical each other, but do not have the relation between alignment and the feature size.
5. utilize very lagre scale integrated circuit (VLSIC) plasma anisotropic etching technology that the regional cutting 15 of groove gate figure is arranged at silicon chip surface.
6. growth of gate oxide layer, dry method growth oxide layer (sio
2) 8 (in Fig. 2 a, gate oxide is meant and is positioned at side, cutting district, the thin layer between polysilicon and the silicon, and the about 100nm of thickness only represents with a line among the figure, an attached circle indicates in order to avoid confusion).
7. utilize low-pressure chemical vapor phase deposition deposit polysilicon and autoregistration to anti-carve to hard mask oxide layer (sio
2) stop, all groove districts have promptly stayed final IGBT polysilicon gate 9.
8. remove hard mask oxide layer (sio
2) (Fig. 2 b), low-pressure chemical vapor phase deposition deposited oxide layer (sio
2), utilize very lagre scale integrated circuit (VLSIC) plasma anisotropic etching technology etching oxide layer to silicon face, at this moment form residual sio at the step place of all polysilicons and silicon
2Side wall is called oxide sidewall spacers (Fig. 2 c).
9. utilize the silicide of very lagre scale integrated circuit (VLSIC) to form technology, at the even depositing metal Ti of silicon chip surface large tracts of land (titanium) 11.At N
2In the atmosphere, pyrolytic reaction will take place in titanium and silicon, and pyrolytic reaction does not take place for Ti and oxide.Remove the metal Ti on oxide sidewall spacers surface with wet chemical selective etching technology, as can be seen, because oxide sidewall spacers has formed grid, source articulamentum 12 automatically.
Claims (3)
1. the preparation method of a silicide fully self aligned chennel gate isolated gate bipolar transistor is characterized in that: may further comprise the steps:
1) chooses n type monocrystalline silicon as base material;
2) form p type silicon and n+ type silicon in the front of n type monocrystalline silicon respectively by twice material modification;
3) material modification of a plurality of local work of the n+ of photoetching for the first time type silicon becomes p+ type silicon; P+ type silicon is communicated with p type silicon at vertical p+ type silicon laterally being the equidistant strip figure of arranging;
4) adopt the low-pressure chemical vapor phase deposition oxide layer on the surface of n type silicon;
5) photoetching groove grid for the second time, the groove grid laterally also are being the equidistant strip figure of arranging, and with p+ type silicon quadrature;
6) utilize very lagre scale integrated circuit (VLSIC) plasma anisotropic etching technology to form remaining sio then at silicon chip surface step place
2Oxide sidewall spacers; When oxide sidewall spacers formed, the oxide layer on silicon and the polysilicon was also removed clean fully, and directly the contact hole as next step uses;
7) utilize the silicide technology of very lagre scale integrated circuit (VLSIC), by the oxide sidewall spacers of previous step form grid automatically, the source connects; After oxide sidewall spacers forms, at silicon chip surface large tracts of land depositing metal titanium Ti, at N
2Pyrolytic reaction in the atmosphere makes the place of silicon and polysilicon form C49 TiSi
2The high resistant silicide layer, and Ti and oxide sidewall spacers do not react;
8) remove unreacted metal Ti with the wet chemical selective etching; The high resistant silicide layer is carried out high annealing promptly be transformed into C54 TiSi
2The low resistance silicide metal connecting layer, its resistivity is 14 μ Ω cm～18 μ Ω cm.
2. the preparation method of silicide fully self aligned chennel gate isolated gate bipolar transistor according to claim 1 is characterized in that, described Twi-lithography carries out according to the following steps:
1). reticle is that two secondary ions inject on the basis of silicon materials in front for the first time, and the p+ silicon layer is injected in photoetching p+ district selectively, and this p+ silicon layer is communicated with the p silicon layer that injects for the first time, realizes the substrate ground connection of fully self aligned chennel gate isolated gate bipolar transistor device; After the groove grid vertical with p+ silicon layer figure form, form the multiple short-circuit structure of fully self aligned chennel gate isolated gate bipolar transistor raceway groove in the place of all p+ silicon layers and the connection of P silicon layer;
2). the groove of photoetching for the second time gate figure, the hard mask that utilizes the low-pressure chemical vapor phase deposition oxide layer to anti-carve, the no photoetching etching of realization polysilicon gate as polysilicon gate; This figure does not have alignment with litho pattern is vertical each other for the first time.
3, the preparation method of silicide fully self aligned chennel gate isolated gate bipolar transistor according to claim 1 is characterized in that, the method for described twice material modification is:
1) after modes such as process High temperature diffusion or ion injection were mixed the boron triad for the first time, silicon was hole conduction, and after mixing the phosphorus pentad, silicon is electron conduction;
2) for the second time silicon chip is carried out large-area material modification twice, adopt slot grid structure, in fully self aligned chennel gate isolated gate bipolar transistor device preparation process, the top layer implanted dopant boron of n type silicon face 1.5-2.0 μ m is become P type silicon, the top layer implanted dopant arsenic of more surperficial 0.5-1.0 μ m is become n type silicon.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB021146748A CN1147934C (en) | 2002-07-15 | 2002-07-15 | Silicide full-automatic aligned chennel gate isolated gate bipolar transistor design and its preparation process |
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| CNB021146748A CN1147934C (en) | 2002-07-15 | 2002-07-15 | Silicide full-automatic aligned chennel gate isolated gate bipolar transistor design and its preparation process |
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| CN1147934C true CN1147934C (en) | 2004-04-28 |
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| CN101577241B (en) * | 2008-05-06 | 2011-06-01 | 上海华虹Nec电子有限公司 | Method for realizing isolation structure in preparation of mixed circuit of triode and MOS tube |
| CN102650609A (en) * | 2011-02-25 | 2012-08-29 | 赣南师范学院 | Microbiological detecting device |
| CN102403210B (en) * | 2011-11-29 | 2013-07-31 | 无锡中微晶园电子有限公司 | Process for self alignment of previously non-crystallized filled high temperature Ti on silicide |
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