CN104425250A - Manufacturing method of IGBT (Insulated Gate Bipolar Translator) - Google Patents
Manufacturing method of IGBT (Insulated Gate Bipolar Translator) Download PDFInfo
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- CN104425250A CN104425250A CN201310389640.1A CN201310389640A CN104425250A CN 104425250 A CN104425250 A CN 104425250A CN 201310389640 A CN201310389640 A CN 201310389640A CN 104425250 A CN104425250 A CN 104425250A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 34
- 239000004065 semiconductor Substances 0.000 claims abstract description 46
- 238000000034 method Methods 0.000 claims abstract description 39
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 229910052751 metal Inorganic materials 0.000 claims abstract description 14
- 239000002184 metal Substances 0.000 claims abstract description 14
- 230000008569 process Effects 0.000 claims abstract description 12
- 239000012535 impurity Substances 0.000 claims abstract description 9
- 238000011049 filling Methods 0.000 claims abstract description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 238000001259 photo etching Methods 0.000 claims description 6
- 238000002513 implantation Methods 0.000 claims description 5
- 238000001039 wet etching Methods 0.000 claims description 5
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 238000005498 polishing Methods 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 2
- 239000000463 material Substances 0.000 abstract description 3
- 238000002347 injection Methods 0.000 abstract description 2
- 239000007924 injection Substances 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 13
- 229910052710 silicon Inorganic materials 0.000 description 13
- 239000010703 silicon Substances 0.000 description 13
- 239000000203 mixture Substances 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 4
- 230000004913 activation Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 108090000723 Insulin-Like Growth Factor I Proteins 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 102000013275 Somatomedins Human genes 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
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- 230000009977 dual effect Effects 0.000 description 1
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- 238000005530 etching Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
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- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
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- 229910052698 phosphorus Inorganic materials 0.000 description 1
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- 238000011084 recovery Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
- H01L29/0834—Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Manufacturing & Machinery (AREA)
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Abstract
The invention provides a manufacturing method of an IGBT (Insulated Gate Bipolar Translator). The manufacturing method comprises the following steps: providing a first conductive type semiconductor wafer with a first surface and a second surface; carrying out impurity injection on the first surface of the semiconductor wafer to form conductive layers; forming separated grooves in the surfaces of the conductive layers; filling second conductive type or first conductive type semiconductor materials into the grooves to form channels; forming an oxidized layer on the conductive layers and the channels; bonding a substrate semiconductor wafer on the oxidized layer; thinning the semiconductor wafer and taking the thinned semiconductor wafer as a drift region; forming a front surface structure of the IGBT based on the drift region; removing the substrate semiconductor wafer; removing the oxidized layer; forming a back surface metal electrode on the channels and the conductive layers. The method has no special requirements on a thin sheet flow capacity and double-faced exposure machine equipment is not needed; the manufacturing method is compatible with an existing conventional process and is simple in process and high in efficiency.
Description
[technical field]
The present invention relates to semiconductor design and manufacturing technology field, particularly a kind of IGBT(Insulated GateBipolar Transistor, igbt) manufacture method.
[background technology]
IGBT is by BJT(Bipolar Junction Transistor, bipolar junction transistor) and MOSFET(Metal-Oxide-Semiconductor-Field-Effect-Transistor, mos field effect transistor) the compound full-control type voltage driven type power semiconductor that forms, have the advantage of the high input impedance of MOSFET and low conduction voltage drop two aspect of BJT concurrently, there is operating frequency high, control circuit is simple, current density is high, on-state such as to force down at the feature, is widely used in power control field.In actual applications, IGBT seldom uses as an individual devices, and especially under the condition of inductive load, IGBT needs a fast recovery diode afterflow.Therefore, existing igbt product, the general fly-wheel diode in parallel (Freewheeling diode is called for short FWD) that adopts is to protect IGBT.In order to reduce costs, fly-wheel diode in parallel can be integrated in igbt chip, namely has the IGBT of diode-built-in or reverse-conducting.
The IGBT of common reverse-conducting needs thinning rear dual surface lithography to prepare the injection window of P+ collector area, the back side.The shortcoming of this scheme mainly contains two aspects: the first, need thinned wafer negotiability, and particularly for the IGBT of common below 1200V, its thickness, at below 200um, requires very high to thin slice flow-through process; The second, need special sided exposure machine to exposing wafer.In addition, the IGBT of existing reverse-conducting adopts back side Twi-lithography technology usually.
Therefore, be necessary to provide a kind of technical scheme of improvement to overcome the problems referred to above.
[summary of the invention]
The object of the present invention is to provide the manufacture method of a kind of IGBT, itself and existing common process are compatible, and technique is simple, efficiency is high, greatly reduce process costs without the need to special equipment.
In order to solve the problem, according to an aspect of the present invention, the invention provides the manufacture method of a kind of IGBT, it comprises: the semiconductor wafer providing first conduction type with first surface and second surface, the first surface of described semiconductor wafer carries out impurity and injects with the conductive layer forming the first conduction type or the second conduction type; At the groove at the formation interval, surface of the conductive layer of described first conduction type or the second conduction type; In described groove, fill the semi-conducting material of the second conduction type or the first conduction type to form passage, the conduction type of wherein said passage is different from the conduction type of described conductive layer, now described passage and the arrangement of described conductive layer interleaved; Described conductive layer and passage form oxide layer; Bonded substrate semiconductor wafer in described oxide layer; From the thinning described semiconductor wafer of the second surface of described semiconductor wafer, and using the semiconductor wafer of the first conduction type after thinning as drift region; The Facad structure of described IGBT is formed based on described drift region; Remove described substrate semiconductor wafer; Remove described oxide layer; Described passage and conductive layer are formed back metal electrode, this back metal electrode and described passage and conductive layer in electrical contact.
As a preferred embodiment of the present invention, the thickness of the described semiconductor wafer provided is 200-700um, and resistivity is 5 ~ 500 Ω * cm.
As a preferred embodiment of the present invention, the implantation dosage that the first surface of described semiconductor wafer injects conductive layer is 1E13 ~ 1E20cm
-2, energy is 30 ~ 200KEV.
As a preferred embodiment of the present invention, by photoetching, the groove of etch process at the formation interval, surface of the conductive layer of described first conduction type or the second conduction type.
As a preferred embodiment of the present invention, the degree of depth of described groove is 0.5 ~ 50um.
As a preferred embodiment of the present invention, after the semi-conducting material of filling second conduction type or the first conduction type, the semi-conducting material of filling is made to become monocrystalline silicon by high-temperature step, subsequently by the first surface of the smooth described substrate of CMP (Chemical Mechanical Polishing) process.
As a preferred embodiment of the present invention, form oxide layer by thermal oxidation or CVD mode on described conductive layer and passage, the thickness of described oxide layer is 0.01-5um.
As a preferred embodiment of the present invention, in described oxide layer, the thickness of the described substrate semiconductor wafer of bonding is 50-650um.
As a preferred embodiment of the present invention, before the Facad structure forming described IGBT based on described drift region, described manufacture method also comprises:
By CMP or the smooth second surface to described thinning described semiconductor wafer of wet etching mode.
As a preferred embodiment of the present invention, the thickness of the drift region that the thickness of described substrate semiconductor wafer and described bonding are formed and be the semiconductor wafer thickness that normally circulates.
Compared with prior art, the manufacture method of IGBT in the present invention, first the spaced collector area at the back side of IGBT and the making of passage is completed, the Facad structure of IGBT is prepared afterwards on semiconductor wafer second surface, only need to do thinning and back face metalization step after Facad structure completes, particular/special requirement is not had to thin slice negotiability, does not more need double-sided exposure machine equipment.
[accompanying drawing explanation]
In order to be illustrated more clearly in the technical scheme of the embodiment of the present invention, below the accompanying drawing used required in describing embodiment is briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.Wherein:
Fig. 1 is the manufacture method flow chart in one embodiment of the IGBT in the present invention;
Fig. 2 to Figure 11 is the vertical section schematic diagram that each manufacturing process of manufacture method in Fig. 1 obtains wafer.
[embodiment]
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, and below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation.
Alleged herein " embodiment " or " embodiment " refers to special characteristic, structure or the characteristic that can be contained at least one implementation of the present invention.Different local in this manual " in one embodiment " occurred not all refers to same embodiment, neither be independent or optionally mutually exclusive with other embodiments embodiment.
Before the manufacture method introducing the IGBT in the present invention, it should be noted that, the emitter of IGBT and the face at grid place are understood to front usually, and the face at the collector electrode place of IGBT is understood reverse side or the back side usually.Semiconductor wafer huge number, conventional is silicon chip, below in embodiment, will for silicon chip.
Fig. 1 is manufacture method 100 flow chart in one embodiment of the IGBT in the present invention.As shown in Figure 1, described manufacture method 100 comprises the steps.
Step 110, shown in composition graphs 2, provides the N-type silicon chip 10 with first surface 11 and second surface 12, and the first surface 11 of described silicon chip carries out the conductive layer 13 that impurity injects N-type or P type.
Concrete, the thickness of described silicon chip 10 can be 200 ~ 700um, and resistivity can be 5 ~ 500 Ω * cm.As shown in Figure 2, the first surface 11 of described silicon chip 10 does general note, the impurity implantation dosage of conductive layer 13 is 1E13 ~ 1E20cm
-2, energy is 30 ~ 200KEV, and described impurity can be donor impurity, as phosphorus or arsenic etc., can be also acceptor impurity, as boron or hydrogen etc.
Step 120, as shown in Figure 3, by photoetching, the groove 25 of etch process at the formation interval, surface of the conductive layer 13 of N-type or P type.
Concrete, the degree of depth of described groove 25 can be 0.5 ~ 50um.
Step 130, shown in composition graphs 4, in described groove 25, filling N-type or P type semiconductor material are to form N-type or P type passage 14.
When described conductive layer 13 is P type, form N-type passage in described step 130, when described conductive layer 13 is N-type, form P type passage in described step 130, conduction type is between the two contrary.In the embodiment shown by Fig. 2-11, with conductive layer 13 for N-type, passage 14 for P type be that example is introduced.Concrete, as shown in Figure 3, P type semiconductor material (such as monocrystalline silicon, polysilicon, amorphous silicon) is filled in described groove 25, its resistivity is 0.001 ~ 50 Ω * cm, make the semi-conducting material of filling become monocrystalline silicon by high-temperature step thus obtain the P type passage 14 after activating, subsequently by the surface of the smooth described conductive layer 13 of chemico-mechanical polishing (CMP) technique.Photoresist 30 in figure 3 can be removed in appropriate steps.
The activation of the P type passage 14 in existing technique usually occurs in after front metal electrode formed, and the activation step in the present invention all occurs in before metal electrode formed, and improves the activation efficiency of doped region (such as P type passage 14).
Step 140, shown in composition graphs 5, described conductive layer 13 and passage 14 forms oxide layer 15.
Concrete, after having injected, remove photoresist cleaning conductive layer 13 and passage 14 surface, form by thermal oxidation or CVD mode the oxide layer 15 that a thickness is 0.01-5um, to play the effect of protection conductive layer 13 and passage 14 on described conductive layer 13 and passage 14.
Step 150, shown in composition graphs 6, overturns described silicon chip 10, the substrate 16 of bonding P type or N-type in described oxide layer 15.The thickness of described substrate 16 is relevant to the thickness of the bonding drift region hereafter mentioned.
Concrete, adopt Direct Bonding (SDB) mode by substrate 16 bonding of described oxide layer 15 and N-type or P type, the thickness of substrate 16 is 50 ~ 650um.
Step 160, shown in composition graphs 7, from the thinning described silicon chip 10 of the second surface 12 of described silicon chip 10, and by the described silicon chip 10 after thinning, as N-type drift region (N Drift) 17.
Concrete, the thickness of the drift region 17 of thinning formation is relevant to the thickness of described substrate 16.The thickness of described substrate 16 and the thickness of described drift region 17 and be the silicon wafer thickness that normally circulates, the normal thickness such as 6 cun of sheets is 625um/675um, and the normal thickness of 8 cun of sheets is 725um.
After thinning completing, CMP or wet etching mode is adopted to make second surface 12 flat-satin of described silicon chip 10.
Step 170, shown in composition graphs 8, adopts normal IGBT technological process to form the Facad structure of described IGBT based on described drift region 17.
The Facad structure of a kind of planar I GBT is illustrated in Fig. 8.The Facad structure of described IGBT comprises: the P type base (P-body) 18 selectively formed on the upper surface of described drift region 17, the N-type emitter region 19 selectively formed in described P type base 18, be positioned at the gate oxide 20 on the upper surface of described drift region 17, the polysilicon gate 21 (G) that described grid oxic horizon 20 is formed, cover the dielectric layer 22 of described grid oxic horizon 20 and polysilicon gate 21, and with described P type base 18 and described N-type emitter region 19 front metal electrode 23 (i.e. emitter E) in electrical contact.
Just schematically illustrate front metal electrode 23 in Fig. 8, in fact, front metal electrode 23 may cover whole dielectric layer 22.In addition, the Facad structure of described IGBT also may comprise the passivation layer (not shown) be formed at outside front metal electrode 23, such as silicon dioxide and silicon nitride.
In other embodiments, can manufacture groove-shaped IGBT, the described Facad structure of groove-shaped IGBT is not identical with the Facad structure of the IGBT in Fig. 8, but has disclosed a lot of groove-shaped IGBT in prior art yet, here just no longer repeated description.Need to know, from certain angle of the present invention, the present invention is not concerned about the concrete Facad structure of IGBT especially, as long as have Facad structure and can form operable IGBT device.
The present invention proposes an example of the manufacturing process of the Facad structure of the IGBT in a kind of Fig. 8, and this flow process comprises:
Step one, growth grid oxic horizon, such as thickness is
Step 2, on grid oxic horizon, generate polycrystalline silicon gate layer, such as thickness is
Step 3, polysilicon gate photoetching, etching, ion implantation, push away trap to form P base, p type impurity implantation dosage is 1E12 ~ 1E15cm
-2, Implantation Energy is 20KEV ~ 1MEV; Pushing away trap temperature is 1000 ~ 1250C, and the time is 10min ~ 1000min.
Step 4, the photoetching of N-type emitter region, ion implantation, annealing are to form N-type, and dosage 1E14 ~ 1E16, energy is 20KEV ~ 1MEV cm
-2; Annealing temperature is 800 ~ 1000C, and the time is 10min ~ 1000min;
Step 5, somatomedin layer, thickness:
Step 6, contact hole photoetching, be etched with formation contact hole, this contact hole communicates with described N-type emitter region and P type base;
Step 7, front metal layer deposit, thickness is about 2um ~ 6um;
Step 8, passivation layer deposit.
From another angle, about the concrete manufacturing process of the Facad structure of IGBT does not belong to emphasis of the present invention yet, it can adopt existing various manufacturing process manufacture to form, therefore in order to outstanding emphasis of the present invention, about the concrete manufacturing process of the Facad structure of IGBT is not described in detail in this article.
Step 180, shown in composition graphs 9, removes described substrate 16.
In one embodiment, after the Facad structure of IGBT completes, carry out thinning, by grinding (Grinding) technique after being thinned to certain thickness to described substrate 16, described substrate 16 is removed further, until expose described oxide layer 15 with wet etching.
Step 190, shown in Figure 10, removes described oxide layer 15.
In one embodiment, after described substrate 16 is removed completely, continue to adopt wet etching described oxide layer 15 all to be removed.
Step 200, shown in Figure 11, by adopting the mode of sputtering or evaporation to obtain back metal electrode (collector electrode C) 24 outside described conductive layer 13 and passage 14, this back metal electrode 24 and described passage 14 and described conductive layer 13 in electrical contact.
What the those of ordinary skill in affiliated field should be understood that is, one of feature of the present invention or object are: first complete the spaced N-type collector area at the back side of IGBT and the making of P type passage, the Facad structure of IGBT is prepared afterwards on the second surface 12 of silicon chip 10, only need to do thinning and back face metalization step after Facad structure completes, like this particular/special requirement be there is no to thin slice negotiability, more do not need double-sided exposure machine equipment.
N-type in above-described embodiment can be called as the first conduction type, and P type can be called as the second conduction type.In other embodiments, the region (such as P base, P type collector area) of the involved all P types in above-described embodiment can change to N-type, the region (N-type drift region, N-type emitter region, N-type cathodic region) of all N-types can change to P type, now can think that the first conduction type is P type, the second conduction type is N-type.
It is pointed out that the scope be familiar with person skilled in art and any change that the specific embodiment of the present invention is done all do not departed to claims of the present invention.Correspondingly, the scope of claim of the present invention is also not limited only to previous embodiment.
Claims (10)
1. a manufacture method of IGBT, is characterized in that, it comprises:
The semiconductor wafer of first conduction type with first surface and second surface is provided, the first surface of described semiconductor wafer carries out impurity and injects with the conductive layer forming the first conduction type or the second conduction type;
At the groove at the formation interval, surface of the conductive layer of described first conduction type or the second conduction type;
In described groove, fill the semi-conducting material of the second conduction type or the first conduction type to form passage, the conduction type of wherein said passage is different from the conduction type of described conductive layer, now described passage and the arrangement of described conductive layer interleaved;
Described conductive layer and passage form oxide layer;
Bonded substrate semiconductor wafer in described oxide layer;
From the thinning described semiconductor wafer of the second surface of described semiconductor wafer, and using the semiconductor wafer of the first conduction type after thinning as drift region;
The Facad structure of described IGBT is formed based on described drift region;
Remove described substrate semiconductor wafer;
Remove described oxide layer;
Described passage and conductive layer are formed back metal electrode, this back metal electrode and described passage and conductive layer in electrical contact.
2. the manufacture method of IGBT according to claim 1, is characterized in that, the thickness of the described semiconductor wafer provided is 200-700um, and resistivity is 5 ~ 500 Ω * cm.
3. the manufacture method of IGBT according to claim 1, is characterized in that, the implantation dosage that the first surface of described semiconductor wafer injects conductive layer is 1E13 ~ 1E20cm
-2, energy is 30 ~ 200KEV.
4. the manufacture method of IGBT according to claim 1, is characterized in that, by photoetching, the groove of etch process at the formation interval, surface of the conductive layer of described first conduction type or the second conduction type.
5. the manufacture method of IGBT according to claim 4, is characterized in that, the degree of depth of described groove is 0.5 ~ 50um.
6. the manufacture method of IGBT according to claim 4, it is characterized in that, after the semi-conducting material of filling second conduction type or the first conduction type, the semi-conducting material of filling is made to become monocrystalline silicon by high-temperature step, subsequently by the first surface of the smooth described substrate of CMP (Chemical Mechanical Polishing) process.
7. the manufacture method of IGBT according to claim 1, is characterized in that, forms oxide layer by thermal oxidation or CVD mode on described conductive layer and passage, and the thickness of described oxide layer is 0.01-5um.
8. the manufacture method of IGBT according to claim 1, is characterized in that, in described oxide layer, the thickness of the described substrate semiconductor wafer of bonding is 50-650um.
9. the manufacture method of IGBT according to claim 1, is characterized in that, before the Facad structure forming described IGBT based on described drift region, described manufacture method also comprises:
By CMP or the smooth second surface to described thinning described semiconductor wafer of wet etching mode.
10. the manufacture method of IGBT according to claim 1, is characterized in that, the thickness of the drift region that the thickness of described substrate semiconductor wafer and described bonding are formed and be the semiconductor wafer thickness that normally circulates.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310389640.1A CN104425250A (en) | 2013-08-30 | 2013-08-30 | Manufacturing method of IGBT (Insulated Gate Bipolar Translator) |
| PCT/CN2014/085301 WO2015027920A1 (en) | 2013-08-30 | 2014-08-27 | Method for manufacturing insulated-gate bipolar transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310389640.1A CN104425250A (en) | 2013-08-30 | 2013-08-30 | Manufacturing method of IGBT (Insulated Gate Bipolar Translator) |
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| CN104425250A true CN104425250A (en) | 2015-03-18 |
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| CN201310389640.1A Pending CN104425250A (en) | 2013-08-30 | 2013-08-30 | Manufacturing method of IGBT (Insulated Gate Bipolar Translator) |
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| WO (1) | WO2015027920A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109244125A (en) * | 2017-06-29 | 2019-01-18 | 万国半导体(开曼)股份有限公司 | Introduce the reverse conduction IGBT and preparation method thereof in epitaxial layer field stop area |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116314309B (en) * | 2023-05-23 | 2023-07-25 | 四川奥库科技有限公司 | Back gate structure of reverse-conduction IGBT device and processing method thereof |
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| US20100140658A1 (en) * | 2008-12-10 | 2010-06-10 | Denso Corporation | Method of manufacturing semiconductor device including insulated gate bipolar transistor and diode |
| US20120178223A1 (en) * | 2011-01-07 | 2012-07-12 | Kabushiki Kaisha Toshiba | Method of Manufacturing High Breakdown Voltage Semiconductor Device |
| CN102983160A (en) * | 2012-12-26 | 2013-03-20 | 无锡凤凰半导体科技有限公司 | Insulated gate bipolar transistor |
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| CN103268860A (en) * | 2013-04-03 | 2013-08-28 | 吴宗宪 | Manufacturing method of IGBT (insulated gate bipolar transistor) device integrated with diode |
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| DE102011079747A1 (en) * | 2010-07-27 | 2012-02-02 | Denso Corporation | Semiconductor device with switching element and freewheeling diode, and control method therefor |
| JP5995435B2 (en) * | 2011-08-02 | 2016-09-21 | ローム株式会社 | Semiconductor device and manufacturing method thereof |
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| US20100140658A1 (en) * | 2008-12-10 | 2010-06-10 | Denso Corporation | Method of manufacturing semiconductor device including insulated gate bipolar transistor and diode |
| US20120178223A1 (en) * | 2011-01-07 | 2012-07-12 | Kabushiki Kaisha Toshiba | Method of Manufacturing High Breakdown Voltage Semiconductor Device |
| CN103137472A (en) * | 2011-11-25 | 2013-06-05 | 上海华虹Nec电子有限公司 | Method for manufacturing insulated gate bipolar transistor (IGBT) component combined with fast recovery diode (FRD) |
| CN102983160A (en) * | 2012-12-26 | 2013-03-20 | 无锡凤凰半导体科技有限公司 | Insulated gate bipolar transistor |
| CN103268860A (en) * | 2013-04-03 | 2013-08-28 | 吴宗宪 | Manufacturing method of IGBT (insulated gate bipolar transistor) device integrated with diode |
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| CN109244125A (en) * | 2017-06-29 | 2019-01-18 | 万国半导体(开曼)股份有限公司 | Introduce the reverse conduction IGBT and preparation method thereof in epitaxial layer field stop area |
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