CN108063166A - A kind of groove structure Schottky semiconductor device and preparation method thereof - Google Patents
A kind of groove structure Schottky semiconductor device and preparation method thereof Download PDFInfo
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- CN108063166A CN108063166A CN201610986208.4A CN201610986208A CN108063166A CN 108063166 A CN108063166 A CN 108063166A CN 201610986208 A CN201610986208 A CN 201610986208A CN 108063166 A CN108063166 A CN 108063166A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 149
- 238000002360 preparation method Methods 0.000 title claims abstract description 9
- 239000000463 material Substances 0.000 claims abstract description 65
- 239000012774 insulation material Substances 0.000 claims description 52
- 239000004020 conductor Substances 0.000 claims description 49
- 239000002184 metal Substances 0.000 claims description 43
- 229910052751 metal Inorganic materials 0.000 claims description 43
- 239000000758 substrate Substances 0.000 claims description 40
- 230000004888 barrier function Effects 0.000 claims description 38
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 30
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 30
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 24
- 229920005591 polysilicon Polymers 0.000 claims description 24
- 239000011810 insulating material Substances 0.000 claims description 18
- 238000005530 etching Methods 0.000 claims description 13
- 239000012535 impurity Substances 0.000 claims description 13
- 238000002161 passivation Methods 0.000 claims description 12
- 238000001312 dry etching Methods 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 9
- 238000001465 metallisation Methods 0.000 claims description 6
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 4
- 230000000903 blocking effect Effects 0.000 abstract description 11
- 230000005684 electric field Effects 0.000 abstract description 5
- 239000002210 silicon-based material Substances 0.000 description 24
- 230000001413 cellular effect Effects 0.000 description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 18
- 125000004437 phosphorous atom Chemical group 0.000 description 17
- 238000011049 filling Methods 0.000 description 10
- 239000000377 silicon dioxide Substances 0.000 description 9
- 238000004519 manufacturing process Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- 238000010276 construction Methods 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66143—Schottky diodes
Abstract
The invention discloses a kind of groove structure Schottky semiconductor devices, and width groove up and down is set in drift layer, optimizes the reverse leakage current under semiconductor device reverse biased and reverse blocking pressure drop, multiple peak value electric fields are formed in drift layer, reduces conducting resistance；The groove structure Schottky semiconductor device of the present invention sets the second conducting semiconductor material of charge compensation abutting against narrow trench sidewall area, improves reverse blocking pressure drop, reduce channel bottom electric field across oxide, improve reverse blocking reliability.The present invention also provides a kind of preparation methods of groove structure Schottky semiconductor device.
Description
Technical field
The present invention relates to a kind of groove structure Schottky semiconductor devices, and the invention further relates to a kind of groove structure Xiao Te
The preparation method of based semiconductor device.
Background technology
Power semiconductor rectifying device is widely used on power management, has been related specifically to Schottky semiconductor device
As the important trend of device development, schottky device has many advantages, such as that the low turn-off speed of opening of positive cut-in voltage is fast, simultaneously
Schottky device also has the shortcomings that the special and higher conducting resistance of poor reverse blocking.
It is used to improve the reverse blocking voltage of Schottky there has been proposed new construction, a kind of new construction is in schottky device table
Face introduces P-type conduction material, improves the reverse BV and leakage current characteristic of device, while also in device forward conduction
Few son is introduced, reduces the switch performance of device；Second class new construction introduces groove MIS structure in device surface, by by table
Inside the potential introduction means of face, the pressure drop of device reverse blocking is improved with this or reduces conducting resistance, the method is in schottky junction
Surface potential and reverse blocking pressure drop cannot take into account very well, and the method sets insulating materials in device so that device it is reliable
Property is affected；Three classes new construction introduces P-type conduction material in device, changes drift region electric field with this, improves device
Reverse BV because needing multiple extension manufacturing process, brings the manufacturing process of device complicated and manufacture cost greatly raises
The problem of.
The content of the invention
The present invention provides a kind of groove structure Schottky semiconductor device and its preparation for said one or multiple problems
Method.
A kind of groove structure Schottky semiconductor device, substrate layer are formed for the first conducting semiconductor material, are high concentration
Impurity adulterates；Drift layer is formed for the first conducting semiconductor material；Multiple width grooves, positioned at drift layer surface, inner wall sets exhausted
Edge material layer；Multiple narrow grooves, positioned at wide trench bottom surfaces, inner wall sets insulation material layer, and narrow trench wall includes setting
Heavy insulation material layer；Wide groove or narrow lower trench are provided with the second conducting semiconductor material or wide groove and narrow groove
Bottom is provided with heavy insulation material layer；Lower part, which is provided in the second insulation material layer or narrow groove, in narrow groove is provided with
In two insulation material layers or wide groove the second insulation material layer, the second insulation material layer are provided in lower part and narrow groove
Different from trench wall insulation material layer, including for nitride, ceramics etc.；Narrow channel bottom includes being located in substrate layer；It is conductive
Material is polysilicon, amorphous silicon or metal, including setting p-type polysilicon material, in wide groove or positioned at wide ditch
In slot and narrow groove；Schottky barrier junction, layer surface of drifting about between wide groove；Electrode metal, on semiconductor device
Lower surface, upper surface electrode metal connection conductive material and schottky barrier junction.
A kind of preparation method of groove structure Schottky semiconductor device adulterates the first conductive semiconductor in high concentration impurities
On the substrate layer that material is formed, by being epitaxially-formed the first conducting semiconductor material drift layer；Passivation layer is formed on surface,
For silicon nitride layer, in wide trench region surface removal passivation layer to be formed, semi-conducting material is performed etching, forms shallow wide groove；
It is aoxidized in the trench, forms semi-conducting material thick oxide layer, dry etching removal channel bottom oxide layer, dry etching half
Conductor material forms narrow groove；The wide trench wall oxide layer of removal, carries out thermal oxide, and oxygen is formed in wide groove and narrow trench wall
Change layer, form silicon nitride layer in the trench, removal drift layer surface is all divided silicon nitride layer with trench interiors, in the trench and floated
It moves layer surface and forms conductive material, etching conductive material removes drift layer surface conductance material；Xiao Te is formed in drift layer surface
Base barrier junction, carry out upper and lower surface metallization, formed upper and lower surface electrode metal, upper surface electrode metal connection conductive material and
Schottky barrier junction.
A kind of groove structure Schottky semiconductor device, substrate layer are formed for the first conducting semiconductor material, are high concentration
Impurity adulterates；Drift layer is formed for the first conducting semiconductor material；Multiple width grooves, positioned at drift layer surface, inner wall sets exhausted
Edge material layer；Multiple narrow grooves, positioned at wide trench bottom surfaces, inner wall sets insulation material layer, and narrow trench wall includes setting
Heavy insulation material layer abuts against narrow trench sidewall area and sets the second conducting semiconductor material；Lower part is provided with second in narrow groove
It is provided in insulation material layer or narrow groove in the second insulation material layer or wide groove and is set in lower part and narrow groove
There is the second insulation material layer, the second insulation material layer is different from trench wall insulation material layer, including for nitride, ceramics etc.；
Narrow channel bottom includes being provided with the second conducting semiconductor material；Narrow channel bottom includes being located in substrate layer；Conductive material is
Polysilicon, amorphous silicon or metal, including setting p-type polysilicon material, in wide groove or positioned at wide groove and narrow
In groove；Schottky barrier junction, layer surface of drifting about between wide groove；Electrode metal, positioned at semiconductor device upper and lower surface,
Upper surface electrode metal connects conductive material and schottky barrier junction.
A kind of preparation method of groove structure Schottky semiconductor device adulterates the first conductive semiconductor in high concentration impurities
By being epitaxially-formed the first conducting semiconductor material drift layer on the substrate layer that material is formed；Passivation layer is formed on surface,
For silicon nitride layer, in wide trench region surface removal passivation layer to be formed, semi-conducting material is performed etching, forms shallow wide groove；
It is aoxidized in the trench, forms semi-conducting material thick oxide layer, dry etching removal channel bottom oxide layer, dry etching half
Conductor material forms narrow groove, and small angle inclination injects the second conductive impurity or orientation epitaxial growth, abutting against narrow channel side
Wall region forms the second conducting semiconductor material；The wide trench wall oxide layer of removal, carries out thermal oxide, in wide groove and narrow groove
Inner wall forms oxide layer, forms silicon nitride layer in the trench, and removal drift layer surface all divides silicon nitride layer with trench interiors,
In groove and drift layer surface forms conductive material, and etching conductive material removes drift layer surface conductance material；In drift layer table
Face forms schottky barrier junction, carries out upper and lower surface metallization, forms upper and lower surface electrode metal, the connection of upper surface electrode metal
Conductive material and schottky barrier junction.
The groove structure Schottky semiconductor device of the present invention does not introduce PN junction in drift layer surface, in forward conduction,
Few son is formed not in drift layer；The groove structure Schottky semiconductor device of the present invention sets width ditch up and down in drift layer
Slot optimizes the reverse leakage current under semiconductor device reverse biased and reverse blocking pressure drop, groove structure Schottky of the invention
Semiconductor device can form multiple peak value electric fields in drift layer under reverse bias, and conducting resistance is reduced with this；The ditch of the present invention
Slot structure Schottky semiconductor device is abutting against narrow trench sidewall area setting the second conducting semiconductor material of charge compensation, improves
Reverse blocking pressure drop reduces channel bottom electric field across oxide, reverse blocking reliability is improved, wherein the second conducting semiconductor material
Including being connected to form PN junction with substrate layer, device reverse blocking anti-static ability is improved with this；The groove structure Xiao Te of the present invention
The manufacturing method flow of based semiconductor device is simple, and the manufacture of cellular is realized by a photoetching process.
Description of the drawings
Fig. 1 is the Schottky semiconductor device cellular section signal that bottom sets the second insulating materials in groove of the present invention
Figure.
Fig. 2 is the groove structure Schottky semiconductor device cellular diagrammatic cross-section of the present invention.
Fig. 3 is the Schottky semiconductor device cellular section signal that the narrow trench wall of the present invention sets heavy insulation material layer
Figure.
Fig. 4 is the structure Schottky semiconductor device cellular section signal that channel bottom of the present invention sets heavy insulation material layer
Figure.
Fig. 5 is the Schottky semiconductor device cellular diagrammatic cross-section that the narrow channel bottom of the present invention is arranged in substrate layer.
Fig. 6 is that the Schottky semiconductor device cellular that the narrow lower trench of the present invention is arranged at the second conducting semiconductor material cuts open
Face schematic diagram.
Fig. 7 is the Schottky semiconductor device cellular section that the wide lower trench of the present invention sets the second conducting semiconductor material
Schematic diagram.
Fig. 8 is the Schottky semiconductor device cellular section that lower trench of the present invention is arranged at the second conducting semiconductor material
Schematic diagram.
Fig. 9 is that lower part sets the Schottky semiconductor device cellular section signal that polysilicon is lightly doped in groove of the present invention
Figure.
Figure 10 is that the narrow trenched side-wall of the present invention abuts against the charge compensation Schottky that region sets the second conducting semiconductor material
Semiconductor device cellular diagrammatic cross-section.
Figure 11 is that the charge compensation Schottky semiconductor device cellular of the second insulating materials of lower part in the wide groove of the present invention cuts open
Face schematic diagram.
Figure 12 is a kind of charge compensation Schottky semiconductor dress that lower part sets the second insulating materials in the narrow groove of the present invention
Put cellular diagrammatic cross-section.
Figure 13 is the charge compensation Schottky semiconductor device cellular section signal that the narrow groove of the present invention is located in drift layer
Figure.
Figure 14 is a kind of charge compensation Schottky semiconductor dress that lower part sets the second insulating materials in the narrow groove of the present invention
Put cellular diagrammatic cross-section.
Figure 15 is that the narrow trench wall of the present invention abuts against the charge compensation Schottky that region sets the second conducting semiconductor material
Semiconductor device cellular diagrammatic cross-section.
Figure 16 is a kind of charge compensation Schottky semiconductor dress that lower part sets the second insulating materials in the narrow groove of the present invention
Put cellular diagrammatic cross-section.
Figure 17 is a kind of charge compensation Xiao that the narrow trench wall of the present invention orients the second conducting semiconductor material of epitaxial growth
Special based semiconductor device cellular diagrammatic cross-section.
Wherein, 1, substrate layer；2nd, drift layer；3rd, schottky barrier junction；4th, insulation material layer；5th, the second insulating materials；6、
Second conducting semiconductor material；7th, conductive material；8th, heavily doped polysilicon；9th, polysilicon is lightly doped；10th, upper surface electrode gold
Belong to；11st, lower surface electrode metal.
Specific embodiment
Embodiment 1
Fig. 1 shows that bottom sets the Schottky semiconductor device section of the second insulating materials to illustrate in groove of the present invention
Figure, with reference to Fig. 1 Schottky semiconductor devices that the present invention will be described in detail.
A kind of groove structure Schottky semiconductor device is N-type semiconductor silicon materials as shown in Figure 1, including substrate layer 1,
Phosphorus atoms doping concentration is 1E19cm-3；Drift layer 2 is the semiconductor silicon material of N-type on substrate layer 1, and phosphorus atoms are mixed
Miscellaneous concentration is 1E16cm-3, thickness 10um；2 surface of drift layer sets wide groove, and narrow groove is set in wide trench bottom surfaces,
Narrow groove is located in drift layer, and trench wall sets insulation material layer 4, is silica；Narrow channel bottom sets the second insulation material
The bed of material 5 is silicon nitride；Filling conductive material 7 in groove is heavily doped polysilicon；Layer surface of drifting about between groove sets Xiao Te
Base barrier junction 3；Upper and lower surface sets electrode metal, and upper surface electrode metal 10 connects schottky barrier junction 3 and conductive material 7.
The technique manufacturing process of this Fig. 1 embodiments is as follows：
The first step on the substrate layer 1 of high concentration impurities doping the first conductive semiconductor silicon materials composition, is given birth to by extension
It is long to form the first conductive semiconductor silicon materials drift layer 2；
Second step forms passivation layer on surface, is silicon nitride layer, and passivation layer is removed on wide trench region surface to be formed,
Semi-conducting material is performed etching, forms wide groove, wide groove is located in drift layer；
3rd step, is aoxidized in the trench, forms semi-conducting material thick oxide layer, dry etching removal channel bottom oxygen
Change layer, dry etching semi-conducting material forms narrow groove；
4th step removes wide trench wall oxide layer, carries out thermal oxide, and wall forms insulating materials 4 in the trench, for oxidation
Layer, forms the second insulation material layer 5 in the trench, is silicon nitride, and removal drift layer surface all divides silicon nitride with trench interiors,
Conductive material 7 is formed with drift layer surface in the trench, is heavily doped polysilicon, etching conductive material 7 removes drift layer surface
Conductive material；
5th step forms schottky barrier junction 3 in drift layer surface, carries out upper and lower surface metallization, form upper and lower surface
Electrode metal, upper surface electrode metal 10 connect conductive material 7 and schottky barrier junction 3.
Fig. 2 shows a kind of groove structure Schottky semiconductor device diagrammatic cross-section of the present invention, including substrate layer 1,
For N-type semiconductor silicon materials, phosphorus atoms heavy doping；Drift layer 2, on substrate layer 1, for the semiconductor silicon material of N-type, phosphorus
Atom is lightly doped；2 surface of drift layer sets wide groove, sets narrow groove in wide trench bottom surfaces, narrow groove is located at drift layer
In, trench wall sets insulation material layer 4, is silica；Filling conductive material 7 in groove is heavily doped polysilicon；Groove it
Between drift about layer surface set schottky barrier junction 3；Upper and lower surface sets electrode metal, and upper surface electrode metal 10 connects Schottky
Barrier junction 3 and conductive material 7.Fig. 3 is that the narrow trench wall of the present invention sets the Schottky semiconductor device of heavy insulation material layer to cut open
Face schematic diagram.Fig. 4 is the Schottky semiconductor device diagrammatic cross-section that channel bottom of the present invention sets heavy insulation material layer, including
Wide channel bottom and narrow channel bottom are provided with heavy insulation material layer, and implementation method is included in exposed trench wall deposit silicon nitride
Film, dry etching silicon nitride film, oxidation technology form thick oxide layer in channel bottom.
Fig. 5 is the Schottky semiconductor device diagrammatic cross-section that the narrow channel bottom of the present invention is arranged in substrate layer, including
Substrate layer 1, for N-type semiconductor silicon materials, phosphorus atoms heavy doping；Drift layer 2 is the semiconductor of N-type on substrate layer 1
Silicon materials, phosphorus atoms are lightly doped；2 surface of drift layer sets wide groove, and narrow groove, narrow trench bottom are set in wide trench bottom surfaces
In substrate layer, trench wall sets insulation material layer 4, is silica；Narrow channel bottom sets the second insulating materials 5, is
Silicon nitride, the second insulating materials upper surface are higher than substrate layer upper surface；Filling conductive material 7 in groove is heavily doped polysilicon；
Layer surface of drifting about between groove sets schottky barrier junction 3；Upper and lower surface sets electrode metal, and upper surface electrode metal 10 connects
Schottky barrier junction 3 and conductive material 7.
Fig. 8 is the Schottky semiconductor device section signal that lower trench of the present invention is arranged at the second conducting semiconductor material
Figure, including substrate layer 1, for N-type semiconductor silicon materials, phosphorus atoms heavy doping；Drift layer 2 is N-type on substrate layer 1
Semiconductor silicon material, phosphorus atoms are lightly doped；2 surface of drift layer sets wide groove, and narrow groove is set in wide trench bottom surfaces, narrow
Groove is located in drift layer, and trench wall sets insulation material layer 4, is silica；Wide groove and narrow lower trench set second
Conducting semiconductor material 6 is P-type semiconductor silicon materials；Filling conductive material 7 in groove is heavily doped polysilicon；Between groove
Layer surface of drifting about sets schottky barrier junction 3；Upper and lower surface sets electrode metal, and upper surface electrode metal 10 connects Schottky gesture
Build knot 3 and conductive material 7.Fig. 6 is that the Schottky that the narrow lower trench of the present invention is arranged at the second conductive semiconductor silicon materials is partly led
Body device diagrammatic cross-section.Fig. 7 is the Schottky semiconductor dress that the wide lower trench of the present invention sets the second conducting semiconductor material
Put diagrammatic cross-section, lower part is provided with the second insulating materials 5 in narrow groove in Fig. 7 structures, is silicon nitride.
Fig. 9 is that lower part sets the Schottky semiconductor device diagrammatic cross-section that polysilicon is lightly doped, bag in groove of the present invention
Substrate layer 1 is included, for N-type semiconductor silicon materials, phosphorus atoms heavy doping；Drift layer 2, on substrate layer 1, for partly leading for N-type
Body silicon materials, phosphorus atoms are lightly doped；2 surface of drift layer sets wide groove, and narrow groove, narrow groove are set in wide trench bottom surfaces
In drift layer, trench wall sets insulation material layer 4, is silica；Polysilicon 9 is lightly doped in filling p-type in narrow groove, wide
Filling heavily doped polysilicon 8 in groove；Layer surface of drifting about between groove sets schottky barrier junction 3；Upper and lower surface sets electrode
Metal, upper surface electrode metal 10 connect schottky barrier junction 3 and conductive material 7.Heavily doped polysilicon 8 is pointed out with gently mixing
Miscellaneous 9 interface of polysilicon includes being located in narrow groove or in wide groove.
Embodiment 2
Figure 10 shows that the narrow trenched side-wall of the present invention abuts against charge compensation Xiao that region sets the second conducting semiconductor material
Special based semiconductor device diagrammatic cross-section, with reference to Figure 10 Schottky semiconductor devices that the present invention will be described in detail.
A kind of groove structure Schottky semiconductor device is as shown in Figure 10, is N-type semiconductor silicon materials including substrate layer 1,
Phosphorus atoms doping concentration is 1E19cm-3；Drift layer 2 is the semiconductor silicon material of N-type on substrate layer 1, and phosphorus atoms are mixed
Miscellaneous concentration is 1E16cm-3, thickness 10um；2 surface of drift layer sets wide groove, and narrow groove is set in wide trench bottom surfaces,
Narrow channel bottom is located in substrate layer, abuts against setting the second conductive semiconductor of charge compensation in the drift layer of narrow trench sidewall area
Material 6, trench wall set insulation material layer 4, are silica；Narrow channel bottom sets the second insulation material layer 5, for nitridation
Silicon, while its upper surface is higher than substrate layer；Filling conductive material 7 in groove is heavily doped polysilicon；Drift layer table between groove
Face sets schottky barrier junction 3；Upper and lower surface sets electrode metal, and upper surface electrode metal 10 connects 3 He of schottky barrier junction
Conductive material 7.Figure 11 structures are close with Figure 10, and distinguishing characteristics sets the second insulation material layer for narrow groove is interior with wide channel bottom
5, it is silicon nitride.Figure 12 structures are close with Figure 10, and distinguishing characteristics sets the second insulation material layer 5 for lower part in narrow groove, and second
Wide channel bottom is closed in 5 upper surface of insulation material layer, and the second insulation material layer 5 is silicon nitride.
The technique manufacturing process of the present embodiment Figure 10 structures is as follows：
The first step on the substrate layer 1 of high concentration impurities doping the first conductive semiconductor silicon materials composition, is given birth to by extension
It is long to form the first conductive semiconductor silicon materials drift layer 2；
Second step forms passivation layer on surface, is silicon nitride layer, and passivation layer is removed on wide trench region surface to be formed,
Semi-conducting material is performed etching, forms wide groove, wide groove is located in drift layer；
3rd step, is aoxidized in the trench, forms semi-conducting material thick oxide layer, dry etching removal channel bottom oxygen
Change layer, dry etching semi-conducting material forms narrow groove, and small angle inclination injects the second conductive impurity boron, abutting against narrow channel side
Wall region, annealing form the second conducting semiconductor material of charge compensation 6；
4th step removes wide trench wall oxide layer, carries out thermal oxide, and wall forms insulating materials 4 in the trench, for oxidation
Layer, forms the second insulation material layer 5 in the trench, is silicon nitride, and removal drift layer surface all divides silicon nitride with trench interiors,
Conductive material 7 is formed with drift layer surface in the trench, is heavily doped polysilicon, etching conductive material 7 removes drift layer surface
Conductive material；
5th step forms schottky barrier junction 3 in drift layer surface, carries out upper and lower surface metallization, form upper and lower surface
Electrode metal, upper surface electrode metal 10 connect conductive material 7 and schottky barrier junction 3.
Figure 13 is the charge compensation Schottky semiconductor device diagrammatic cross-section that the narrow groove of the present invention is located in drift layer, is wrapped
Substrate layer 1 is included, for N-type semiconductor silicon materials, phosphorus atoms heavy doping；Drift layer 2, on substrate layer 1, for partly leading for N-type
Body silicon materials, phosphorus atoms are lightly doped；2 surface of drift layer sets wide groove, and narrow groove, narrow groove are set in wide trench bottom surfaces
Bottom is located in drift layer, abuts against and the second conducting semiconductor material of charge compensation 6 is set in the drift layer of narrow trench sidewall area,
Trench wall sets insulation material layer 4, is silica；Narrow channel bottom sets the second insulation material layer 5, is silicon nitride；Groove
Interior filling conductive material 7, is heavily doped polysilicon；Layer surface of drifting about between groove sets schottky barrier junction 3；Upper and lower surface is set
Electrode metal is put, upper surface electrode metal 10 connects schottky barrier junction 3 and conductive material 7.Figure 14 structures are close with Figure 13, area
It is not characterized as in narrow groove that lower part sets the second insulation material layer 5, wide channel bottom is closed in 5 upper surface of the second insulation material layer,
Second insulation material layer 5 is silicon nitride.
Figure 15 is that the narrow trench wall of the present invention abuts against the charge compensation Schottky that region sets the second conducting semiconductor material
Semiconductor device diagrammatic cross-section, including substrate layer 1, for N-type semiconductor silicon materials, phosphorus atoms heavy doping；Drift layer 2, is located at
It is the semiconductor silicon material of N-type on substrate layer 1, phosphorus atoms are lightly doped；2 surface of drift layer sets wide groove, in wide trench bottom
Portion surface sets narrow groove, and narrow channel bottom is located in drift layer, abuts against in the drift layer in narrow trench wall region and set charge
The second conducting semiconductor material 6 is compensated, trench wall sets insulation material layer 4, is silica；Narrow channel bottom sets second absolutely
Edge material layer 5 is silicon nitride；Filling conductive material 7 in groove is heavily doped polysilicon；Layer surface of drifting about between groove is set
Schottky barrier junction 3；Upper and lower surface sets electrode metal, and upper surface electrode metal 10 connects schottky barrier junction 3 and conduction material
Material 7.Figure 16 structures are close with Figure 15, and distinguishing characteristics sets the second insulation material layer 5, the second insulating materials for lower part in narrow groove
Wide channel bottom is closed in 5 upper surface of layer, and the second insulation material layer 5 is silicon nitride.
Figure 17 is a kind of charge compensation Xiao that the narrow trench wall of the present invention orients the second conducting semiconductor material of epitaxial growth
Special based semiconductor device cellular diagrammatic cross-section, including substrate layer 1, for N-type semiconductor silicon materials, phosphorus atoms heavy doping；Drift
Layer 2 is the semiconductor silicon material of N-type on substrate layer 1, and phosphorus atoms are lightly doped；2 surface of drift layer sets wide groove,
Wide trench bottom surfaces set narrow groove, and narrow channel bottom is located in drift layer, abut against narrow trench wall region and set orientation outer
The second conducting semiconductor material of charge compensation 6 that epitaxial growth is formed, trench wall set insulation material layer 4, are silica；Narrow ditch
Trench bottom sets the second insulation material layer 5, is silicon nitride；Filling conductive material 7 in groove is heavily doped polysilicon；Groove it
Between drift about layer surface set schottky barrier junction 3；Upper and lower surface sets electrode metal, and upper surface electrode metal 10 connects Schottky
Barrier junction 3 and conductive material 7.
The present invention is elaborated by examples detailed above, while other examples can also be used to realize the present invention, not office of the invention
It is limited to above-mentioned specific example, therefore the present invention is limited by scope.
Claims (10)
1. a kind of groove structure Schottky semiconductor device, it is characterised in that：Including：
Substrate layer is formed for the first conducting semiconductor material, is adulterated for high concentration impurities；
Drift layer is formed for the first conducting semiconductor material；
Multiple width grooves, positioned at drift layer surface, inner wall sets insulation material layer；
Narrow groove, positioned at wide trench bottom surfaces, inner wall sets insulation material layer；
Conductive material is polysilicon, amorphous silicon or metal, in wide groove or in wide groove and narrow groove；
Schottky barrier junction, layer surface of drifting about between wide groove；
Electrode metal, positioned at semiconductor device upper and lower surface, upper surface electrode metal connection conductive material and schottky barrier junction.
2. semiconductor device as described in claim 1, it is characterised in that：The wide groove and narrow channel bottom are provided with thickness
Insulating materials is provided with the second conducting semiconductor material in wide groove or narrow lower trench.
3. semiconductor device as described in claim 1, it is characterised in that：Lower part is provided with insulation material in the narrow groove
It is provided in material or narrow groove in insulating materials or wide groove and is provided with insulating materials in lower part and narrow groove.
4. semiconductor device as described in claim 1, it is characterised in that：The narrow channel bottom includes being located at substrate layer
In.
5. a kind of preparation method of groove structure Schottky semiconductor device as described in claim 1, it is characterised in that：Including
Following steps：
1) on the substrate layer for adulterating the first conducting semiconductor material composition in high concentration impurities, led by being epitaxially-formed first
Electric semi-conducting material drift layer；
2) passivation layer is formed on surface, is silicon nitride layer, in wide trench region surface removal passivation layer to be formed, perform etching half
Conductor material forms wide groove；
3) aoxidized in the trench, form semi-conducting material thick oxide layer, dry etching removal channel bottom oxide layer, dry method
Etching semiconductor material forms narrow groove；
4) wide trench wall oxide layer is removed, carries out thermal oxide, wall forms oxide layer in the trench, forms silicon nitride in the trench
Layer, removal drift layer surface all divide silicon nitride with trench interiors, form conductive material, etching with drift layer surface in the trench
Conductive material removes drift layer surface conductance material；
5) schottky barrier junction is formed in drift layer surface, carries out upper and lower surface metallization, form upper and lower surface electrode metal, on
Surface electrode metal connects conductive material and schottky barrier junction.
6. a kind of groove structure Schottky semiconductor device, it is characterised in that：Including：
Substrate layer is formed for the first conducting semiconductor material, is adulterated for high concentration impurities；
Drift layer is formed for the first conducting semiconductor material；
Multiple width grooves, positioned at drift layer surface, inner wall sets insulation material layer；
Narrow groove, positioned at wide trench bottom surfaces, inner wall sets insulation material layer, abuts against narrow trench sidewall area and charge is set to mend
Repay the second conducting semiconductor material；
Conductive material is polysilicon, amorphous silicon or metal, in wide groove or in wide groove and narrow groove；
Schottky barrier junction, layer surface of drifting about between wide groove；
Electrode metal, positioned at semiconductor device upper and lower surface, upper surface electrode metal connection conductive material and schottky barrier junction.
7. semiconductor device as claimed in claim 6, it is characterised in that：Lower part is provided with insulation material in the narrow groove
It is provided in material or narrow groove in insulating materials or wide groove and is provided with insulation material layer in lower part and narrow groove.
8. semiconductor device as claimed in claim 6, it is characterised in that：The narrow groove bottom includes being provided with second
Conducting semiconductor material.
9. semiconductor device as claimed in claim 6, it is characterised in that：The narrow channel bottom includes being located at substrate layer
In.
10. a kind of preparation method of groove structure Schottky semiconductor device as claimed in claim 6, it is characterised in that：Bag
Include following steps：
1) on the substrate layer for adulterating the first conducting semiconductor material composition in high concentration impurities, led by being epitaxially-formed first
Electric semi-conducting material drift layer；
2) passivation layer is formed on surface, is silicon nitride layer, in wide trench region surface removal passivation layer to be formed, perform etching half
Conductor material forms wide groove；
3) aoxidized in the trench, form semi-conducting material thick oxide layer, dry etching removal channel bottom oxide layer, dry method
Etching semiconductor material forms narrow groove, and small angle inclination is injected the second conductive impurity, formed abutting against narrow trench sidewall area
Second conducting semiconductor material；
4) wide trench wall oxide layer is removed, carries out thermal oxide, wall forms oxide layer in the trench, forms silicon nitride in the trench
Layer, removal drift layer surface all divide silicon nitride layer with trench interiors, form conductive material with drift layer surface in the trench, carve
Conductive material is lost, removes drift layer surface conductance material；
5) schottky barrier junction is formed in drift layer surface, carries out upper and lower surface metallization, form upper and lower surface electrode metal, on
Surface electrode metal connects conductive material and schottky barrier junction.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109346406A (en) * | 2018-11-23 | 2019-02-15 | 江苏新广联半导体有限公司 | A kind of production method of the gallium nitride SBD of parallel-connection structure |
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| US20030057442A1 (en) * | 1999-12-22 | 2003-03-27 | Frederic Lanois | Production of single-pole components |
| US20060157745A1 (en) * | 2005-01-18 | 2006-07-20 | Stmicroelectronics S.A. | Vertical unipolar component with a low leakage current |
| CN103137710A (en) * | 2011-11-21 | 2013-06-05 | 朱江 | Trench Schottky semiconductor device with various insulating layer isolation and preparation method thereof |
| CN203300654U (en) * | 2013-06-19 | 2013-11-20 | 张家港凯思半导体有限公司 | Oblique-trench Schottky barrier rectifying device |
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2016
- 2016-11-09 CN CN201610986208.4A patent/CN108063166A/en not_active Withdrawn
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030057442A1 (en) * | 1999-12-22 | 2003-03-27 | Frederic Lanois | Production of single-pole components |
| US20060157745A1 (en) * | 2005-01-18 | 2006-07-20 | Stmicroelectronics S.A. | Vertical unipolar component with a low leakage current |
| CN103137710A (en) * | 2011-11-21 | 2013-06-05 | 朱江 | Trench Schottky semiconductor device with various insulating layer isolation and preparation method thereof |
| CN203300654U (en) * | 2013-06-19 | 2013-11-20 | 张家港凯思半导体有限公司 | Oblique-trench Schottky barrier rectifying device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109346406A (en) * | 2018-11-23 | 2019-02-15 | 江苏新广联半导体有限公司 | A kind of production method of the gallium nitride SBD of parallel-connection structure |
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Application publication date: 20180522 |