CN108346692A - Power semiconductor and its manufacturing method - Google Patents
Power semiconductor and its manufacturing method Download PDFInfo
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- CN108346692A CN108346692A CN201710056660.5A CN201710056660A CN108346692A CN 108346692 A CN108346692 A CN 108346692A CN 201710056660 A CN201710056660 A CN 201710056660A CN 108346692 A CN108346692 A CN 108346692A
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- 238000007667 floating Methods 0.000 claims description 30
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
- H01L29/42332—Gate electrodes for transistors with a floating gate with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
- H01L29/42336—Gate electrodes for transistors with a floating gate with one gate at least partly formed in a trench
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
Abstract
Disclose power semiconductor and its manufacturing method.The power semiconductor includes the separate gate structures being located in groove.The separate gate structures include the first grid conductor, second grid conductor and third grid conductor being separated from each other, the first part of the first grid conductor is located at the top of the groove and is clipped between the second grid conductor and the third grid conductor, and the second part of the first grid conductor extends to the lower part of the groove.The power semiconductor uses separate gate structures to improve response speed and reduce switching loss.
Description
Technical field
The present invention relates to ic manufacturing technology fields, more particularly, to power semiconductor and its manufacturer
Method.
Background technology
Power semiconductor is also known as power electronic devices, including power diode, thyristor, VDMOS (vertical double expansions
Dispersed metallic oxide semiconductor) field-effect transistor, LDMOS (lateral diffusion metal oxide semiconductor) field-effect transistors with
And IGBT (insulated gate bipolar transistor) etc..IGBT is made of BJT (double pole triode) and FET (field-effect transistor)
Compound full-control type voltage driven type power semiconductor.IGBT has both the advantages of both BJT and FET, i.e. high input impedance
And the characteristics of low conduction voltage drop, therefore there is good switching characteristic, being widely used in has the characteristics that high pressure, heavy current
Field in, for example, the fields such as alternating current generator, frequency converter, Switching Power Supply, lighting circuit, Traction Drive.
On the basis of traditional IGBT device, it has been suggested that a kind of new plasma enhancing injection insulated gate bipolar is brilliant
Body pipe (Injection Enhanced Gate Transistors, that is, IEGT) device architecture.The device architecture is typically to pass through
One floating wide p-well structure is set in IGBT device structure to improve the conduction loss of device and obtain a small grid
Electrode capacitance.The device so designed can obtain the ability of fast conducting in the case of smaller gate drive current, and
Conducting efficiency can be improved and reduce conduction loss.However, IEGT devices there is anti-dVce/dt abilities are weaker, be easy to by
The problem of noise signal is interfered.IEGT devices have big Miller capacitance, and device is caused to occur a big Miller when off
Platform.Therefore, the switching speed of IEGT devices reduces, and turn-off power loss is big, so as to cause whole switching loss still mistake
Greatly.
Therefore, it is desirable to the design of the power semiconductor based on IEGT structures is further improved, to improve response speed
With reduction switching loss.
Invention content
In view of the above problems, separate gate structures being used to improve response speed and drop the purpose of the present invention is to provide a kind of
The power semiconductor and its manufacturing method of low switching losses.
According to an aspect of the present invention, a kind of power semiconductor is provided, including：The collecting zone of first doping type；
The field cut-off region of the second doping type on the collecting zone, second doping type and the first doping type phase
Instead；The drift region of the second doping type in the field cut-off region；The second doping type on the drift region
Buffering area；The well region of the first doping type on the buffering area；The hair of the second doping type in the well region
Penetrate area；It is extended downwardly from the well region surface, the groove of the drift region is reached across the well region and the buffering area；And
The separate gate structures being located in the groove, wherein the separate gate structures include the first grid conductor being separated from each other, second
The first part of grid conductor and third grid conductor, the first grid conductor is located at the top of the groove and is clipped in institute
It states between second grid conductor and the third grid conductor, the second part of the first grid conductor extends to the groove
Lower part.
Preferably, further include：On first part's side wall of the groove upper portion side wall and the first grid conductor
Gate-dielectric, the gate-dielectric and the second grid conductor form gate stack, and the first grid is led
Body, the second grid conductor and the third grid conductor are separated from each other.
Preferably, further include：Positioned at the insulating layer of the lower trench sidewalls, the insulating layer leads the first grid
The second part of body is separated from each other with the well region and the drift region, and the thickness of the gate-dielectric is less than the insulating layer
Thickness.
Preferably, the first grid conductor is earth grid, and the second grid conductor is active gate, the third
Grid conductor is floating grid.
Preferably, the second grid conductor surrounds the biasing well region of the well region, and the third grid conductor surrounds institute
State the floating well region of well region.
Preferably, further include the grid conductor being formed in above the floating well region, the grid conductor and described second
Grid conductor is electrically connected.
Preferably, the emitter region is formed in the effective coverage of the well region, and the emitter region and described first
Grid conductor is electrically connected.
Preferably, further include：Interlayer dielectric layer above the groove and the emitter region；In the well region
Contact zone, the contact zone is the doping concentration that the first doping type and doping concentration are higher than the well region；Across the layer
Between dielectric layer contact the conductive channel of the emitter region and the contact zone；And the emitter being electrically connected with the conductive channel
Electrode.
Preferably, further include：The collection emitter-base bandgap grading electrode being electrically connected with the collecting zone.
Preferably, the groove extends in the principal plane of power semiconductor according to the shape of bending, to limit
The biasing well region and the floating well region.
Preferably, the groove forms multiple U-shaped structures being connected to each other according to lattice, and the separate gate structures exist
It is extended continuously in the groove, and in the lattice, the region that the third grid conductor surrounds forms signal island.
Preferably, the doping concentration of the field cut-off region is higher than the doping concentration of the drift region.
Preferably, further include：Fly-wheel diode, the fly-wheel diode include anode and cathode, and the biasing well region is made
For the anode, the cathode is the N-doped zone for penetrating the collecting zone and reaching the cut-off region.
Preferably, first doping type is one kind in N-type and p-type, and second doping type is N-type and p-type
In another kind.
According to another aspect of the present invention, a kind of method of manufacture power semiconductor, the power semiconductor are provided
Device includes the emitter region of the collecting zone and the second doping type of the first doping type, first doping type and described second
Doping type is on the contrary, include：The buffering area of the second doping type is formed in the semiconductor substrate, and the semiconductor substrate is located at institute
State the drift region that the part below buffering area forms the second doping type；It is formed from the buffer surface and extends to the drift
Groove in area；Separate gate structures are formed in the trench；The well region of the first doping type is formed in the buffering area；
Emitter region is formed in the well region；And it forms second on a side surface opposite with the emitter region for the drift region and mixes
The field cut-off region of miscellany type；And form the first doping type in a side surface opposite with the emitter region for field cut-off region
Collecting zone, wherein the separate gate structures include the first grid conductor, second grid conductor and third grid being separated from each other
The first part of conductor, the first grid conductor is located at the top of the groove and is clipped in the second grid conductor and institute
Between stating third grid conductor, the second part of the first grid conductor extends to the lower part of the groove.
Preferably, the step of formation separate gate structures include：Insulating layer is formed in the side wall of the groove and bottom；Institute
It states and forms the first grid conductor in groove, the insulating layer surrounds the first grid conductor；On the top of the groove
Form gate-dielectric and the second grid conductor and the third grid conductor, wherein the gate-dielectric and institute
It states second grid conductor and forms gate stack, and by the first grid conductor, the second grid conductor and the third grid
Pole conductor is separated from each other.
Preferably, the first grid conductor includes positioned at the first part on the groove top and under the groove
The second part in portion, the step of forming gate-dielectric and the second grid conductor and the third grid conductor include：
The part that the insulating layer is located at the upper portion side wall of the groove is removed, first part's phase with the first grid conductor is formed
Adjacent the first opening and the second opening；In the side wall of the first part of the upper portion side wall and first grid conductor of the groove
Upper formation gate-dielectric；The second grid conductor is formed in first opening；And the shape in second opening
At the third grid conductor, wherein the thickness of the gate-dielectric is less than the thickness of the insulating layer, and the grid electricity is situated between
Matter and the second grid conductor form gate stack, and by the first grid conductor, the second grid conductor and described
Third grid conductor is separated from each other.
Preferably, the first grid conductor is earth grid, and the second grid conductor is active gate, the third
Grid conductor is floating grid.
Preferably, the second grid conductor surrounds the biasing well region of the well region, and the third grid conductor surrounds institute
State the floating well region of well region.
Preferably, further include that grid conductor is formed above the floating well region, the grid conductor and the second gate
Pole conductor electrical connection.
Preferably, the emitter region is formed in the effective coverage of the well region, and the method further includes：By the transmitting
Area is electrically connected with the first grid conductor.
Preferably, the doping concentration of the field cut-off region is higher than the doping concentration of the drift region.
Preferably, further include：Interlayer dielectric layer is formed above the groove and the emitter region；The shape in the well region
At contact zone, the contact zone is the doping concentration that the first doping type and doping concentration are higher than the well region；In the interlayer
The conductive channel for contacting the emitter region and the contact zone is formed in dielectric layer；And it is formed and is electrically connected with the conductive channel
Emitter electrode.
Preferably, including：Form the collection emitter-base bandgap grading electrode being electrically connected with the collecting zone.
Preferably, further include：The cathode of fly-wheel diode is formed, the biasing well region is as the anode, the cathode
To penetrate the N-doped zone that the collecting zone reaches the cut-off region.
Preferably, first doping type is one kind in N-type and p-type, and second doping type is N-type and p-type
In another kind.
Compared with prior art, power semiconductor according to the ... of the embodiment of the present invention includes the separate gate being located in groove
Structure.The power semiconductor is realized by the way that the gate structure of different potentials is arranged to power semiconductor grid signal
Separation, can obtain lower grid capacitance to reach, improve the response time of device, improve switching speed, reduce device
Switching loss.
Power semiconductor of the present invention, which uses separate gate structures, can effectively reduce the Miller electricity of device
Hold, improves the negative-feedback effect of device at work, improve the stability of device.Third gate electrode is floating and around floating
Well region is set, portion can form local hole charge aggregation in the area, can improve the saturation voltage drop of power semiconductor
And conduction loss.
Further, which is closed area, is isolated with outer signals, can improve device and resist to dv/dt
Interference performance reduces power semiconductor due to failing caused by larger dv/dt.
Further, which is extended continuously in the trench, is formed on " signal island ".It is reached by conductive channel 113
To the different settings for realizing grid signal on the basis of not extra chips additional areas, the flexible of device structure design is improved
Property.
Further, the structure cell of the power semiconductor includes that the shape in principal plane according to bending extends
Groove and separate gate structures.The envelope that can be formed in practice by adjusting effective signal grid and floating third grid conductor
Area/quantitative proportion of closed region obtains the IGBT device of different parameters performance.
Further, which is internally integrated fly-wheel diode, when device works without additional in parallel
One fly-wheel diode or fast recovery diode device, so as to be effectively reduced the application cost of the device.
Description of the drawings
By referring to the drawings to the description of the embodiment of the present invention, above-mentioned and other purposes of the invention, feature and
Advantage will be apparent from, in the accompanying drawings：
The decomposition perspective view and vertical view of power semiconductor according to a first embodiment of the present invention is shown respectively in Fig. 1 and 2
Figure；
Fig. 3 a to 3i show the sectional view of method, semi-conductor device manufacturing method different phase according to a first embodiment of the present invention；
Fig. 4 shows the sectional view of semiconductor devices according to a second embodiment of the present invention；
Fig. 5 shows the gate waveform comparison diagram of power semiconductor according to the ... of the embodiment of the present invention when off.
Specific implementation mode
Hereinafter reference will be made to the drawings is more fully described the present invention.In various figures, identical element is using similar attached
Icon is remembered to indicate.For the sake of clarity, the various pieces in attached drawing are not necessarily to scale.Furthermore, it is possible to be not shown certain
Well known part.For brevity, the semiconductor structure that can be obtained after several steps described in a width figure.
It should be appreciated that in the structure of outlines device, it is known as positioned at another floor, another area when by a floor, a region
When domain " above " or " top ", can refer to above another layer, another region, or its with another layer, it is another
Also include other layers or region between a region.Also, if device overturn, this layer, a region will be located at it is another
Layer, another region " following " or " lower section ".
If, herein will be using " A is directly on B in order to describe located immediately at another layer, another region above scenario
The form of presentation of face " or " A is on B and abuts therewith ".In this application, " A is in B " indicates that A is located in B, and
And A and B is abutted rather than A is located in the doped region formed in B.
In this application, term " semiconductor structure " refers to entire half formed in each step of manufacture semiconductor devices
The general designation of conductor structure, including all layers formed or region.
Many specific details of the present invention, such as the structure of device, material, size, processing work is described hereinafter
Skill and technology, to be more clearly understood that the present invention.But it just as the skilled person will understand, can not press
The present invention is realized according to these specific details.
Unless hereinafter particularly pointing out, the various pieces of semiconductor devices can be by well known to those skilled in the art
Material is constituted.Semi-conducting material is for example including Group III-V semiconductor, such as GaAs, InP, GaN, SiC and IV race semiconductor, such as
Si、Ge。
The decomposition perspective view and vertical view of power semiconductor according to the ... of the embodiment of the present invention is shown respectively in Fig. 1 and 2.For
For the sake of clear, the separation of some parts of power semiconductor is shown in Fig. 1, in addition, be not shown in figure some regions.
It is appreciated that in actual product, the various pieces of power semiconductor be combine and include unshowned
Some regions, to form complete device architecture.Line AA in fig. 2 shows the interception position of subsequent sectional view.
As shown in Figure 1, in the vertical direction of power semiconductor 100, power semiconductor 100 includes heap successively
Folded N-type drift region 101, N-type buffering area 102 and P type trap zone 109.The doping concentration of N-type buffering area 102 is higher than N-type drift region
Doping concentration.Groove 103 is extended to via N-type buffering area 102 in N-type drift region 101 from the surface of P type trap zone 109 to be reached
Scheduled depth.Separate gate structures are formed in groove 103, include the insulating layer 104 positioned at 103 lower sides of groove, are formed
First grid conductor 105, second grid conductor 106 in groove 103 and third grid conductor 107, and by three each other every
The gate-dielectric 108 opened.Further, gate-dielectric 108 is also located in 103 upper portion side wall of groove, and second grid is led
Body 106 and third grid conductor 107 are spaced apart with P type trap zone 109.The thickness of gate-dielectric 108 is less than insulating layer 104
Thickness.
N-type emitter region 111 and p-type contact zone 110 are formed in P type trap zone 109.P-type contact zone 110 is relative to p-type trap
109 heavy doping of area.Conductive channel 113 is in contact with both N-type emitter region 111 and p-type contact zone 110.Further, emitter
Electrode is connected with conductive channel 113.
Although being not shown in figure, however, surface opposite with emitter region 111 is formed in N-type drift region 101 forms heap
Folded N-type field cut-off region, p-type collecting zone and collector electrode.The doping concentration of the N-type field cut-off region is higher than N-type drift region
101。
In groove 103, second grid conductor 106 and third grid conductor 107 are located at the top of groove 103, the first grid
Pole conductor 105 extends to lower part from the top of groove 103, including be located at 103 upper and lower part of groove first part and
Second part.The top of first grid conductor 105 is between second grid conductor 106 and third grid conductor 107.In the reality
It applies in example, the width of the first part of first grid conductor 105 is less than the width of second part.Further, first grid is led
It is separated from each other by gate-dielectric 108 between body 105, second grid conductor 106 and third grid conductor 107.In the embodiment
In, first grid conductor 105 is grounded (such as emitter with power semiconductor 100), and second grid conductor 106 is power
The active gate of semiconductor devices 100, third grid conductor 107 are floating.
As shown in Fig. 2, in the principal plane of power semiconductor 100, groove 103 and separate gate structures therein are formed
Multiple U-shaped structures interconnected amongst one another, including emitter interconnecting area ZA, separate gate extension area ZB and separate gate interconnecting area ZC.It is sending out
In emitter-base bandgap grading interconnecting area ZA, N-type emitter region 111 and p-type contact zone 110 are formed, and the conductive channel 113 that the two is interconnected.It is excellent
Selection of land can be in emitter interconnecting area ZA if the emitter region 111 of power semiconductor 100 is grounded in a state of use
In, first grid conductor 105 is connect with emitter region 111, to realize the ground connection of first grid conductor 105.Prolong in separate gate
It stretches in area ZB, groove 103 and separate gate structures therein extend according to the shape of bending.In separate gate interconnecting area ZC, groove
103 and separate gate structures therein connect with adjacent U-shaped structure, formed lattice.Power semiconductor 100 utilizes that
This is abutted and the third grid conductor 107 that is extended continuously forms signal island, can for example be formed in this region and second grid
The gate electrode that conductor 106 is connected.
Further, P type trap zone 109 includes the first part 109-1 and third grid that second grid conductor 106 surrounds
The second part 109-2 that pole conductor 107 surrounds.In this embodiment, the first part 109-1 of P type trap zone 109 is that power is partly led
The biasing well region of body device 100, second part 109-2 is located near floating third grid conductor 107, floating to be formed
Floating well region.According to the performance parameter of the power semiconductor, the face of the biasing well region and the floating well region is set
Product ratio.In power semiconductor, if improving the area ratio of floating well region relative to biasing well region, it can reduce
Conduction loss, but will increase parasitic capacitance simultaneously, reduce the switching speed of device.Therefore, suitable area ratio can be set,
To weigh the loss of power semiconductor and the demand of switching speed.
The N-type emitter region 111 and p-type contact zone 110 of power semiconductor 100 are respectively positioned on first of P type trap zone 109
Divide 109-1, that is, is located in the biasing well region of power semiconductor 100.In signal island, the first grid conductor that is extended continuously
105 and third grid conductor 107 surround the second part 109-2 of P type trap zone 109, in the floating of power semiconductor 100
The gate electrode that formation is connected with second grid conductor 106 in well region is set, to reduce Miller capacitance.
Power semiconductor according to this embodiment can be effectively reduced Miller capacitance using separate gate structures, from
And improve negative-feedback effect at work, improve job stability.Meanwhile by the way that floating third gate electrode is arranged
107, closed floating well region is formed in P type trap zone 109, portion can form local hole charge aggregation in the area, from
And the saturation voltage drop and conduction loss of power semiconductor can be improved.
Further, since the floating well region of the P type trap zone 109 is completely enclosed, it is isolated with outer signals, it can be with
Anti-interference ability of the device to dv/dt is improved, reduces power semiconductor due to failing caused by larger dv/dt.In addition,
The power semiconductor forms signal island using third grid conductor 107 that is adjacent to each other and being extended continuously, in this region
Such as the gate electrode being connected with second grid conductor 106 can be formed.
Further, the interconnection that emitter region 111 and P type trap zone 109 are realized by conductive channel 113, to not additional
The different settings that grid signal is realized on the basis of chip additional areas, improve the flexibility of device structure design.
Further, which includes that the N-type field between N-type drift region 101 and p-type collecting zone is cut
Only area.N-type cut-off region is the semiconductor layer for being heavily doped to N-type for abutting and being in contact with each other with N-type drift region 101 so that electric field
Field cut-off region have to go to the toilet reduce sharply it is weak, it is compound to which in shutdown moment majority carrier can be accelerated.Field cut-off region improves power half
The avalanche resistance tolerance of conductor device, and reduce tail current to reduce switching loss.
Fig. 3 a to 3i show the sectional view of method, semi-conductor device manufacturing method different phase according to the ... of the embodiment of the present invention.It is described
The interception position of sectional view is located in the emitter interconnecting area ZA of power semiconductor 100, as shown in the line AA in Fig. 2.
This method starts from semiconductor substrate.Semiconductor substrate is, for example, to be doping to the silicon substrate of N-type, which indulges
To uniform doping, resistivity is for example between the range of 1~15 Ω cm.Semiconductor substrate has opposite first surface and the
Two surfaces.Preferably, in the first surface of semiconductor substrate, pass through the techniques shape such as photoetching, etching, ion implanting, impurity activation
The partial pressure ring structure of success rate semiconductor, the partial pressure ring structure belong to a kind of well known structural portion of this field device architecture
Point, this will not be detailed here.
N-type buffering area 102 is formed in the first surface of semiconductor substrate so that semiconductor substrate is located at N-type buffering area 102
The part of lower section forms N-type drift region 101, as shown in Figure 3a.First surface of the N-type buffering area 102 from semiconductor substrate
Scheduled depth is extended downward into, and doping concentration is higher than the N-type drift region 101.It is used to form N-type buffering area 102
Technique includes forming Etching mask by photoetching and etching, carries out ion implanting via the opening of Etching mask, then goes
Except Etching mask, and thermal annealing is carried out with activator impurity.
Then, groove 103 is formed in the first surface of semiconductor substrate, and fills insulating layer 104 in groove 103,
As shown in Figure 3b.The groove 103 is extended downwardly from the surface of N-type buffering area 102, and is reached in the N-type drift region 101
Scheduled depth.The technique for being used to form groove 103 includes forming Etching mask by photoetching and etching, is covered via resist
The expose portion of the opening etching removal N-type buffering area 102 of mould, and the further expose portion of removal N-type drift region 101.
The technique for being used to form insulating layer 104 includes that the inner wall by thermal oxide in groove 103 forms oxide layer 104.The oxide layer
The 104 conformally side wall of covering groove 103 and bottoms, to still retain a part of inner space of groove 103.
Then, first grid conductor 105 is formed in the groove 103 for being lined with oxide layer 104, as shown in Figure 3c.The first grid
Pole conductor 105 is for example made of the polysilicon adulterated.The technique for being used to form first grid conductor 105 includes using works such as sputterings
Skill deposit polycrystalline silicon so that polysilicon fills the remainder of groove 103, and is removed using chemical-mechanical planarization (CMP)
Polysilicon outside groove 103, so that the polysilicon of filling groove 103 forms first grid conductor 105.
Then, gate-dielectric 108 and second grid conductor 106 are formed on the top of groove 103 and third grid is led
Body 107, as shown in Figure 3d.Gate-dielectric 108 is for example made of silica, and its thickness is less than the thickness of insulating layer 104.
The technique for being used to form gate-dielectric 108 includes the part for using etching that removing oxide layer 104 is gone to be located at 103 top of groove, from
And form first opening and second opening adjacent with the first part of first grid conductor 105.First opening and second
The sidewall surfaces and first grid conductor 105 on 103 top of opening exposure groove are located at the sidewall surfaces on 103 top of groove.Into
One step, using thermal oxide, by the side wall table of the sidewall surfaces on 103 top of groove and the corresponding portion of first grid conductor 105
Face aoxidizes, and forms gate-dielectric 108.It is used to form the technique of second grid conductor 106 and third grid conductor 107 and is used for
The technique for forming first grid conductor 105 is identical, and this will not be detailed here.Second grid conductor 106 is located in the first opening, third
Grid conductor 107 is located in the second opening.
In this step, separate gate structures are formed.Separate gate structures are formed in groove 103, including are located in groove 103
First grid conductor 105, second grid conductor 106 and third grid conductor 107, and grid electricity that three is separated from each other
Medium 108.Further, gate-dielectric 108 is also located in the upper portion side wall of groove 103.First grid conductor 105 is from groove
103 top extends to lower part, including is located at first part and the second part of 103 upper and lower part of groove.Insulating layer
104 are located at the lower sides of groove 103, and around the second part of first grid conductor 105.First grid conductor 105
Top is between second grid conductor 106 and third grid conductor 107.Since first grid conductor 105 is located on groove 103
The sidewall surfaces thermal oxide in portion is transformed into gate-dielectric 108, and therefore, the width of the first part of first grid conductor 105 is small
In the width of second part.
Then, P type trap zone 109 is formed on the surface of N-type buffering area 102, as shown in Figure 3 e.The P type trap zone 109 is from N
The surface of type buffering area 102 extends downward into scheduled depth.It is used to form the technique and N-type buffering area 102 of P type trap zone 109
It is essentially identical, differ only in dopant type on the contrary, and P type trap zone 109 depth be less than N-type buffering area 102 depth
Degree.
The groove 103 formed before the step extends to N from the surface of P type trap zone 109 via N-type buffering area 102
Reach scheduled depth in type drift region 101.The depth of P type trap zone 109 is less than or equal to second grid conductor 106 and third grid
The depth of conductor 107.Thus, on the top of groove 103, gate-dielectric 108 leads second grid conductor 106 and third grid
Body 107 is spaced apart with P type trap zone 109.In the lower part of groove 103, using insulating layer 104 by first grid conductor 105
Second part is spaced apart with N-type buffering area 102.In this embodiment, second grid conductor 106 and gate-dielectric 108 will
Efforts gate stack as power semiconductor 100.
Then, N-type emitter region 111 is formed on the surface of P type trap zone 109, as illustrated in figure 3f.The N-type emitter region 111 from
The surface of P type trap zone 109 extends downward into scheduled depth.It is used to form the technique and N-type buffering area 102 of N-type emitter region 111
Essentially identical, the depth for differing only in N-type emitter region 111 is less than the depth of P type trap zone 109, and this will not be detailed here.
It should be noted that N-type emitter region 111 is formed in one adjacent with second grid conductor 106 in P type trap zone 109
In subregion, without being formed in another part region adjacent with third grid conductor 107 in P type trap zone 109.Referring to
Fig. 2, groove 103 extend in the principal plane of power semiconductor according to the shape of bending, the second gate formed in groove 103
N-type emitter region 111 is formed in the region that pole conductor 106 surrounds.
Then, the dielectric layer 112 between the surface deposits of semiconductor structure.The interlayer dielectric layer for example can be that thickness is
600 nanometers to 1.5 microns of boron-phosphorosilicate glass (BPSG).In interlayer dielectric layer 112 contact hole is formed using techniques such as etchings.
Preferably, ion implanting is carried out via contact hole, forms p-type contact zone 110 in P type trap zone 109.Further, it is contacting
Conductive channel 113 is formed in hole.Conductive channel 113 is in contact with both N-type emitter region 111 and p-type contact zone 110, such as Fig. 3 g
It is shown.
Then, after filling metal in the contact hole of interlayer dielectric layer 112, to the metal layer of formation, via mask into
Row etching, to which metal layer pattern is melted into emitter electrode 114, as illustrated in figure 3h.The emitter electrode 114 and conductive channel
113 are connected.
Then, surface opposite with emitter region 111 is formed in N-type drift region 101 forms the N-type field cut-off region stacked
115, p-type collecting zone 116 and collector electrode 117, as shown in figure 3i.The doping concentration of the N-type field cut-off region 115 is higher than N-type
The doping concentration of drift region 101.Preferably, before forming N-type field cut-off region 115, reduction process is used to reduce N-type drift
The thickness in area 101.The technique for being used to form N-type drift region 101 and p-type collecting zone 116 is included in N-type drift region 101 and passes through
Ion implanting forms the doped region of corresponding doping concentration, and carries out thermal annealing with activator impurity.It is used to form collector electrode
117 technique is identical as the technique for being used to form emitter electrode 114, and this will not be detailed here.
Preferably, after the step of forming collector electrode 117 and emitter electrode 114, in vacuum or nitrogen protection
The metal layer in the preset thickness region of the reservation and deposition is heat-treated under atmosphere.Heat treatment temperature and time are not
It is sufficient to make the metal layer of power semiconductor to melt.
Further, as shown in Fig. 2, in emitter interconnecting area ZA, the ground connection of first grid conductor 105 is provided.If
The emitter region 111 of power semiconductor 100 is grounded in a state of use, then can be by first grid conductor 105 and emitter region
111 are connected to each other.In separate gate interconnecting area ZC, adjacent U-shaped structure is connected to each other, and forms lattice, wherein continuously prolong
The third grid conductor 107 stretched forms signal island.The grid electricity being connected with second grid conductor 106 is formed in signal island
Pole.Third grid conductor 107 suspends.
Fig. 4 shows the sectional view of semiconductor devices according to a second embodiment of the present invention.It is according to second embodiment partly to lead
Body device is with semiconductor devices according to first embodiment the difference is that including embedded fly-wheel diode, other aspects are then
It is essentially identical.As shown in figure 4, the anode of the fly-wheel diode is the biasing well region of well region 109, cathode 118 is to penetrate collecting zone
116 reach the N-doped zone of cut-off region 115.Cathode 118 is contacted with both p-type collector 116 and N-type field cut-off region 115.Into
One step, collector electrode 117 is all connected with both p-type collecting zone 116 and cathode 118.It is used to form the technique example of cathode 118
Such as it is included in 116 intermediate ion of p-type collecting zone to inject to form N-doped zone, which prolongs from the surface of p-type collecting zone 116
Extend to N-type field cut-off region 115.Be used to form the technique of collector electrode 117 for example including deposition conductive layer covered cathode 118 with
The surface of collecting zone 116.
Power semiconductor according to second embodiment is internally integrated fly-wheel diode, when device works without additional
A fly-wheel diode or fast recovery diode device in parallel, so as to be effectively reduced the application cost of the device.
Fig. 5 shows the gate waveform comparison diagram of power semiconductor according to the ... of the embodiment of the present invention when off.With biography
System IEGT structures power semiconductor compare, using the power semiconductor of structure of the invention shutdown during transmitting
Pole collector voltage VCE eliminates Miller platform in changing over time, saturation voltage is reduced rapidly to zero, to improve response
Speed and reduce switching loss.
It should be noted that herein, relational terms such as first and second and the like are used merely to a reality
Body or operation are distinguished with another entity or operation, are deposited without necessarily requiring or implying between these entities or operation
In any actual relationship or order or sequence.Moreover, the terms "include", "comprise" or its any other variant are intended to
Non-exclusive inclusion, so that the process, method, article or equipment including a series of elements is not only wanted including those
Element, but also include other elements that are not explicitly listed, or further include for this process, method, article or equipment
Intrinsic element.In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that
There is also other identical elements in process, method, article or equipment including element.
For example above according to the embodiment of the present invention, these embodiments are not also limited there is no all details of detailed descriptionthe
The specific embodiment that the invention is only.Obviously, as described above, can make many modifications and variations.This specification is chosen simultaneously
These embodiments are specifically described, are in order to preferably explain the principle of the present invention and practical application, to make technical field
Technical staff can utilize modification of the invention and on the basis of the present invention to use well.The present invention only by claims and
The limitation of its full scope and equivalent.
Claims (29)
1. a kind of power semiconductor, including：
The collecting zone of first doping type；
The field cut-off region of the second doping type on the collecting zone, second doping type adulterate class with described first
Type is opposite；
The drift region of the second doping type in the field cut-off region；
The buffering area of the second doping type on the drift region；
The well region of the first doping type on the buffering area；
The emitter region of the second doping type in the well region；
It is extended downwardly from the well region surface, the groove of the drift region is reached across the well region and the buffering area；And
The separate gate structures being located in the groove,
Wherein, the separate gate structures include the first grid conductor, second grid conductor and third grid conductor being separated from each other,
The first part of the first grid conductor is located at the top of the groove and is clipped in the second grid conductor and described
Between three grid conductors, the second part of the first grid conductor extends to the lower part of the groove.
2. power semiconductor according to claim 1, further includes：Positioned at the groove upper portion side wall and described first
It is folded that gate-dielectric on first part's side wall of grid conductor, the gate-dielectric and the second grid conductor form grid
Layer, and the first grid conductor, the second grid conductor and the third grid conductor are separated from each other.
3. power semiconductor according to claim 2, further includes：Positioned at the insulating layer of the lower trench sidewalls,
The second part of the first grid conductor is separated from each other by the insulating layer with the well region and the drift region, the grid
Dielectric thickness is less than the thickness of the insulating layer.
4. power semiconductor according to claim 3, wherein the first grid conductor is earth grid, described
Second grid conductor is active gate, and the third grid conductor is floating grid.
5. power semiconductor according to claim 4, wherein the second grid conductor is inclined around the well region
Well region is set, the third grid conductor surrounds the floating well region of the well region.
6. power semiconductor according to claim 5, wherein joined according to the performance of the power semiconductor
The area ratio of the biasing well region and the floating well region is arranged in number.
7. power semiconductor according to claim 5 further includes that the grid being formed in above the floating well region is led
Body, the grid conductor are electrically connected with the second grid conductor.
8. power semiconductor according to claim 5, wherein the emitter region is formed in the effective district of the well region
In domain, and the emitter region is electrically connected with the first grid conductor.
9. power semiconductor according to claim 4, further includes：
Interlayer dielectric layer above the groove and the emitter region；
Contact zone in the well region, the contact zone are the first doping type and doping concentration mixing higher than the well region
Miscellaneous concentration；
The conductive channel of the emitter region and the contact zone is contacted across the interlayer dielectric layer；And
The emitter electrode being electrically connected with the conductive channel.
10. power semiconductor according to claim 4, further includes：
The collection emitter-base bandgap grading electrode being electrically connected with the collecting zone.
11. power semiconductor according to claim 5, wherein the groove is flat in the master of power semiconductor
Extend according to the shape of bending in face, to limit the biasing well region and the floating well region.
12. power semiconductor according to claim 9, wherein the groove formed it is multiple according to lattice that
The U-shaped structure of this connection, the separate gate structures are extended continuously in the trench, and in the lattice, described
The region that third grid conductor surrounds forms signal island.
13. power semiconductor according to claim 5, wherein the doping concentration of the field cut-off region is higher than described
The doping concentration of drift region.
14. power semiconductor according to claim 13, further includes：Fly-wheel diode, the fly-wheel diode packet
Anode and cathode is included, for the biasing well region as the anode, the cathode is to penetrate the collecting zone to reach the cut-off region
N-doped zone.
15. the power semiconductor according to any one of claim 1 to 14, wherein first doping type is N
One kind in type and p-type, second doping type are the another kind in N-type and p-type.
16. a kind of power semiconductor, including：
The collecting zone of first doping type；
The field cut-off region of the second doping type on the collecting zone, second doping type adulterate class with described first
Type is opposite；
The drift region of the second doping type in the field cut-off region；
The buffering area of the second doping type on the drift region；
The well region of the first doping type on the buffering area；
The emitter region of the second doping type in the well region；
It is extended downwardly from the well region surface, the groove of the drift region is reached across the well region and the buffering area；And
The separate gate structures being located in the groove,
Wherein, the groove extends in the principal plane of power semiconductor according to the shape of bending, thus by the well region
It is limited to biasing well region and floating well region.
17. a kind of power semiconductor, including：
The collecting zone of first doping type；
The field cut-off region of the second doping type on the collecting zone, second doping type adulterate class with described first
Type is opposite；
The drift region of the second doping type in the field cut-off region；
The buffering area of the second doping type on the drift region；
The well region of the first doping type on the buffering area；
The emitter region of the second doping type in the well region；
It is extended downwardly from the well region surface, the groove of the drift region is reached across the well region and the buffering area；And
The separate gate structures being located in the groove,
Wherein, the groove forms multiple U-shaped structures being connected to each other according to lattice, and the separate gate structures are in the ditch
It is extended continuously in slot, and forms signal island in the lattice.
18. a kind of method of manufacture power semiconductor, the power semiconductor includes the current collection of the first doping type
The emitter region in area and the second doping type, first doping type is with second doping type on the contrary, including：
The buffering area of the second doping type is formed in the semiconductor substrate, and the semiconductor substrate is located at below the buffering area
Part forms the drift region of the second doping type；
Form the groove extended to from the buffer surface in the drift region；
Separate gate structures are formed in the trench；
The well region of the first doping type is formed in the buffering area；
Emitter region is formed in the well region；And
The field cut-off region of the second doping type is formed on a side surface opposite with the emitter region for the drift region；
And the collecting zone of the first doping type is formed in a side surface opposite with the emitter region for field cut-off region,
Wherein, the separate gate structures include the first grid conductor, second grid conductor and third grid conductor being separated from each other,
The first part of the first grid conductor is located at the top of the groove and is clipped in the second grid conductor and described
Between three grid conductors, the second part of the first grid conductor extends to the lower part of the groove.
19. according to the method for claim 18, wherein formed separate gate structures the step of include：
Insulating layer is formed in the side wall of the groove and bottom；
The first grid conductor is formed in the trench, and the insulating layer surrounds the first grid conductor；
Gate-dielectric and the second grid conductor and the third grid conductor are formed on the top of the groove,
Wherein, the gate-dielectric and the second grid conductor form gate stack, and by the first grid conductor, institute
It states second grid conductor and the third grid conductor is separated from each other.
20. according to the method for claim 19, wherein the first grid conductor includes positioned at the of the groove top
A part and second part positioned at the lower trench form gate-dielectric and the second grid conductor and described the
The step of three grid conductors includes：
The part that the insulating layer is located at the upper portion side wall of the groove is removed, first with the first grid conductor is formed
Split-phase adjacent the first opening and the second opening；
Gate-dielectric is formed on the side wall of the first part of the upper portion side wall and first grid conductor of the groove；
The second grid conductor is formed in first opening；And
The third grid conductor is formed in second opening,
Wherein, the thickness of the gate-dielectric is less than the thickness of the insulating layer,
The gate-dielectric and the second grid conductor form gate stack, and by the first grid conductor, described the
Two grid conductors and the third grid conductor are separated from each other.
21. according to the method for claim 20, wherein the first grid conductor is earth grid, the second grid
Conductor is active gate, and the third grid conductor is floating grid.
22. according to the method for claim 21, wherein the second grid conductor surrounds the biasing well region of the well region,
The third grid conductor surrounds the floating well region of the well region.
23. further including according to the method for claim 22, forming grid conductor, the grid above the floating well region
Conductor is electrically connected with the second grid conductor.
24. according to the method for claim 23, wherein the emitter region is formed in the effective coverage of the well region, institute
The method of stating further includes：The emitter region is electrically connected with the first grid conductor.
25. according to the method for claim 20, wherein the doping concentration of the field cut-off region is mixed higher than the drift region
Miscellaneous concentration.
26. according to the method for claim 20, further including：
Interlayer dielectric layer is formed above the groove and the emitter region；
Contact zone is formed in the well region, the contact zone is the first doping type and doping concentration mixing higher than the well region
Miscellaneous concentration；
The conductive channel for contacting the emitter region and the contact zone is formed in the interlayer dielectric layer；And
Form the emitter electrode being electrically connected with the conductive channel.
27. according to the method for claim 20, further including：
Form the collection emitter-base bandgap grading electrode being electrically connected with the collecting zone.
28. according to the method for claim 20, further including：Form the cathode of fly-wheel diode, the biasing well region conduct
The anode, the cathode are the N-doped zone for penetrating the collecting zone and reaching the cut-off region.
29. the method according to any one of claim 18 to 28, wherein first doping type is in N-type and p-type
One kind, second doping type be N-type and p-type in another kind.
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