CN108346692B - Power semiconductor device and method of manufacturing the same - Google Patents

Power semiconductor device and method of manufacturing the same Download PDF

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Publication number
CN108346692B
CN108346692B CN201710056660.5A CN201710056660A CN108346692B CN 108346692 B CN108346692 B CN 108346692B CN 201710056660 A CN201710056660 A CN 201710056660A CN 108346692 B CN108346692 B CN 108346692B
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region
gate conductor
gate
type
trench
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CN108346692A (en
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顾悦吉
杨彦涛
陈琛
王珏
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Hangzhou Silan Integrated Circuit Co Ltd
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Hangzhou Silan Integrated Circuit Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H01L29/42332—Gate electrodes for transistors with a floating gate with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H01L29/42336—Gate electrodes for transistors with a floating gate with one gate at least partly formed in a trench
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate

Abstract

A power semiconductor device and a method of manufacturing the same are disclosed. The power semiconductor device includes a split gate structure located in a trench. The split gate structure includes a first gate conductor, a second gate conductor, and a third gate conductor spaced apart from each other, a first portion of the first gate conductor being located at an upper portion of the trench and sandwiched between the second gate conductor and the third gate conductor, a second portion of the first gate conductor extending to a lower portion of the trench. The power semiconductor device adopts a split gate structure to improve response speed and reduce switching loss.

Description

Power semiconductor device and method of manufacturing the same
Technical Field
The present application relates to the field of integrated circuit manufacturing technology, and more particularly, to a power semiconductor device and a method of manufacturing the same.
Background
Power semiconductor devices, also known as power electronics devices, include power diodes, thyristors, VDMOS (vertical double diffused metal oxide semiconductor) field effect transistors, LDMOS (lateral diffused metal oxide semiconductor) field effect transistors, IGBTs (insulated gate bipolar transistors), and the like. The IGBT is a composite fully controlled voltage driven power semiconductor device composed of a BJT (bipolar transistor) and a FET (field effect transistor). The IGBT has both the advantages of the BJT and the FET, i.e. the characteristics of high input impedance and low on-voltage drop, so that the IGBT has good switching characteristics, and is widely used in fields having characteristics of high voltage, high current, etc., such as ac motor, frequency converter, switching power supply, lighting circuit, traction drive, etc.
Based on the conventional IGBT device, a new structure of a plasma enhanced injection insulated gate bipolar transistor (Injection Enhanced Gate Transistors, IEGT) device has been proposed. The device structure is typically improved in turn-on loss of the device and a small gate capacitance is achieved by providing a floating wide P-well structure in the IGBT device structure. The device designed in this way can obtain the capability of fast conduction under the condition of smaller gate driving current, and can improve the conduction efficiency and reduce the conduction loss. However, IEGT devices suffer from weak immunity to dcde/dt and are prone to interference from noise signals. IEGT devices have large miller capacitance, resulting in a large miller plateau when the device is turned off. Therefore, the switching speed of the IEGT device is reduced and the turn-off loss is large, resulting in that the overall switching loss is still excessive.
Accordingly, further improvements in the design of power semiconductor devices based on IEGT structures are desired to increase response speed and reduce switching losses.
Disclosure of Invention
In view of the above, an object of the present application is to provide a power semiconductor device employing a split gate structure to improve response speed and reduce switching loss, and a method of manufacturing the same.
According to an aspect of the present application, there is provided a power semiconductor device including: a collector region of a first doping type; a field stop region of a second doping type on the collector region, the second doping type being opposite to the first doping type; a drift region of a second doping type located on the field stop region; a buffer region of a second doping type located on the drift region; a well region of a first doping type located on the buffer region; an emitter region of a second doping type located in the well region; a trench extending downward from the well region surface, through the well region and the buffer region, to the drift region; and a split gate structure located in the trench, wherein the split gate structure includes a first gate conductor, a second gate conductor, and a third gate conductor spaced apart from each other, a first portion of the first gate conductor being located at an upper portion of the trench and sandwiched between the second gate conductor and the third gate conductor, a second portion of the first gate conductor extending to a lower portion of the trench.
Preferably, the method further comprises: a gate dielectric on the trench upper sidewalls and a first portion of the sidewalls of the first gate conductor, the gate dielectric and the second gate conductor forming a gate stack and separating the first gate conductor, the second gate conductor and the third gate conductor from each other.
Preferably, the method further comprises: an insulating layer on a lower sidewall of the trench, the insulating layer separating the second portion of the first gate conductor from the well region and the drift region, the gate dielectric having a thickness less than a thickness of the insulating layer.
Preferably, the first gate conductor is a grounded gate, the second gate conductor is a working gate, and the third gate conductor is a floating gate.
Preferably, the second gate conductor surrounds an offset well region of the well region, and the third gate conductor surrounds a floating well region of the well region.
Preferably, the floating well region further comprises a gate conductor formed above the floating well region, and the gate conductor is electrically connected with the second gate conductor.
Preferably, the emitter region is formed in an effective region of the well region, and the emitter region is electrically connected to the first gate conductor.
Preferably, the method further comprises: an interlayer dielectric layer located above the trench and the emitter region; the contact region is positioned in the well region, is of a first doping type and has a doping concentration higher than that of the well region; a conductive path through the interlayer dielectric layer contacting the emitter region and the contact region; and an emitter electrode electrically connected to the conductive via.
Preferably, the method further comprises: and a collector electrode electrically connected to the collector region.
Preferably, the trench extends in a curved shape in a main plane of the power semiconductor device, thereby defining the offset well region and the floating well region.
Preferably, the trench forms a plurality of U-shaped structures connected to each other in a grid pattern in which the split gate structure extends continuously, and in which the region surrounded by the third gate conductor forms a signal island.
Preferably, the doping concentration of the field stop region is higher than the doping concentration of the drift region.
Preferably, the method further comprises: and the freewheeling diode comprises an anode and a cathode, the bias well region is used as the anode, and the cathode is an N-type doped region penetrating through the collector region to the cut-off region.
Preferably, the first doping type is one of N-type and P-type, and the second doping type is the other of N-type and P-type.
According to another aspect of the present application, there is provided a method of manufacturing a power semiconductor device including a collector region of a first doping type and an emitter region of a second doping type, the first doping type being opposite to the second doping type, comprising: forming a buffer region of a second doping type in a semiconductor substrate, wherein a part of the semiconductor substrate below the buffer region forms a drift region of the second doping type; forming a trench extending from the buffer region surface into the drift region; forming a split gate structure in the trench; forming a well region of a first doping type in the buffer region; forming an emission region in the well region; and forming a field stop region of a second doping type on a surface of the drift region opposite the emission region; and forming a collector region of a first doping type on a surface of a side of the field stop region opposite to the emitter region, wherein the split gate structure includes a first gate conductor, a second gate conductor, and a third gate conductor spaced apart from each other, a first portion of the first gate conductor being located at an upper portion of the trench and sandwiched between the second gate conductor and the third gate conductor, a second portion of the first gate conductor extending to a lower portion of the trench.
Preferably, the step of forming the split gate structure includes: forming an insulating layer on the side wall and the bottom of the groove; forming the first gate conductor in the trench, the insulating layer surrounding the first gate conductor; a gate dielectric and the second and third gate conductors are formed in an upper portion of the trench, wherein the gate dielectric and the second gate conductor form a gate stack and separate the first, second and third gate conductors from each other.
Preferably, the first gate conductor comprises a first portion located at an upper portion of the trench and a second portion located at a lower portion of the trench, the step of forming a gate dielectric and the second and third gate conductors comprising: removing a portion of the insulating layer located on the upper side wall of the trench to form a first opening and a second opening adjacent to the first portion of the first gate conductor; forming a gate dielectric on upper sidewalls of the trench and sidewalls of the first portion of the first gate conductor; forming the second gate conductor in the first opening; and forming the third gate conductor in the second opening, wherein a thickness of the gate dielectric is less than a thickness of the insulating layer, the gate dielectric and the second gate conductor form a gate stack, and the first gate conductor, the second gate conductor, and the third gate conductor are spaced apart from one another.
Preferably, the first gate conductor is a grounded gate, the second gate conductor is a working gate, and the third gate conductor is a floating gate.
Preferably, the second gate conductor surrounds an offset well region of the well region, and the third gate conductor surrounds a floating well region of the well region.
Preferably, a gate conductor is formed over the floating well region, the gate conductor being electrically connected to the second gate conductor.
Preferably, the emitter region is formed in an active area of the well region, the method further comprising: the emitter region is electrically connected to the first gate conductor.
Preferably, the doping concentration of the field stop region is higher than the doping concentration of the drift region.
Preferably, the method further comprises: forming an interlayer dielectric layer over the trench and the emitter region; forming a contact region in the well region, wherein the contact region is of a first doping type and has a doping concentration higher than that of the well region; forming a conductive channel in the interlayer dielectric layer, wherein the conductive channel is in contact with the emitting region and the contact region; and forming an emitter electrode electrically connected with the conductive via.
Preferably, it comprises: a collector electrode is formed in electrical connection with the collector region.
Preferably, the method further comprises: and forming a cathode of the freewheeling diode, wherein the bias well region is used as the anode, and the cathode is an N-type doped region penetrating through the collector region to the cut-off region.
Preferably, the first doping type is one of N-type and P-type, and the second doping type is the other of N-type and P-type.
Compared with the prior art, the power semiconductor device according to the embodiment of the application comprises the split gate structure in the trench. The power semiconductor device realizes separation of gate signals of the power semiconductor device by setting the gate structures with different potentials, thereby achieving the purposes of obtaining lower gate capacitance, improving response time of the device, improving switching speed and reducing switching loss of the device.
The power semiconductor device adopts the split gate structure, so that the Miller capacitance of the device can be effectively reduced, the negative feedback effect of the device in operation is improved, and the stability of the device is improved. The third gate electrode floats and surrounds the floating well region, and local hole charge accumulation can be formed in the region, so that the saturation voltage drop and the conduction loss of the power semiconductor device can be improved.
Furthermore, the floating well region is a closed region and isolated from external signals, so that the anti-interference capability of the device on dv/dt can be improved, and the failure of the power semiconductor device caused by larger dv/dt can be reduced.
Further, the split gate structure extends continuously in the trench, forming a "signal island". Different settings of gate signals are realized on the basis of no extra area of an extra chip through the conductive channel 113, and the flexibility of the structural design of the device is improved.
Further, the method comprises the steps of, the cell structure of the power semiconductor device comprises a groove and a split gate structure which extend in a main plane according to a bent shape. In practice IGBT devices of different parametric performance can be obtained by adjusting the area/number ratio of the effective signal gate and the enclosed region formed by the floating third gate conductor.
Furthermore, the flywheel diode is integrated in the power semiconductor device, and the flywheel diode or the fast recovery diode device is not required to be additionally connected in parallel when the device works, so that the application cost of the device can be effectively reduced.
Drawings
The above and other objects, features and advantages of the present application will become more apparent from the following description of embodiments of the present application with reference to the accompanying drawings, in which:
fig. 1 and 2 show an exploded perspective view and a top view, respectively, of a power semiconductor device according to a first embodiment of the present application;
fig. 3a to 3i show cross-sectional views of a semiconductor device manufacturing method according to a first embodiment of the present application at different stages;
fig. 4 shows a cross-sectional view of a semiconductor device according to a second embodiment of the present application;
fig. 5 shows a gate waveform contrast diagram of a power semiconductor device according to an embodiment of the present application when turned off.
Detailed Description
The application will be described in more detail below with reference to the accompanying drawings. Like elements are denoted by like reference numerals throughout the various figures. For clarity, the various features of the drawings are not drawn to scale. Furthermore, some well-known portions may not be shown. The semiconductor structure obtained after several steps may be depicted in one figure for simplicity.
It will be understood that when a layer, an area, or a structure of a device is described as being "on" or "over" another layer, another area, it can be referred to as being directly on the other layer, another area, or further layers or areas can be included between the other layer, another area, etc. And if the device is flipped, the one layer, one region, will be "under" or "beneath" the other layer, another region.
If, for the purposes of describing a situation directly on top of another layer, another region, the expression "a directly on top of B" or "a directly on top of B and adjoining it" will be used herein. In the present application, "a is directly in B" means that a is in B and a is adjacent to B, instead of a being in the doped region formed in B.
In the present application, the term "semiconductor structure" refers to a generic term for the entire semiconductor structure formed in the various steps of fabricating a semiconductor device, including all layers or regions that have been formed.
Numerous specific details of the application, such as device structures, materials, dimensions, processing techniques and technologies, are set forth in the following description in order to provide a thorough understanding of the application. However, as will be understood by those skilled in the art, the present application may be practiced without these specific details.
Unless specifically indicated below, the various portions of the semiconductor device may be composed of materials known to those skilled in the art. Semiconductor materials include, for example, group III-V semiconductors such as GaAs, inP, gaN, siC, and group IV semiconductors such as Si, ge.
Fig. 1 and 2 show an exploded perspective view and a top view, respectively, of a power semiconductor device according to an embodiment of the present application. For clarity, some parts of the power semiconductor device are shown separated in fig. 1, and, furthermore, some regions are not shown in the figure. It will be appreciated that in actual production, the various parts of the power semiconductor device are grouped together and include regions not shown, thereby forming a complete device structure. Line AA in fig. 2 shows the cut-out position of the subsequent cross-sectional view.
As shown in fig. 1, in the vertical direction of the power semiconductor device 100, the power semiconductor device 100 includes an N-type drift region 101, an N-type buffer region 102, and a P-type well region 109, which are stacked in order. The doping concentration of the N-type buffer region 102 is higher than the doping concentration of the N-type drift region. Trench 103 extends from the surface of P-type well region 109 through N-type buffer region 102 into N-type drift region 101 to a predetermined depth. A split gate structure is formed in trench 103, including an insulating layer 104 on a lower sidewall of trench 103, a first gate conductor 105, a second gate conductor 106, and a third gate conductor 107 formed in trench 103, and a gate dielectric 108 separating the three from each other. Further, a gate dielectric 108 is also located on upper sidewalls of trench 103, separating second gate conductor 106 and third gate conductor 107 from P-type well region 109. The thickness of the gate dielectric 108 is less than the thickness of the insulating layer 104.
An N-type emitter region 111 and a P-type contact region 110 are formed in the P-type well region 109. The P-type contact region 110 is heavily doped relative to the P-type well region 109. Conductive via 113 is in contact with both N-type emitter region 111 and P-type contact region 110. Further, the emitter electrode is connected to the conductive path 113.
Although not shown in the drawings, a stacked N-type field stop region, P-type collector region, and collector electrode are formed in the surface of the N-type drift region 101 opposite to the surface where the emitter region 111 is formed. The doping concentration of the N-type field stop region is higher than that of the N-type drift region 101.
In the trench 103, a second gate conductor 106 and a third gate conductor 107 are located at an upper portion of the trench 103, and the first gate conductor 105 extends from the upper portion to a lower portion of the trench 103, including a first portion and a second portion located at the upper portion and the lower portion of the trench 103, respectively. An upper portion of the first gate conductor 105 is located between the second gate conductor 106 and the third gate conductor 107. In this embodiment, the width of the first portion of the first gate conductor 105 is smaller than the width of the second portion. Further, the first gate conductor 105, the second gate conductor 106 and the third gate conductor 107 are separated from each other by a gate dielectric 108. In this embodiment, the first gate conductor 105 is grounded (e.g., with the emitter of the power semiconductor device 100), the second gate conductor 106 is the working gate of the power semiconductor device 100, and the third gate conductor 107 is floating.
As shown in fig. 2, in the main plane of the power semiconductor device 100, the trench 103 and the split gate structure therein form a plurality of U-shaped structures interconnected with each other, including an emitter interconnect region ZA, a split gate extension region ZB, and a split gate interconnect region ZC. In the emitter interconnect region ZA, an N-type emitter region 111 and a P-type contact region 110, and a conductive path 113 interconnecting the two are formed. Preferably, if the emitter region 111 of the power semiconductor device 100 is grounded in a use state, the first gate conductor 105 may be connected to the emitter region 111 in the emitter interconnection region ZA, thereby achieving the grounding of the first gate conductor 105. In the split gate extension region ZB, the trench 103 and the split gate structure therein extend in a bent shape. In the split gate interconnect region ZC, the trenches 103 and the split gate structures therein are connected to adjacent U-shaped structures to form a grid pattern. The power semiconductor device 100 forms a signal island with the third gate conductors 107 adjoining each other and extending continuously, in which region, for example, a gate electrode connected to the second gate conductor 106 can be formed.
Further, the P-type well region 109 includes a first portion 109-1 surrounded by the second gate conductor 106, and a second portion 109-2 surrounded by the third gate conductor 107. In this embodiment, the first portion 109-1 of the P-type well region 109 is an offset well region of the power semiconductor device 100 and the second portion 109-2 is located near the floating third gate conductor 107, thereby forming a floating well region. And setting the area ratio of the bias well region and the floating well region according to the performance parameters of the power semiconductor device. In the power semiconductor device, if the area ratio of the floating well region is increased relative to the bias well region, the on-loss can be reduced, but at the same time, the parasitic capacitance can be increased, and the switching speed of the device can be reduced. Thus, a suitable area ratio may be set to trade off the loss of the power semiconductor device and the switching speed requirements.
The N-type emitter region 111 and the P-type contact region 110 of the power semiconductor device 100 are both located in the first portion 109-1 of the P-type well region 109, i.e., in the offset well region of the power semiconductor device 100. In the signal island, the first gate conductor 105 and the third gate conductor 107, which extend continuously, surround the second portion 109-2 of the P-type well region 109, thereby forming a gate electrode connected to the second gate conductor 106 in the floating well region of the power semiconductor device 100 to reduce the miller capacitance.
According to the power semiconductor device of the embodiment, the miller capacitance can be effectively reduced by adopting the split gate structure, so that the negative feedback effect in operation is improved, and the working stability is improved. Meanwhile, by providing the floating third gate electrode 107, a closed floating well region is formed in the P-type well region 109, and local hole charge accumulation is formed inside the region, so that the saturation voltage drop and the on-loss of the power semiconductor device can be improved.
Further, since the floating well region of the P-type well region 109 is completely closed and isolated from external signals, the anti-interference capability of the device on dv/dt can be improved, and the failure of the power semiconductor device caused by larger dv/dt can be reduced. In addition, the power semiconductor device forms a signal island with the third gate conductors 107 that adjoin each other and extend continuously, in which region, for example, a gate electrode connected to the second gate conductor 106 can be formed.
Further, the interconnection between the emitter region 111 and the P-type well region 109 is realized through the conductive channel 113, so that different settings of gate signals are realized on the basis of no extra area of an extra chip, and the flexibility of the structural design of the device is improved.
Further, the power semiconductor device includes an N-type field stop region between the N-type drift region 101 and the P-type collector region. The N-type cut-off region is a heavily doped N-type semiconductor layer adjacent to and in contact with the N-type drift region 101 such that the electric field is drastically reduced within the field cut-off region, thereby accelerating majority carrier recombination at the turn-off instant. The field stop region improves avalanche resistance of the power semiconductor device and reduces tail current thereby reducing switching losses.
Fig. 3a to 3i show cross-sectional views of different stages of a method of manufacturing a semiconductor device according to an embodiment of the application. The cut-out position of the cross-sectional view is located in the emitter interconnect zone ZA of the power semiconductor device 100, as indicated by line AA in fig. 2.
The method begins with a semiconductor substrate. The semiconductor substrate is, for example, a silicon substrate doped to an N-type, and the silicon substrate is uniformly doped in a longitudinal direction and has a resistivity in a range of, for example, 1 to 15 Ω·cm. The semiconductor substrate has opposite first and second surfaces. Preferably, the voltage dividing ring structure of the power semiconductor is formed on the first surface of the semiconductor substrate through photolithography, etching, ion implantation, impurity activation and other processes, and the voltage dividing ring structure is a well-known structural part of the device structure in the art, and will not be described in detail herein.
An N-type buffer region 102 is formed on a first surface of the semiconductor substrate such that an N-type drift region 101 is formed at a portion of the semiconductor substrate under the N-type buffer region 102, as shown in fig. 3 a. The N-type buffer region 102 extends downward from the first surface of the semiconductor substrate to a predetermined depth and has a higher doping concentration than the N-type drift region 101. The process for forming the N-type buffer 102 includes forming a resist mask by photolithography and etching, performing ion implantation through an opening of the resist mask, then removing the resist mask, and performing thermal annealing to activate impurities.
Then, a trench 103 is formed in the first surface of the semiconductor substrate, and an insulating layer 104 is filled in the trench 103, as shown in fig. 3 b. The trench 103 extends downward from the surface of the N-type buffer region 102 and reaches a predetermined depth in the N-type drift region 101. The process for forming the trench 103 includes forming a resist mask by photolithography and etching, removing the exposed portion of the N-type buffer region 102 via the opening etching of the resist mask, and further removing the exposed portion of the N-type drift region 101. The process for forming the insulating layer 104 includes forming an oxide layer 104 on the inner wall of the trench 103 by thermal oxidation. The oxide layer 104 conformally covers the sidewalls and bottom of the trench 103, thereby still preserving a portion of the interior space of the trench 103.
Then, a first gate conductor 105 is formed in the trench 103 lined with an oxide layer 104, as shown in fig. 3 c. The first gate conductor 105 is composed of doped polysilicon, for example. The process for forming the first gate conductor 105 includes depositing polysilicon using a sputtering or the like process such that the polysilicon fills the remainder of the trench 103, and removing polysilicon located outside the trench 103 using Chemical Mechanical Planarization (CMP) such that the polysilicon filling the trench 103 forms the first gate conductor 105.
Then, a gate dielectric 108 and a second gate conductor 106 and a third gate conductor 107 are formed in the upper portion of the trench 103, as shown in fig. 3 d. The gate dielectric 108 is composed of, for example, silicon oxide and has a thickness smaller than that of the insulating layer 104. The process for forming gate dielectric 108 includes removing portions of oxide layer 104 located at an upper portion of trench 103 using an etch to form a first opening and a second opening adjacent to a first portion of first gate conductor 105. The first and second openings expose sidewall surfaces of the upper portion of the trench 103, and the first gate conductor 105 is located on the sidewall surface of the upper portion of the trench 103. Further, a gate dielectric 108 is formed by oxidizing the sidewall surface of the upper portion of the trench 103 and the sidewall surface of the corresponding portion of the first gate conductor 105 using thermal oxidation. The process for forming the second gate conductor 106 and the third gate conductor 107 is the same as the process for forming the first gate conductor 105 and will not be described in detail here. The second gate conductor 106 is located in the first opening and the third gate conductor 107 is located in the second opening.
In this step, a split gate structure is formed. A split gate structure is formed in trench 103, including a first gate conductor 105, a second gate conductor 106, and a third gate conductor 107 located in trench 103, and a gate dielectric 108 separating the three from one another. Further, a gate dielectric 108 is also located on upper sidewalls of trench 103. The first gate conductor 105 extends from an upper portion to a lower portion of the trench 103, including first and second portions located at the upper and lower portions of the trench 103, respectively. An insulating layer 104 is located on the lower sidewalls of the trench 103 and surrounds a second portion of the first gate conductor 105. An upper portion of the first gate conductor 105 is located between the second gate conductor 106 and the third gate conductor 107. Since the sidewall surface of the first gate conductor 105 at the upper portion of the trench 103 is thermally oxidized to be converted into the gate dielectric 108, the width of the first portion of the first gate conductor 105 is smaller than the width of the second portion.
Then, a P-type well region 109 is formed on the surface of the N-type buffer region 102, as shown in fig. 3 e. The P-type well region 109 extends downward from the surface of the N-type buffer region 102 to a predetermined depth. The process for forming P-type well region 109 is substantially the same as N-type buffer region 102, except that the dopant type is opposite and the depth of P-type well region 109 is less than the depth of N-type buffer region 102.
The trench 103 that has been formed before this step extends from the surface of the P-type well region 109 into the N-type drift region 101 via the N-type buffer region 102 to a predetermined depth. The depth of the P-type well region 109 is equal to or less than the depths of the second gate conductor 106 and the third gate conductor 107. Thus, in the upper portion of trench 103, gate dielectric 108 separates second gate conductor 106 and third gate conductor 107 from P-type well region 109. In the lower portion of the trench 103, an insulating layer 104 is used to separate a second portion of the first gate conductor 105 from the N-type buffer region 102. In this embodiment, the second gate conductor 106 and the gate dielectric 108 will be the active gate stack of the power semiconductor device 100.
Then, an N-type emitter 111 is formed on the surface of the P-type well 109, as shown in fig. 3 f. The N-type emitter region 111 extends downward from the surface of the P-type well region 109 to a predetermined depth. The process for forming N-type emitter region 111 is substantially the same as N-type buffer region 102, except that the depth of N-type emitter region 111 is less than the depth of P-type well region 109, and will not be described in detail herein.
It should be noted that the N-type emitter region 111 is formed in a portion of the P-type well region 109 adjacent to the second gate conductor 106, but is not formed in another portion of the P-type well region 109 adjacent to the third gate conductor 107. Referring to fig. 2, the trench 103 extends in a bent shape in a main plane of the power semiconductor device, and an N-type emitter 111 is formed in a region surrounded by the second gate conductor 106 formed in the trench 103.
An interlayer dielectric layer 112 is then deposited on the surface of the semiconductor structure. The interlayer dielectric layer may be, for example, borophosphosilicate glass (BPSG) having a thickness of 600 nanometers to 1.5 micrometers. A contact hole is formed in the interlayer dielectric layer 112 by etching or the like. Preferably, ion implantation is performed through the contact hole, forming a P-type contact region 110 in the P-type well region 109. Further, a conductive via 113 is formed in the contact hole. Conductive via 113 is in contact with both N-type emitter region 111 and P-type contact region 110, as shown in fig. 3 g.
Then, after filling the contact hole of the interlayer dielectric layer 112 with a metal, the formed metal layer is etched through a mask, thereby patterning the metal layer into the emitter electrode 114, as shown in fig. 3 h. The emitter electrode 114 is connected to the conductive path 113.
Then, a stacked N-type field stop region 115, P-type collector region 116, and collector electrode 117 are formed in the surface of the N-type drift region 101 opposite to the surface where the emitter region 111 is formed, as shown in fig. 3 i. The doping concentration of the N-type field stop region 115 is higher than the doping concentration of the N-type drift region 101. Preferably, a thinning process is employed to reduce the thickness of N-type drift region 101 prior to forming N-type field stop region 115. The process for forming the N-type drift region 101 and the P-type collector region 116 includes forming a doped region of a corresponding doping concentration in the N-type drift region 101 by ion implantation, and performing thermal annealing to activate the impurities. The process for forming the collector electrode 117 is the same as the process for forming the emitter electrode 114, and will not be described in detail herein.
Preferably, after the step of forming the collector electrode 117 and the emitter electrode 114, the remaining predetermined thickness region and the deposited metal layer are heat-treated under vacuum or nitrogen atmosphere. The heat treatment temperature and time are insufficient to melt the metal layer of the power semiconductor device.
Further, as shown in fig. 2, in the emitter interconnect zone ZA, the ground of the first gate conductor 105 is provided. The first gate conductor 105 and the emitter region 111 may be connected to each other if the emitter region 111 of the power semiconductor device 100 is grounded in the use state. In the split gate interconnect region ZC, adjacent U-shaped structures are connected to each other forming a grid pattern, wherein the continuously extending third gate conductors 107 form signal islands. A gate electrode connected to the second gate conductor 106 is formed in the signal island. The third gate conductor 107 is suspended.
Fig. 4 shows a cross-sectional view of a semiconductor device according to a second embodiment of the present application. The semiconductor device according to the second embodiment is different from the semiconductor device according to the first embodiment in that it includes an embedded flywheel diode, and otherwise is substantially the same. As shown in fig. 4, the anode of the freewheeling diode is an offset well region of the well region 109, and the cathode 118 is an N-doped region penetrating the collector region 116 to the stop region 115. Cathode 118 is in contact with both P-type collector 116 and N-type field stop region 115. Further, a collector electrode 117 is connected to both the P-type collector region 116 and the cathode 118. The process for forming the cathode 118 includes, for example, ion implantation in the P-type collector region 116 to form an N-type doped region extending from the surface of the P-type collector region 116 to the N-type field stop region 115. The process for forming collector electrode 117 includes, for example, depositing a conductive layer overlying the surfaces of cathode 118 and collector region 116.
According to the power semiconductor device of the second embodiment, the flywheel diode is integrated inside, and when the device works, an additional flywheel diode or a fast recovery diode device is not required to be connected in parallel, so that the application cost of the device can be effectively reduced.
Fig. 5 shows a gate waveform contrast diagram of a power semiconductor device according to an embodiment of the present application when turned off. Compared with the power semiconductor device with the traditional IEGT structure, the emitter-collector voltage VCE during the turn-off period of the power semiconductor device with the structure eliminates a miller platform in time, and the saturation voltage is rapidly reduced to zero, so that the response speed is improved and the switching loss is reduced.
It should be noted that in this document relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.
Embodiments in accordance with the present application, as described above, are not intended to be exhaustive or to limit the application to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the application and the practical application, to thereby enable others skilled in the art to best utilize the application and various modifications as are suited to the particular use contemplated. The application is limited only by the claims and the full scope and equivalents thereof.

Claims (25)

1. A power semiconductor device, comprising:
a collector region of a first doping type;
a field stop region of a second doping type on the collector region, the second doping type being opposite to the first doping type;
a drift region of a second doping type located on the field stop region;
a buffer region of a second doping type located on the drift region;
a well region of a first doping type located on the buffer region;
an emitter region of a second doping type located in the well region;
a trench extending downward from the well region surface, through the well region and the buffer region, to the drift region; and
a split gate structure in the trench,
the split gate structure comprises a first gate conductor, a second gate conductor and a third gate conductor which are separated from each other, wherein a first part of the first gate conductor is located at the upper part of the groove and clamped between the second gate conductor and the third gate conductor, a second part of the first gate conductor extends to the lower part of the groove, the first gate conductor is a grounded gate, the second gate conductor is a working gate, and the third gate conductor is a floating gate.
2. The power semiconductor device of claim 1, further comprising: a gate dielectric on the trench upper sidewalls and a first portion of the sidewalls of the first gate conductor, the gate dielectric and the second gate conductor forming a gate stack and separating the first gate conductor, the second gate conductor and the third gate conductor from each other.
3. The power semiconductor device of claim 2, further comprising: an insulating layer on a lower sidewall of the trench, the insulating layer separating the second portion of the first gate conductor from the well region and the drift region, the gate dielectric having a thickness less than a thickness of the insulating layer.
4. A power semiconductor device according to claim 3, wherein the second gate conductor surrounds an offset well region of the well region and the third gate conductor surrounds a floating well region of the well region.
5. The power semiconductor device of claim 4, wherein an area ratio of the bias well region and the floating well region is set according to a performance parameter of the power semiconductor device.
6. The power semiconductor device of claim 4 further comprising a gate conductor formed over said floating well region, said gate conductor being electrically connected to said second gate conductor.
7. The power semiconductor device of claim 4 wherein the emitter region is formed in an active area of the well region and the emitter region is electrically connected to the first gate conductor.
8. The power semiconductor device of claim 3, further comprising:
an interlayer dielectric layer located above the trench and the emitter region;
the contact region is positioned in the well region, is of a first doping type and has a doping concentration higher than that of the well region;
a conductive path through the interlayer dielectric layer contacting the emitter region and the contact region; and
and an emitter electrode electrically connected with the conductive channel.
9. The power semiconductor device of claim 3, further comprising:
and a collector electrode electrically connected to the collector region.
10. The power semiconductor device of claim 4 wherein said trench extends in a serpentine shape in a main plane of the power semiconductor device, thereby defining said offset well region and said floating well region.
11. The power semiconductor device of claim 8 wherein the trench forms a plurality of U-shaped structures connected to one another in a grid pattern, the split gate structures extend continuously in the trench, and in the grid pattern, the area surrounded by the third gate conductor forms a signal island.
12. The power semiconductor device of claim 4 wherein a doping concentration of said field stop region is higher than a doping concentration of said drift region.
13. The power semiconductor device of claim 12, further comprising: and the freewheeling diode comprises an anode and a cathode, the bias well region is used as the anode, and the cathode is an N-type doped region penetrating through the collector region to the cut-off region.
14. The power semiconductor device of any of claims 1-13, wherein the first doping type is one of N-type and P-type and the second doping type is the other of N-type and P-type.
15. A method of manufacturing a power semiconductor device comprising a collector region of a first doping type and an emitter region of a second doping type, the first doping type being opposite to the second doping type, comprising:
forming a buffer region of a second doping type in a semiconductor substrate, wherein a part of the semiconductor substrate below the buffer region forms a drift region of the second doping type;
forming a trench extending from the buffer region surface into the drift region;
forming a split gate structure in the trench;
forming a well region of a first doping type in the buffer region;
forming an emission region in the well region; and
forming a field stop region of a second doping type on a surface of the drift region opposite to the emission region;
and forming a collector region of the first doping type on a surface of a side of the field stop region opposite to the emitter region,
the split gate structure comprises a first gate conductor, a second gate conductor and a third gate conductor which are separated from each other, wherein a first part of the first gate conductor is located at the upper part of the groove and clamped between the second gate conductor and the third gate conductor, a second part of the first gate conductor extends to the lower part of the groove, the first gate conductor is a grounded gate, the second gate conductor is a working gate, and the third gate conductor is a floating gate.
16. The method of claim 15, wherein forming a split gate structure comprises:
forming an insulating layer on the side wall and the bottom of the groove;
forming the first gate conductor in the trench, the insulating layer surrounding the first gate conductor;
forming a gate dielectric and the second and third gate conductors in an upper portion of the trench,
wherein the gate dielectric and the second gate conductor form a gate stack and separate the first gate conductor, the second gate conductor and the third gate conductor from each other.
17. The method of claim 16, wherein the first gate conductor comprises a first portion located at an upper portion of the trench and a second portion located at a lower portion of the trench, the forming a gate dielectric and the second and third gate conductors comprising:
removing a portion of the insulating layer located on the upper side wall of the trench to form a first opening and a second opening adjacent to the first portion of the first gate conductor;
forming a gate dielectric on upper sidewalls of the trench and sidewalls of the first portion of the first gate conductor;
forming the second gate conductor in the first opening; and
forming the third gate conductor in the second opening,
wherein the thickness of the gate dielectric is less than the thickness of the insulating layer,
the gate dielectric and the second gate conductor form a gate stack and separate the first gate conductor, the second gate conductor, and the third gate conductor from one another.
18. The method of claim 17, wherein the second gate conductor surrounds an offset well region of the well region and the third gate conductor surrounds a floating well region of the well region.
19. The method of claim 18, further comprising forming a gate conductor over the floating well region, the gate conductor electrically connected to the second gate conductor.
20. The method of claim 19, wherein the emitter region is formed in an active area of the well region, the method further comprising: the emitter region is electrically connected to the first gate conductor.
21. The method of claim 17, wherein a doping concentration of the field stop region is higher than a doping concentration of the drift region.
22. The method of claim 17, further comprising:
forming an interlayer dielectric layer over the trench and the emitter region;
forming a contact region in the well region, wherein the contact region is of a first doping type and has a doping concentration higher than that of the well region;
forming a conductive channel in the interlayer dielectric layer, wherein the conductive channel is in contact with the emitting region and the contact region; and
an emitter electrode is formed in electrical connection with the conductive via.
23. The method of claim 17, further comprising:
a collector electrode is formed in electrical connection with the collector region.
24. The method of claim 18, further comprising: and forming a cathode of the freewheel diode, wherein the bias well region is used as an anode of the freewheel diode, and the cathode is an N-type doped region penetrating through the collector region to reach the cut-off region.
25. The method of any of claims 15 to 24, wherein the first doping type is one of N-type and P-type and the second doping type is the other of N-type and P-type.
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013214551A (en) * 2012-03-30 2013-10-17 Toshiba Corp Semiconductor device and manufacturing method of the same
CN103579311A (en) * 2012-07-27 2014-02-12 株式会社东芝 Semiconductor device
CN105027295A (en) * 2013-08-06 2015-11-04 富士电机株式会社 Trench gate mos semiconductor device and method for manufacturing same
CN105027292A (en) * 2013-04-11 2015-11-04 富士电机株式会社 Semiconductor device and semiconductor device manufacturing method
CN105870180A (en) * 2016-04-26 2016-08-17 电子科技大学 Double split trench gate charge storage-type RC-IGBT and manufacturing method thereof
CN206422071U (en) * 2017-01-25 2017-08-18 杭州士兰集成电路有限公司 Power semiconductor

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4817827B2 (en) * 2005-12-09 2011-11-16 株式会社東芝 Semiconductor device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013214551A (en) * 2012-03-30 2013-10-17 Toshiba Corp Semiconductor device and manufacturing method of the same
CN103579311A (en) * 2012-07-27 2014-02-12 株式会社东芝 Semiconductor device
CN105027292A (en) * 2013-04-11 2015-11-04 富士电机株式会社 Semiconductor device and semiconductor device manufacturing method
CN105027295A (en) * 2013-08-06 2015-11-04 富士电机株式会社 Trench gate mos semiconductor device and method for manufacturing same
CN105870180A (en) * 2016-04-26 2016-08-17 电子科技大学 Double split trench gate charge storage-type RC-IGBT and manufacturing method thereof
CN206422071U (en) * 2017-01-25 2017-08-18 杭州士兰集成电路有限公司 Power semiconductor

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