CN111725306B - Groove type power semiconductor device and manufacturing method thereof - Google Patents
Groove type power semiconductor device and manufacturing method thereof Download PDFInfo
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- CN111725306B CN111725306B CN201910220539.0A CN201910220539A CN111725306B CN 111725306 B CN111725306 B CN 111725306B CN 201910220539 A CN201910220539 A CN 201910220539A CN 111725306 B CN111725306 B CN 111725306B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
Abstract
The invention relates to a trench type power semiconductor device and a manufacturing method thereof, which aims to solve the problems of improving the manufacturing cost of the device and increasing parasitic gate capacitance caused by the existence of a gate bus and provides the following technical scheme: a gate contact hole is arranged in the interlayer dielectric layer above the groove starting section, a gate conductive material in the groove is connected with the gate electrode metal layer above the groove through the gate contact hole, the width of the gate contact hole is smaller than that of the groove starting section, and the width of the groove starting section is larger than that of the groove extending section. The invention has the beneficial effects that: the trench type power semiconductor device can realize stable and reliable gate connection on the basis of not negatively affecting the performance of the device, and reduces the photoetching process steps of the device by omitting a gate bus plate, reduces the manufacturing cost of the device, reduces the parasitic capacitance of the gate introduced by the gate bus plate, and improves the switching speed of the device.
Description
Technical Field
The present invention relates to the structural design and fabrication methods of Power semiconductor devices, and in particular, trench Power transistors such as Insulated Gate Bipolar Transistors (IGBTs) and Power metal oxide semiconductor field effect transistors (Power MOSFETs).
Background
The power transistor is a key component of a power electronic system and is widely applied to various application systems such as motor driving, electric energy conversion and the like. Generally, power transistors mainly include Power metal oxide semiconductor field effect transistors (Power MOSFETs), insulated Gate Bipolar Transistors (IGBTs), and the like, the former are mainly applicable to medium-low voltage (600V or less) low-Power systems, and the latter are mainly applicable to medium-high voltage high-Power (600V or more) high-Power systems. From the structure of the power transistor, two structures, namely a planar gate and a trench gate, are mainly adopted, wherein the trench gate structure can improve the cell density, reduce the channel resistance, realize more excellent forward conduction characteristics and become the main stream structure of the current power transistor device.
Fig. 1 illustrates a partial top view schematic of a prior art trench IGBT device 100. On the device 100The surface is provided with an emitter metal layer (113) and a gate metal layer (114) which are respectively used as an emitter electrode and a gate electrode of the device 100, wherein a gate bus plate (121) is arranged below the gate metal layer (114), and the gate bus plate (121) is generally made of a heavily doped polycrystalline silicon material and is connected to the gate metal layer (114) through a gate contact hole (116); the area covered below the emitter metal layer (113) is an active area for conducting current, and the emitter metal layer (113) is connected with the active area below the emitter metal layer through an emitter contact hole (112); in addition, the device 100 has a series of trenches (105) arranged in a flat shape, the trenches (105) extend from the lower side of the gate bus plate (121) into the active region below the emitter metal layer (113), and the trenches (105) are filled with gate conductive material generally composed of heavily doped polysilicon for conducting gate signals, thereby controlling on and off of cells in the active region; the grid groove (105) is isolated from the emitter electrode (113) above the grid groove through an insulating medium layer. The cross-sectional structure corresponding to the tangent line M-M' in the active region in FIG. 1 is shown in FIG. 2. As shown in FIG. 2, the bottom of the device 100 has a collector (101) composed of a metal layer, a semiconductor region above the collector (101) and p's respectively from bottom to top + Collector doping region (102), n-type electric field stop layer (103), and n - A type drift region (104); the trench (105) extends downwards from the upper surface of the semiconductor region into n - The method comprises the steps that in a type drift region (104), a polysilicon conductive material (107) is filled in a groove (105), the polysilicon conductive material (107) is isolated from the groove (105) by a gate dielectric layer (106), and the structural material of the gate dielectric layer (106) is silicon dioxide generally; a p-type body region (108) is arranged between adjacent grooves (105), and n is arranged above the p-type body region (108) + Emitter region (110) and p + A contact region (109), and n + The shaped emitter region (110) adjoins one side wall of the trench (105); an interlayer dielectric layer (111) is arranged above the groove (105), and the interlayer dielectric layer (111) isolates the groove (105) from the emitter electrode (113); an emitter electrode (113) is connected with n through an emitter contact hole (112) in the interlayer dielectric layer (111) + Emitter region (110) and p + The shaped contact areas (109) are connected.
When the device 100 is operated in a forward on state, a positive voltage is applied to the gate electrode (114) and conducted to the polysilicon conductive material (107) within the trench (105), which in turn forms an electron inversion layer at the interface of the p-type body region (108) and the sidewalls of the trench (105) as a conductive channel for electrons, while the collector (101) is connected to a forward voltage and the emitter (113) is connected to a low potential, thereby forming a current between the collector (101) and the emitter (113).
As described above, the polysilicon conductive material (107) in the trench (105) of the prior art device 100 needs to be connected to the gate bus plate (121) first and then to the gate electrode (114) through the gate contact hole (116) on the bus plate (121). Thus, during the fabrication of the device 100, the polysilicon material needs to be subjected to photolithography after filling the gate trench (105) with polysilicon conductive material to preserve the polysilicon material at the gate bus plate (121) and within the trench (105); the gate bus plate (121) is typically 20 μm or more in width so as to provide sufficient space for the gate contact holes (116) and reduce parasitic gate resistance of the bus plate (121) itself. However, the process of forming the gate bus plate (121) requires an additional planar photolithography process of one-step gate conductive material, thereby increasing the manufacturing cost of the device; in addition, the gate bus plate (121) and the semiconductor surface are isolated by the gate dielectric layer (106), and the thickness of the gate dielectric layer (106) is generally smaller (about 50-100 nm), so that the gate bus plate (121) can introduce additional parasitic gate capacitance in a gate loop of the device, which has adverse effects on the switching speed and switching loss of the device.
In order to avoid the problems of high manufacturing cost of the device, parasitic gate capacitance and the like caused by the gate bus plate (121), one scheme is to etch the gate contact hole directly above the trench (105), thereby omitting the gate bus plate (121). However, in order to reduce the parasitic capacitance of the gate electrode introduced by the trench (105) to increase the switching speed of the device, the surface area of the trench (105) needs to be reduced, which results in that the width of the trench (105) is generally set to be narrow (about 1 μm), while in the device processing process, the contact hole lithography process often has a certain alignment deviation, if the contact hole on the gate electrode trench is slightly deviated, the short circuit between the gate electrode and the emitter electrode is very easy to be caused, the process risk is too high, and the high-precision lithography alignment process increases the manufacturing difficulty and the cost of the device, so that the device is not damaged.
Disclosure of Invention
According to the above-mentioned trench power transistor of the prior art, that is, the problem that the existence of the gate bus leads to the increase of the manufacturing cost of the device and the parasitic gate capacitance, it is necessary to provide an innovative design and manufacturing scheme of the gate connection structure, and on the premise of firm and reliable connection structure, the manufacturing cost of the device is reduced, the parasitic gate capacitance is reduced, and the switching performance of the device is improved.
The specific technical scheme provided by the invention is described below.
The invention aims to provide a groove type power semiconductor device, which comprises a collector metal layer positioned at the bottom of the device;
the semiconductor region is positioned above the collector metal layer and comprises a second conduction type collector doping region, a first conduction type electric field stop layer and a first conduction type drift region from bottom to top; more than one parallel arranged groove extending into the semiconductor region from the upper surface of the semiconductor region is also arranged in the semiconductor region, the groove is filled with a grid conductive material, and a grid dielectric layer is arranged between the grid conductive material and the inner wall of the groove;
an interlayer dielectric layer located on the semiconductor region;
the emitter electrode metal layer and the gate electrode metal layer are positioned on the interlayer dielectric layer, wherein a groove positioned below the gate electrode metal layer forms a groove starting section, and a groove positioned below the emitter electrode metal layer forms a groove extending section;
and a gate contact hole is formed in the interlayer dielectric layer above the groove starting section, a gate conductive material in the groove is connected with the gate electrode metal layer above the groove through the gate contact hole, the width of the gate contact hole is smaller than that of the groove starting section, and the width of the groove starting section is larger than that of the groove extending section.
Further, the width of the groove starting section is 1.2-1.8 mu m, and the width of the groove extending section is 0.6-1.2 mu m.
Further, a second conductive type buffer doped region is arranged around the initial section of the groove, and the junction depth of the second conductive type buffer doped region is greater than or equal to the depth of the initial section of the groove.
Furthermore, one side edge of the second conductive type buffer doped region extends to the lower part of the emitter electrode metal layer and is connected with the emitter electrode metal layer through an emitter contact hole in the interlayer dielectric layer.
Furthermore, more than one pseudo groove is arranged in the semiconductor region and positioned below the emitter electrode metal layer, and the pseudo groove is connected with the emitter electrode metal layer through a pseudo gate contact hole arranged above the initial section of the pseudo groove.
Further, the width of the initial section of the pseudo groove is larger than that of the extension section of the pseudo groove.
Further, a second conductive type buffer doped region is arranged around the initial section of the pseudo groove, and the junction depth of the second conductive type buffer doped region is larger than or equal to the depth of the initial section of the pseudo groove.
Further, emitter contact holes are not formed in the surface of the semiconductor region between the adjacent dummy trenches.
Further, the starting segments of adjacent pseudo-trenches are connected to form a continuous "U" shaped pseudo-trench.
Further, two symmetrically arranged U-shaped pseudo grooves are connected in the extension section to form a closed O-shaped pseudo groove.
Furthermore, an electrically floating doped region of the second conductivity type is arranged between two adjacent dummy trench extensions.
Further, the starting segments of adjacent grooves are connected to form a continuous "U" shaped groove.
Further, two symmetrically arranged U-shaped grooves are connected in the extension section to form a closed O-shaped groove.
Another object of the present invention is to provide a method for manufacturing a trench type power semiconductor device, the method comprising the steps of:
(1) Forming a first conductivity type drift region in a semiconductor substrate;
(2) Forming a second conduction type buffer doping region on the corresponding position of the surface of the first conduction type drift region in a photoetching and ion implantation mode, wherein the second conduction type buffer doping region is formed synchronously with a second conduction type field wire ring doping region commonly used for a terminal voltage-withstanding region of the power device;
(3) Etching a groove on the surface of a semiconductor substrate, and realizing that the width 'y' of the groove at the initial section is larger than the width 'x' of the groove at the extension section through a photoetching pattern, wherein the depth'd 2' of the groove at the initial section is also larger than the depth'd 1' of the groove at the extension section, so that a pseudo groove can be synchronously etched in the step;
(4) Forming a gate dielectric layer on the inner wall of the trench, and filling the trench with a gate conductive material;
(5) Carrying out back etching on the gate conductive material, completely removing the gate conductive material on the upper surface of the semiconductor region, and only keeping the gate conductive material in the groove, wherein the process does not need a photoetching plate;
(6) Forming a second conductive type body region, a first conductive type emitter region and a second conductive type contact region between the extension sections of the adjacent trenches;
(7) Depositing an interlayer dielectric layer on the surfaces of the semiconductor region and the groove;
(8) Photoetching an interlayer dielectric layer, forming an emitter contact hole between extension sections of adjacent grooves, and forming a gate contact hole above an initial section of each groove;
(9) Depositing a metal layer on the surface of the interlayer dielectric layer, and forming an emitter electrode metal layer and a gate electrode metal layer by photoetching;
(10) And thinning the back of the semiconductor region, forming a first conductive type electric field cut-off layer and a second conductive type collector doping region under the first conductive type drift region in an ion implantation and/or diffusion mode, and then depositing a metal layer on the back of the device to form a collector metal layer to manufacture the device.
In the trench type power semiconductor device structure of the present invention, the gate conductive material (207) in the trench (205) is directly connected to the gate electrode metal layer (214) through the gate contact hole (216) above the starting section of the trench (205), thereby omitting the gate bus plate, compared with the trench type power semiconductor device 100 of the prior art, the photolithography step of the gate conductive material can be saved, the manufacturing cost of the device can be reduced, and the parasitic gate capacitance introduced by the gate bus plate can be avoided.
In addition, since the gate contact hole (216) is positioned at the initial section of the trench (205), and the width of the initial section of the trench (205) is set to be wider, more margin can be reserved for the photoetching alignment deviation of the gate contact hole (216); on the other hand, the device is used for arranging the extending section of the groove (205) in the conductive active area, and the width of the extending section of the groove (205) is smaller, so that extra grid parasitic capacitance is not increased, the switching speed of the device is increased, and the switching loss is reduced. Considering the loading effect of the trench etching, the larger width of the starting section of the trench (205) results in a faster etching speed, so that the depth of the starting section of the trench (205) is greater than the depth of the extension section of the trench (205); in order to avoid adverse effects on the breakdown voltage of the device caused by the increase of the depth of the initial section of the groove (205), a p-type buffer doped region (215) is arranged around the initial section of the groove (205), the junction depth of the p-type buffer doped region (215) is larger than or equal to the depth of the initial section of the groove (205), and in the voltage-resistant state of the device, the p-type buffer doped region (215) can effectively reduce the electric field near the initial section of the groove (205) and maintain the breakdown voltage of the device; in addition, according to the manufacturing method provided by the invention, the p-type buffer doped region (215) can be formed synchronously with a p-type field line ring doped region (not shown in the document) commonly used for a device terminal voltage-resistant region, so that no extra photolithography and process steps are added.
In summary, the beneficial effects of the invention are as follows: the trench type power semiconductor device can realize stable and reliable gate connection on the basis of not negatively affecting the performance of the device, and reduces the photoetching process steps of the device by omitting a gate bus plate, reduces the manufacturing cost of the device, reduces the parasitic capacitance of the gate introduced by the gate bus plate, and improves the switching speed of the device.
Drawings
Fig. 1 is a partial top view schematic diagram of a prior art trench IGBT device 100.
Fig. 2 is a schematic cross-sectional view of a line corresponding to line M-M' of the device 100 of fig. 1.
Fig. 3 is a partial top view schematic diagram of an IGBT device 200 according to a first embodiment of the invention.
Fig. 4 isbase:Sub>A schematic cross-sectional view ofbase:Sub>A line corresponding to linebase:Sub>A-base:Sub>A' of the device 200 of fig. 3.
Fig. 5 is a schematic cross-sectional view of a line corresponding to line B-B' of the device 200 of fig. 3.
Fig. 6-23 are schematic cross-sectional views of the major manufacturing steps of device 200.
Fig. 24 is a partial top view schematic diagram of an IGBT device 300 according to a second embodiment of the invention.
Fig. 25 is a schematic cross-sectional view of a line corresponding to line C-C' of the device 300 of fig. 24.
Fig. 26 is a schematic cross-sectional view of a line D-D' corresponding to the device 300 of fig. 24.
Fig. 27 is a partial top view schematic diagram of an IGBT device 400 according to a third embodiment of the invention.
Fig. 28 is a schematic cross-sectional view of a line corresponding to line E-E' of device 400 of fig. 27.
Fig. 29 is a schematic cross-sectional view of a line corresponding to line F-F' of device 400 in fig. 27.
Fig. 30 is a partial top view schematic diagram of an IGBT device 500 according to a fourth embodiment of the invention.
Fig. 31 is a schematic cross-sectional view of a line corresponding to line G-G' of the device 500 of fig. 30.
Detailed Description
It should be noted that the device design and fabrication schemes shown in this specification relate only to the structural parts associated with trench gate electrode connections, and that other structural parts and process steps required to achieve a complete device (e.g., the terminal voltage-withstanding structure of the device, etc.) are not described in this document. In addition, this documentCorresponding positional words such as "upper", "lower", "left", "right", "front", "rear", "vertical", "horizontal" and the like in the description are relative positions corresponding to the reference drawings, and are not limited to fixed directions in the detailed description. In the following description, the semiconductor substrate of the transistor is considered to be made of a silicon (Si) material. However, the substrate may be formed of any other material suitable for the fabrication of the device, such as germanium (Ge), silicon carbide (SiC), and the like. In the following description, the conductivity type of the semiconductor region is classified into p-type and n-type. A p-type conductive semiconductor region may be formed by doping the original semiconductor region with one or more impurities, which may be, but are not limited to: boron (B), aluminum (Al), gallium (Ga), etc.; an n-type conductive semiconductor region may also be formed by doping the original semiconductor region with one or more impurities, such as, but not limited to: phosphorus (P), arsenic (As), tellurium (Sb), selenium (Se), and protons (H) + ) Etc. In practice, the invention is not limited to n-type or p-type channel devices, i.e., the invention is equally applicable to p-type channel devices, as long as the n-type region and the p-type region described in this document are interchanged. In the following description, a trench type IGBT device will be used, but it should be noted that the present invention is also applicable to other semiconductor devices such as trench type MOSFET, and only p on the back of the device is needed at this time + The collector doping region is replaced with n + The drain doping region is formed.
The power semiconductor device of the present invention is specifically exemplified below.
Example 1
Fig. 3 isbase:Sub>A schematic partial top view of an IGBT device 200 according tobase:Sub>A first embodiment of the invention, and fig. 4 and 5 are schematic cross-sectional structures corresponding to the cut linesbase:Sub>A-base:Sub>A 'and B-B' of the device 200 in fig. 3, respectively. As shown in fig. 4 and 5, the device 200 has a collector metal layer (201) at the bottom of the device, and semiconductor regions above the collector metal layer (201) and including p from bottom to top + Collector doping region (202), n-type electric field stop layer (203) and n - -a type drift region (204); at the half partAn interlayer dielectric layer (211) is arranged on the conductor region, and the interlayer dielectric layer is generally made of materials such as silicon oxide or silicon nitride; an emitter electrode metal layer (213) and a gate electrode metal layer (214) which are formed by metal layers are respectively arranged at different areas above the interlayer dielectric layer (211), as shown in fig. 3; on the upper surface of the semiconductor region there are a series of parallel arranged trenches (205), the trenches (205) start under the gate electrode metal layer (214) and extend into the lower part of the emitter electrode metal layer (213), the part of the trenches (205) under the gate electrode metal layer (214) is called the start section of the trenches (205), the part of the trenches (205) under the emitter electrode metal layer (213) is called the extension section of the trenches (205), in particular the width of the start section of the trenches (205) is larger than the width of the extension section of the trenches (205), i.e. "y" marked in fig. 3 ">"x". Preferably, the width "y" of the starting section of the trench (205) is generally 1.2 to 1.8 μm and the length is generally 5 to 15 μm from the top view of the device; the width "x" of the trench (205) extension is typically 0.6-1.2 μm, and the length of the trench (205) extension is greater than the length of the emitter electrode metal layer (213) of the device 200 in the direction of extension of the trench (205). -filling the trench (205) with a gate conductive material (207), the gate conductive material (207) generally being composed of a heavily doped polysilicon material; a gate dielectric layer (206) is arranged between the gate conductive material (207) and the inner wall of the trench (205), the gate dielectric layer (206) is generally made of dielectric materials such as silicon oxide or silicon nitride, and the upper surface of the gate conductive material (207) is covered by an interlayer dielectric layer (211); in addition, a gate contact hole (216) is formed in the interlayer dielectric layer (211) above the initial section of the trench (205), the gate conductive material (207) in the trench (205) is connected with the gate electrode metal layer (214) above the trench through the gate contact hole (216), and the width of the gate contact hole (216) is smaller than that of the initial section of the trench (205). Preferably, the width of the gate contact hole (216) is 0.3-0.7 mu m, the width of the initial section of the groove (205) is 0.5 mu m or more than that of the gate contact hole (216), and the design can provide sufficient alignment deviation allowance for the contact hole photoetching process in the device manufacturing process, so that the difficulty of the contact hole photoetching process is reduced.
In addition, the groove is205 The initiation segment and the trench (205) extension segment may be formed in the same etch process during device fabrication without adding process steps. Considering the loading effect of trench etching, a larger width of the starting section of the trench (205) results in a relatively faster etching rate, such that the depth of the starting section of the trench (205) is greater than the depth of the extension section of the trench (205). Preferably, the depth of the extended section of the trench (205) is 4-6 μm, and the depth of the initial section of the trench (205) is generally 0.2-0.8 μm deeper than the extended section of the trench (205). It should be noted that in the device voltage-withstanding state, the electric field at the deep position of the trench tends to be relatively high, so that the initial section of the trench (205) tends to break down in advance, and in order to avoid the problem, the device structure of the present invention is further provided with a p-type buffer doped region (215) in the semiconductor region around the initial section of the trench (205), wherein the p-type buffer doped region (215) is located in n - Above the type drift region (204) and seen in cross section (as shown in fig. 5), the junction depth of the p-type buffer doped region (215) is greater than or equal to the depth of the starting section of the trench (205); the length of the p-type buffer doped region (215) is longer than the length of the initial section of the trench (205) as seen in a top view (as shown in fig. 3), and preferably, one side edge of the p-type buffer doped region (215) extends to the lower part of the emitter electrode metal layer (213) and is connected with the emitter electrode metal layer (213) through the emitter contact hole (212). In this way, the p-type buffer doped region (215) will be at a low potential, and by surrounding the starting section of the trench (205) with the p-type buffer doped region (215), the electric field near the starting section of the trench (205) can be effectively reduced, thereby avoiding adverse effects on the breakdown voltage of the device and maintaining the voltage-withstanding capability of the device.
In addition, as shown in fig. 4, a p-type body region (208) is also arranged between the extension sections of the adjacent grooves (205), and the p-type body region (208) is positioned at n - -over the type drift region (204), and the p-type body region (208) has a depth less than the depth of the extension of the trench (205); above the p-type body region (208) is provided with n + Emitter region (210) and p + A contact region (209), said n + An emitter region (210) is adjacent to one side wall of the extension of the trench (205), said n + Emitter region (210) and p + The contact region (209) passes through the interlayer dielectric layer(211) The emitter contact hole (212) of the semiconductor device is connected with the emitter electrode metal layer (213) above the emitter contact hole. The device structure near the extension of the trench (205) may be consistent with prior art trench-type power semiconductor devices.
In addition, the present invention also proposes the main manufacturing steps of the IGBT device 200 according to the first embodiment, and the following description will be given by selecting the cross-sectional structures corresponding to the tangents ofbase:Sub>A-base:Sub>A 'and B-B' in fig. 3. First, n is formed in a semiconductor substrate - -a type drift region (204), said n - The type drift region (204) may be formed by crystal epitaxy or by zone melting; next, as shown in FIGS. 6 and 7, at n - Forming a p-type buffer doped region (215) at a corresponding position on the surface of the type drift region (204) by means of photoetching and ion implantation, wherein the p-type buffer doped region (215) can be formed synchronously with a p-type field wire ring doped region (not shown in the document) commonly used for a terminal voltage-resistant region of a power device, so that no extra photoetching plate and process steps are added; next, as shown in fig. 8 and 9, etching the trench (205) on the surface of the semiconductor substrate, and implementing the width "y" of the trench (205) at the initial section thereof to be larger than the width "x" of the trench at the extension section thereof by using the photolithography pattern, wherein the depth "d2" of the trench (205) at the initial section thereof is also larger than the depth "d1" thereof at the extension section thereof due to the loading effect of the etching process; next, as shown in fig. 10 and 11, a gate dielectric layer (206) is formed on the inner wall of the trench (205) by oxidation and/or dielectric deposition, and then the trench (205) is filled with a gate conductive material (207); next, as shown in fig. 12 and 13, the gate conductive material (207) is etched back, so that the gate conductive material on the upper surface of the semiconductor region is completely removed, and only the gate conductive material (207) in the trench (205) is remained, wherein the etching of the gate conductive material (207) in this step does not require photolithography; next, as shown in fig. 14 and 15, a p-type body region (208), n, is formed by ion implantation and/or diffusion between the extension portions of adjacent trenches (205) + Emitter region (210) and p + A contact region (209); next, as shown in fig. 16 and 17, an interlayer dielectric layer (211) is deposited on the surfaces of the semiconductor region and the trench (205); next, as shown in FIGS. 18 and 19Photoetching the interlayer dielectric layer (211), forming an emitter contact hole (212) between extension sections of adjacent grooves (205), and forming a gate contact hole (216) above the initial section of the groove (205); next, as shown in fig. 20 and 21, a metal layer is deposited on the surface of the interlayer dielectric layer (211), and an emitter electrode metal layer (213) and a gate electrode metal layer (214) are formed by photolithography; finally, as shown in FIGS. 22 and 23, the back of the semiconductor region is thinned, and then at n - An n-type electric field cut-off layer (203) and a p-type electric field cut-off layer are formed under the drift region (204) by ion implantation and/or diffusion + And (3) a shaped collector doping region (202), and then depositing a metal layer on the back of the device to form a collector electrode (201), thereby completing the manufacture of the device 200.
It should be noted that, with respect to the trench semiconductor device 100 of the prior art, the manufacturing of the power semiconductor device 200 of the present invention does not require photolithography of the gate conductive material (207), thereby reducing the number of photolithography steps and process steps and reducing the manufacturing cost of the device.
Example 2
Fig. 24 is a schematic partial top view of an IGBT device 300 according to a second embodiment of the invention, and fig. 25 and 26 are schematic cross-sectional structures corresponding to C-C 'and D-D' tangents of the device 300 in fig. 24, respectively. With respect to the device 200 described hereinabove, the device 300 also has the following features: the semiconductor device comprises a plurality of pseudo grooves (218) which are arranged in parallel with the grooves (205), wherein the initial section and the extension section of the pseudo grooves (218) are positioned below the emitter electrode metal layer (213), and the width of the initial section of the pseudo grooves (218) is larger than that of the extension section of the pseudo grooves. The dummy trench (218) is filled with a dummy gate conductive material (227), a dummy gate contact hole (217) is formed above the initial section of the dummy trench (218), the dummy gate conductive material (227) is connected with the emitter electrode metal layer (213) through the dummy gate contact hole (217), and the width of the dummy gate contact hole (217) is smaller than that of the initial section of the dummy trench (218). The adoption of the pseudo groove (218) design can reduce the density of the grid groove, reduce the parasitic capacitance of the grid of the device and accelerate the switching speed of the device. It should be noted that the dummy trenches (218) may be etched in the same step of lithography as the trenches (205), thus eliminating the need for additional lithography and process steps. Correspondingly, the width of the starting section and the extending section of the pseudo groove (218) and the width of the starting section and the extending section of the groove (205) can be respectively corresponding to be equal; the depths of the start section and the extension section of the dummy trench (218) and the depths of the start section and the extension section of the trench (205) may also be respectively and correspondingly equal. Similarly, to avoid affecting the breakdown voltage of the device due to the deeper depth of the beginning segment of the dummy trench (218), the beginning segment of the dummy trench (218) is surrounded by the p-type buffer doped region (215), and the junction depth of the p-type buffer doped region (215) is greater than or equal to the depth of the beginning segment of the dummy trench (218).
Example 3
Fig. 27 is a schematic partial top view of an IGBT device 400 according to a third embodiment of the invention, and fig. 28 and 29 are schematic cross-sectional structures corresponding to E-E 'and F-F' tangents of the device 400 in fig. 27, respectively. With respect to the device 300 described above, the device 400 also has the following features: more than one dummy trench (218) is arranged between adjacent trenches (205), and the surface of the semiconductor region between the adjacent dummy trenches (218) is not provided with an emitter contact hole (212). A p-type body region (208) may be provided between the extension segments of adjacent dummy trenches (218), as shown in fig. 28. Because the emitter contact holes (212) are not arranged between the adjacent pseudo grooves (218), the semiconductor region of the region can be in an electric floating state, so that more current carriers can be stored in the IGBT conducting state, and the conducting voltage drop of the IGBT is reduced.
Example 4
Fig. 30 is a schematic partial top view of an IGBT device 500 according to a fourth embodiment of the invention, and fig. 31 is a schematic cross-sectional structure corresponding to a G-G' cut line of the device 500 in fig. 30. With respect to the device 400 described hereinabove, the device 500 also has the following features: as shown in fig. 30, the initial sections of the grooves and the pseudo grooves are respectively vertical to the extension sections thereof, the initial sections of the adjacent two grooves are connected with each other to form a continuous "U" shaped groove (225), and the initial sections of the adjacent two pseudo grooves are connected with each other to form a continuous "U" shaped pseudo groove (219); in addition, the "U" shaped trench (225) in FIG. 30 may also be disposed symmetrically up and down to the pattern shown in FIG. 30 on the other side (not shown in FIG. 30) below FIG. 30, thereby forming a closed "O" shaped trench; similarly, the "U" -shaped dummy trench 219 may be disposed symmetrically up and down as an "O" -shaped dummy trench. Preferably, a p-type floating doped region (220) is arranged between two adjacent extension sections of the pseudo groove (219), and the junction depth of the p-type floating doped region (220) is larger than that of the p-type body region (208). The design can reduce the groove density of the device on the premise of maintaining the breakdown voltage of the device, is beneficial to improving the carrier storage concentration of the IGBT in the on state, and optimizes the switching and on loss of the IGBT.
Claims (14)
1. A trench power semiconductor device includes
A collector metal layer at the bottom of the device;
the semiconductor region is positioned above the collector metal layer and comprises a second conduction type collector doping region, a first conduction type electric field stop layer and a first conduction type drift region from bottom to top; more than one parallel arranged groove extending into the semiconductor region from the upper surface of the semiconductor region is also arranged in the semiconductor region, the groove is filled with a grid conductive material, and a grid dielectric layer is arranged between the grid conductive material and the inner wall of the groove;
an interlayer dielectric layer located on the semiconductor region;
the emitter electrode metal layer and the gate electrode metal layer are positioned on the interlayer dielectric layer, wherein a groove positioned below the gate electrode metal layer forms a groove starting section, and a groove positioned below the emitter electrode metal layer forms a groove extending section;
it is characterized in that the method comprises the steps of,
a gate contact hole is formed in the interlayer dielectric layer above the groove starting section, a gate conductive material in the groove is connected with the gate electrode metal layer above the groove through the gate contact hole, the width of the gate contact hole is smaller than that of the groove starting section, and the width of the groove starting section is larger than that of the groove extending section;
the periphery of the initial section of the groove is provided with a second conduction type buffer doping area, and the junction depth of the second conduction type buffer doping area is larger than or equal to the depth of the initial section of the groove;
and one side edge of the second conductive type buffer doped region extends to the lower part of the emitter electrode metal layer and is connected with the emitter electrode metal layer through an emitter contact hole in the interlayer dielectric layer.
2. The trench power semiconductor device of claim 1 wherein the trench initiation section has a width of 1.2 to 1.8 μm and the trench extension section has a width of 0.6 to 1.2 μm.
3. The trench power semiconductor device of claim 1 wherein said collector doping region of the second conductivity type is replaced with a drain doping region of the first conductivity type.
4. A trench power semiconductor device as claimed in any one of claims 1 to 3 wherein more than one dummy trench is provided in said semiconductor region below said emitter electrode metal layer, said dummy trench being connected to said emitter electrode metal layer by a dummy gate contact hole provided above a start section of said dummy trench.
5. The trench power semiconductor device of claim 4 wherein the width of the start segment of the dummy trench is greater than the width of the extension segment thereof.
6. The trench power semiconductor device of claim 5 wherein a buffer doped region of the second conductivity type is disposed around the beginning segment of the dummy trench and the junction depth of the buffer doped region of the second conductivity type is greater than or equal to the depth of the beginning segment of the dummy trench.
7. The trench power semiconductor device of claim 4 wherein the semiconductor region surfaces between adjacent dummy trenches are not provided with emitter contact holes.
8. The trench power semiconductor device of claim 4 wherein the starting segments of adjacent dummy trenches are connected to form a continuous "U" shaped dummy trench.
9. The trench power semiconductor device of claim 8 wherein two symmetrically disposed "U" shaped dummy trenches are connected at an extension to form a closed "O" shaped dummy trench.
10. The trench power semiconductor device of claim 9 wherein an electrically floating doped region of the second conductivity type is disposed between two adjacent dummy trench extensions.
11. The trench power semiconductor device of claim 1 wherein the starting segments of adjacent trenches are connected to form a continuous "U" shaped trench.
12. The trench power semiconductor device of claim 11 wherein two symmetrically disposed "U" shaped trenches are joined at an extension to form a closed "O" shaped trench.
13. A method of manufacturing a trench power semiconductor device, the method comprising:
(1) Forming a first conductivity type drift region in a semiconductor substrate;
(2) Forming a second conduction type buffer doping region on the corresponding position of the surface of the first conduction type drift region in a photoetching and ion implantation mode, wherein the second conduction type buffer doping region is formed synchronously with a second conduction type field wire ring doping region commonly used for a terminal voltage-withstanding region of the power device;
(3) Etching a groove on the surface of the semiconductor substrate, and realizing that the width 'y' of the groove at the initial section is larger than the width 'x' of the groove at the extension section by using a photoetching pattern, wherein the depth'd 2' of the groove at the initial section is also larger than the depth'd 1' of the groove at the extension section;
(4) Forming a gate dielectric layer on the inner wall of the trench, and filling the trench with a gate conductive material;
(5) Carrying out back etching on the gate conductive material, completely removing the gate conductive material on the upper surface of the semiconductor region, and only keeping the gate conductive material in the groove, wherein the process does not need a photoetching plate;
(6) Forming a second conductive type body region, a first conductive type emitter region and a second conductive type contact region between the extension sections of the adjacent trenches;
(7) Depositing an interlayer dielectric layer on the surfaces of the semiconductor region and the groove;
(8) Photoetching an interlayer dielectric layer, forming an emitter contact hole between extension sections of adjacent grooves, and forming a gate contact hole above an initial section of each groove;
(9) Depositing a metal layer on the surface of the interlayer dielectric layer, and forming an emitter electrode metal layer and a gate electrode metal layer by photoetching;
(10) And thinning the back of the semiconductor region, forming a first conductive type electric field cut-off layer and a second conductive type collector doping region under the first conductive type drift region in an ion implantation and/or diffusion mode, and then depositing a metal layer on the back of the device to form a collector metal layer.
14. The method of manufacturing a trench type power semiconductor device according to claim 13, wherein dummy trenches are etched simultaneously in step (3).
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| JP2013251468A (en) * | 2012-06-01 | 2013-12-12 | Fuji Electric Co Ltd | Semiconductor device and method for controlling the same |
| CN103985746A (en) * | 2014-06-05 | 2014-08-13 | 无锡新洁能股份有限公司 | Groove type IGBT (Insulated Gate Bipolar Transistor) device and manufacturing method thereof |
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| CN102187465A (en) * | 2008-10-14 | 2011-09-14 | 三菱电机株式会社 | Power device |
| JP2013251468A (en) * | 2012-06-01 | 2013-12-12 | Fuji Electric Co Ltd | Semiconductor device and method for controlling the same |
| CN103985746A (en) * | 2014-06-05 | 2014-08-13 | 无锡新洁能股份有限公司 | Groove type IGBT (Insulated Gate Bipolar Transistor) device and manufacturing method thereof |
| WO2018105749A1 (en) * | 2016-12-09 | 2018-06-14 | 国立大学法人九州工業大学 | Insulated gate bipolar transistor device, method for producing semiconductor device, and method for producing insulated gate bipolar transistor device |
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