JP4696327B2 - Insulated gate type semiconductor device - Google Patents

Insulated gate type semiconductor device Download PDF

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JP4696327B2
JP4696327B2 JP15731299A JP15731299A JP4696327B2 JP 4696327 B2 JP4696327 B2 JP 4696327B2 JP 15731299 A JP15731299 A JP 15731299A JP 15731299 A JP15731299 A JP 15731299A JP 4696327 B2 JP4696327 B2 JP 4696327B2
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region
base region
conductivity type
emitter
type base
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JP2000349284A (en
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年生 村田
佐智子 河路
雅康 石子
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株式会社豊田中央研究所
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Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor element that controls a current flowing between other electrodes by applying a voltage to a gate electrode. In particular, the present invention relates to a structure of an insulated gate semiconductor device aiming at high latch-up resistance and low on-voltage.
[0002]
[Prior art]
An insulated gate transistor changes the electrical conductivity of a semiconductor by the electric field effect by a gate voltage, and controls the electric current which flows between the other area | regions provided in the both ends of the gate area | region. For example, an IGBT (Insulated Gate Bipolar Transistor) is known for power. The IGBT controls a current of several tens of amperes with a control voltage of several tens of volts. However, when a large current is applied, a parasitic transistor described later operates due to the internal structure, and a latch-up state is established. For this reason, high latch-up resistance and low on-voltage have been conventionally required. For example, there is a vertical IGBT as a semiconductor element considering high latch tolerance and low on-voltage. Further, there is a semiconductor device (Japanese Patent Laid-Open No. 1-198076) having a substantially equivalent structure and characterized by a gate electrode having a trench structure.
[0003]
FIG. 14 shows the structure of a conventional vertical IGBT. The equivalent circuit is the same as FIG. Vertical IGBT is p + The n-type impurity doped silicon substrate is used as the collector region 70, and is formed on the collector region 70 successively by so-called planar technology such as epitaxial growth technology, lithography technology, ion implantation technology, diffusion technology, etching technology, etc. + Buffer area 71, n - Type base region 72, p-type base region 73, n + Emitter region 74, p + The gate electrode 75, the emitter electrode 77, and the collector electrode 78 are formed by a shaped emitter region 80, an insulating gate film 76, a CVD (Chemical Vapor Deposition), and the like. The n-type buffer region 71 may not be formed.
[0004]
Referring to FIGS. 14 and 3, in this device, n + Emitter region 74, p-type base region 73, n - The field effect transistor (Tr1) is formed in the base region 72, and the p-type base region 73, n - Shape base region 72, p + In the collector region 70, a bipolar transistor (Tr2) is formed.
The structure is such that the current flowing in Tr2 is controlled by controlling Tr1, but n + Emitter region 74, p-type base region 73, n - A bipolar transistor (Tr3) formed with the shaped base region 72 is also parasitic.
[0005]
When the emitter electrode 77 is grounded, a positive voltage of, for example, several hundred volts is applied to the collector electrode 78, and a positive voltage of several volts to several tens of volts is applied to the gate electrode 75, the field effect transistor (Tr1) shown in FIG. ON, n - Electrons flow into the shape base region 72. As a result, p + N from the collector region - Holes are injected into the shaped base region 72, and the high resistivity n - A conductivity modulation effect that increases the electron concentration and hole concentration of the shaped base region 72 equally occurs.
The IGBT is an element that can reduce the on-voltage by the conductivity modulation effect. The switching speed is one digit faster than the power transistor, and the current capacity is one to two orders of magnitude greater than that of the MOS transistor. And since the switching speed is high, the capacity | capacitance of the electric current is increasingly demanded in recent years.
[0006]
[Problems to be solved by the invention]
However, as described above, the IGBT has n + Emitter region 74, p-type base region 73, n - There is an npn-type parasitic transistor Tr3 composed of the base region 72. When a large current is passed through Tr2, that is, n - Shape base region 72 to p + When a large current is passed through the emitter region 80, p + Since the emitter region 80 has the resistance Rp, a potential difference of ΔV (= I · Rp) is generated between the emitter electrode 77 and the p-type base region 73. When this ΔV exceeds a threshold voltage (about 0.7V), Tr3 is turned on. That is, there is a problem that the parasitic thyristor composed of Tr2 and Tr3 shown in FIG. 3 is in an ON state and a current always flows, and this IGBT cannot be controlled by the gate voltage (latch-up state).
[0007]
Therefore, in the conventional example, the p + emitter region 80 having a higher impurity concentration is provided to lower the resistance value Rp, or in some cases p + Instead of removing the emitter region 80, an electrode having a trench structure is used instead (for example, Japanese Patent Laid-Open No. 1-198076), and an electrode is directly joined to the p-type base region 73 to avoid latch-up.
However, as in the conventional example, the p-type base region 73 and n + Since the structure is such that a hole current is easily injected into the pn junction surface by the emitter region 74, if a larger current flows, the potential of the p-type base region 73 rises and the parasitic thyristor is turned on as before, and further High latch-up tolerance has not been realized.
[0008]
If the gap between the gate electrodes 75 is narrowed, p + The holes injected from the collector region 70 are n - Accumulation in the shape base region 72 improves the conductivity modulation effect, and as a result, the on-voltage can be reduced. However, n + Emitter region 74, p-type base region 73, p + In the conventional configuration in which the emitter region 80 is formed between the gate electrodes, there is a limit to narrowing the gap. That is, there is a limit to lowering the on-voltage.
[0009]
The present invention has been made to solve the above-described problems, and an object of the present invention is to provide an n-type semiconductor device, particularly an IGBT, n + Depending on the positional relationship between the emitter region and the gate electrode and the p-type base region, and n + It is an object to provide an insulated gate semiconductor device excellent in high latch-up resistance, low on-voltage and high withstand voltage by suppressing the flow of hole current by the junction shape of the emitter region and the p-type base region.
[0010]
[Means for Solving the Problems]
In order to achieve this object, the insulated gate semiconductor device according to claim 1 is an insulated gate semiconductor device, wherein an electrically insulating film is formed on the side surfaces of the first conduction type carrier and the second conduction type carrier. The gate electrode is provided with an emitter electrode, a first conductivity type emitter region, Target Second conductivity type on insulating film base Region, first conductivity type base The first conduction type carriers flow in the region path, and the current flowing from the collector electrode to the second conduction type collector region, the first conduction type base region, the second conduction type base region, and the emitter electrode is controlled by the gate voltage. In an insulated gate semiconductor device, the gate electrode with an electrically insulating film has an upper surface bonded to the lower surface of the second conductivity type base region, and is perpendicular to the main surface of the collector electrode from the collector electrode toward the emitter electrode. Flowing into Current path Is formed to extend from the peripheral portion of the insulated gate semiconductor element with a certain thickness in the horizontal direction so as to be narrowed at the center of the plane parallel to the main surface, and the emitter electrode is narrowed Current path The collector electrode is formed on the entire lower surface of the second conductivity type collector region, and is connected to the entire upper surface of the first conductivity type emitter region and the second conductivity type base region. At the junction surface with the emitter electrode, the second conductivity type base region is: That The first conductivity type emitter region is on the electrical insulating film of the gate electrode facing the emitter electrode, and is inverted on the electrical insulating film. At the position where the layer is formed, the emitter electrode and the second conductivity type base region are joined to each other, and the thickness of the first conductivity type emitter region depends on the level difference between the central portion of the second conductivity type base region. It is characterized by being thinner than the thickness at.
[0011]
[0012]
The insulated gate semiconductor device according to claim 2, wherein the second conductivity type of the second conductivity type carrier injected from the collector region near the junction of the first conductivity type base region with the second conductivity type base region. To the base area Current path An electrically insulating region is formed so as to narrow the width.
[0013]
[Operation and effect of the invention]
The insulated gate semiconductor device according to claim 1, wherein the gate electrode with the electrically insulating film has a predetermined flow path so as to narrow a flow path of the first conduction type carrier and the second conduction type carrier in a region close to the emitter electrode. The shape is formed to a predetermined depth.
When the second conductivity type carriers injected from the second conductivity type collector region into the first conductivity type base region diffuse into the second conductivity type base region, it becomes difficult to reach the first conductivity type emitter region, and the emitter The first conductivity type emitter region is formed on the electrical insulating film of the gate electrode facing the emitter electrode and joined to the emitter electrode and the second conductivity type base region so that the electrode can be easily reached.
The thickness of the first conductivity type emitter region in the current direction is set to be equal to or less than the thickness of the second conductivity type base region.
[0014]
When a voltage is applied to the gate electrode, first, a field effect transistor composed of a first conduction type emitter region, a second conduction type base region, and a first conduction type base region is turned on. One conductivity type carrier is injected into the second conductivity type base region. Along with this, the second conductivity type carriers are injected from the second conductivity type collector region into the first conductivity type base region, and diffused into the first conductivity type base region. The diffused second conductivity type carrier passes through the channel narrowed by the gate electrode with the electrical insulating film, and the position and direction of diffusion are limited.
[0015]
On the other hand, the first conductivity type emitter region, the second conductivity type base region, and the first conductivity type base region constitute a parasitic transistor. The first-conductivity-type emitter region that also serves as the emitter of this parasitic transistor is formed at a location away from this diffusion flow, that is, on the electrically insulating film of the gate electrode facing the emitter electrode side.
Therefore, the minority carriers subjected to this restriction hardly flow into the first conduction type emitter region, and the majority flows directly into the emitter electrode. That is, the potential of the second conductivity type base region that is the base of the parasitic transistor does not rise. That is, the parasitic transistor does not turn on within a predetermined maximum current value. Therefore, high latch-up is realized.
[0016]
Further, at this time, the thickness of the first conductivity type emitter region in the current direction is preferably set to be equal to or less than the thickness of the second conductivity type base region. If the thickness of the first conduction type emitter region in the current direction is reduced, the resistance component is also reduced, and the potential increase in the second conduction type base region due to the first conduction type carrier is suppressed. Therefore, a larger current can be achieved. In other words, the on-voltage can be further reduced.
[0017]
In addition, since the flow path is narrowed by the gate electrode with the electrical insulating film, the density of the second conductive carriers in the flow path in the first conductive type base region is increased. The conductivity modulation effect in the region close to the emitter electrode is also increased, and the on-voltage can be substantially reduced.
[0018]
In addition, the second conductivity type base region is formed in a step shape at the end thereof, and is joined with the same thickness as the first conductivity type emitter region.
Most of the second conductivity type carriers diffused from the first conductivity type base region to the second conductivity type base region go to the emitter electrode, but a part goes to the first conductivity type emitter region.
At this time, the thickness of the second conductivity type base region is not uniform and is formed in a stepped shape at the end thereof. That is, the emitter electrode is formed so as to narrow the path of the second conductivity type carrier. Therefore, the carrier toward the first conductivity type emitter region is absorbed by the emitter electrode on the way. In other words, the resistance between the second conductivity type base region and the first conductivity type emitter region is reduced. That is, the potential increase of the second conductivity type base region due to the second conductivity type carrier is suppressed. Therefore, the latch-up resistance can be improved for the same reason as described above, and the current can be increased.
In addition, since the second conductivity type base region can be thickened, a high breakdown voltage can be achieved. As a result, an insulated gate semiconductor device that achieves a high breakdown voltage and a high latch-up resistance is obtained.
[0019]
The insulated gate semiconductor device according to claim 2, wherein the second conductivity type carrier injected from the collector region is in the second conductivity type near the junction of the first conductivity type base region with the second conductivity type base region. To the base area Current path An electrically insulating region that narrows the width is formed.
Since the electrically insulating region is formed in the channel of the second conductivity type carrier of the first conductivity type base region narrowed by the gate electrode, the second conductivity type carrier which is a minority carrier injected from the collector region Is accumulated in the high resistance base region, which is the first conductivity type base region, and its concentration is improved. In the high-resistance base region close to the emitter region, the minority carrier concentration is improved. As a result, the conductivity modulation is increased, and as a result, the on-voltage is lowered.
Therefore, as in the insulated gate semiconductor device according to the first aspect, the advancement of the latch-up resistance can be maintained and a further lower on-voltage can be realized.
In the above description, if the first conductivity type is n-type, the first conductivity type carrier is an electron, the second conductivity type is a p-type, and the second conductivity type carrier is a hole. Conversely, if the first conductivity type is p-type, the first conductivity type carrier is a hole, the second conductivity type is an n-type, and the second conductivity type carrier is an electron.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described based on specific examples. In addition, this invention is not limited to the following Example.
First embodiment
In the following description, the first conductivity type is n-type, the first conductivity type carrier is electron, the second conductivity type is p-type, and the second conductivity type carrier is hole.
FIG. 1 shows a first embodiment of an IGBT according to the present invention. The figure is a sectional view showing a cell structure. The insulated gate semiconductor device of this example is p + N on the collector region 10 + Shape buffer area 11 + N which is a high resistance region on the buffer region 11 - A base region 12 is provided. The cell pitch w is about 4 μm.
[0021]
Furthermore, n - Both upper side surfaces of the base region 12 have gate electrodes 13a and 13b with electrical insulating films 14a and 14b, and both electrodes n so as to narrow the carrier flow path. - It is formed in the base region 12 with an interelectrode distance L.
Further, a part of the electrical insulating films 14a and 14b and n - The p-type base region 16 is in close contact with the p-type base region 12, and the n + -type emitter regions 15a and 15b are provided on the electrical insulating films 14a and 14b on both sides thereof. At this time, the end of the p-type base region 16 is joined to the n + -type emitter regions 15a and 15b with a step.
Furthermore, the n + Emitter electrodes 18 are formed on the p-type emitter regions 15a and 15b and the adjacent p-type base region 16, respectively. + A collector electrode 19 is formed in the collector region 10. The insulated gate semiconductor device of this example has such a structure.
[0022]
FIG. 2 shows a method for manufacturing the insulated gate semiconductor device. The above structure is manufactured by a planar technique centered on a lithography technique and a solid phase epitaxial technique. In this embodiment, the process is divided into the following four steps (a) to (d). FIG. 2 shows the main part of the manufacturing process, and the parts not shown are the same as those in FIG.
In step (a), first, p shown in FIG. + P of silicon substrate + On the collector region 10, for example, n having a thickness of 15 μm + Epitaxial layer 11 is formed. Then this n + On the epitaxial layer 11, for example, n having a thickness of 60 μm - Forming an epitaxial layer, n - A shaped base region 12 is formed (FIG. 2). N at this time - The impurity concentration of the shaped base region 12 is 1 × 10 14 / Cm Three It is.
Next, heat treatment is performed in this state. As a result, n - For example, a silicon oxide film having a thickness of 100 nm is formed on the surface of the shaped base region 12. The silicon oxide film becomes a part of an electrical insulating film 14b described later.
Thereafter, phosphorous-doped polycrystalline Si having a thickness of, for example, 200 nm and a silicon oxide film having a thickness of 100 nm are sequentially deposited, and the central portion is deleted by a patterning technique and an etching technique. As a result, gate electrodes 13a and 13b whose upper and lower sides are sandwiched between the electrical insulating films 14a and 14b are formed (FIG. 2A).
[0023]
Next, in step (b), a silicon oxide film or the like is deposited on the substrate in a thickness of 50 to 200 nm. Next, a silicon oxide film is formed on the side walls of the gate electrodes 13a and 13b by RIE (Reactive lon Etching) to form a side wall 14c as an electrical insulating film (FIG. 2 (b)).
Next, the process proceeds to step (c). The thicknesses of the electrical insulating films 14a, 14b, and 14c are all about 0.1 μm.
[0024]
In the step (c), thereafter, for example, amorphous Si having a thickness of 1 μm is formed by CVD or the like, and the single crystal Si layer 16A is formed by SPE (Solid Phase Epitaxy) technique or the like. After that, the single crystal Si layer 16A is formed with a thickness of 0. Reduce the thickness to 5 μm (Figure 2 (c)). Next, the process proceeds to step (d).
[0025]
In the step (d), for example, boron is ion-implanted in the central portion by a resist pattern technique and an ion implantation technique to form the p base region 16. Further, for example, phosphorus is ion-implanted into both end portions to make n + Emitter regions 15a and 15b are formed. Then, a desired impurity profile is obtained by thermal diffusion or the like.
After that, n by the above RIE technology etc. + The emitter regions 15a and 15b are etched to a predetermined thickness, for example, about 0.3 μm. N at this time + The impurity surface concentration of the emitter regions 15a and 15b is 1 × 10 20 / Cm Three It is. In this way, the basic structure of the insulated gate semiconductor device is produced. (Figure 2 (d)).
Note that the etching in the step (d) is performed by using the p-type base region 16 and n. + You may carry out across the boundary of the shape | mold emitter area | regions 15a and 15b. Although details will be described later, with such a structure, a high breakdown voltage and a high latch-up resistance can be realized.
This etching is performed in the p base region 16 and n. + It may be performed before the formation of the emitter regions 15a and 15b. The above is the method for manufacturing the insulated gate semiconductor device of this example.
[0026]
Next, the operation of the insulated gate semiconductor device will be described with reference to FIGS. FIG. 3 is an equivalent circuit of the insulated gate semiconductor device having the above configuration. This element is designed with a withstand voltage of 600V and a cut-off voltage of 4V. The emitter electrode 18 is grounded, a positive voltage of several hundred volts, for example, is applied to the collector electrode 19, and a positive voltage of several volts to several tens of volts, which is sufficiently higher than the cutoff voltage, is applied to the gate electrodes 13a and 13b. At this time, first, inversion layers 17a and 17b are formed on the boundary surface between the p-type base region 16 and the electrical insulating films 14a and 14b by the electric field effect (FIG. 1). The electrons pass through the inversion layers 17a and 17b, respectively. + N from emitter regions 15a, 15b - It flows into the shaped base region 12 (that is, Tr1 in the equivalent circuit shown in FIG. 3 is turned on) and diffuses toward the collector region 10 by a strong electric field.
[0027]
On the other hand, when the diffusion of electrons proceeds sufficiently, n - The potential of the shape base region 12 is lowered. n - When the potential of the shaped base region 12 decreases, the pn junction is biased in the forward direction. + Holes from the collector region 10 of the shape - Implanted into the shaped base region 12. The injected holes are n - The shaped base region 12 is diffused in the direction of the emitter electrode 18 and collected in the carrier accumulation region 12A narrowed by the gate electrodes 13a and 13b. As a result, the carrier concentration increases in that region, and n is reduced by conductivity modulation. - The resistance value of the shape base region 12 is lowered. As a result, a large current flows into the emitter regions 15a and 15b, and n - The holes in the base region 12 also flow into the p-type base region 16 as a large current. That is, Tr2 is turned on.
[0028]
At this time, a resistance Rp in the direction of the emitter electrode 18 usually exists in the p-type base region 16. The carrier passage route is directly connected to the emitter electrode 18 and n + There are two routes through the emitter regions 15a and 15b. That is, the resistance Rp is a combined resistance of the resistance values of the two paths.
Thereby, when a large current flows, the potential of the p-type base region 16 increases, and n + Emitter regions 15a and 15b, p-type base region 16, and n - The parasitic Tr3 composed of the shape base region 12 is turned on. That is, it becomes a latch-up state in which current cannot flow from Tr1 and current continues to flow.
[0029]
In order not to generate this potential difference while securing a large current, it is necessary to make this Rp as small as possible. Therefore, in the present invention, in order to reduce the resistance value Rp as much as possible, the junction area between the p-type base region 16 and the emitter electrode 18 is set to be three times or more that of the conventional vertical gate structure. Since the resistance value is inversely proportional to the area, Rp is reduced compared to the prior art, and latch-up is less likely to occur. That is, the latch-up resistance is improved.
[0030]
In addition, the thickness of the p-type base region 16 is reduced to the breakdown voltage limit (about 0.5 μm). Since the resistance value is proportional to the resistance length, if the thickness of the p-type base region 16 is reduced to the withstand voltage limit, Rp is reduced as compared with the prior art.
N + The emitter regions 15a and 15b are provided at both ends on the electrical insulating films 14a and 14b so as to be away from the carrier flow path. Part of the hall is n + The emitter regions 15a and 15b flow into the emitter regions 15a and 15b, and the thickness is 0.3 μm, which is close to the processing limit. Therefore, the resistance component thereby is reduced to the limit. Therefore, high breakdown voltage performance can be maintained, and the latch-up resistance can be further improved.
[0031]
Further, the p-type base region 16 has a step structure at its end, and has a thickness of 0.3 μm and n + It is joined to the emitter regions 15a and 15b. Therefore, n + Part of the holes toward the emitter regions 15a and 15b are absorbed by this stepped portion. That is, the potential increase in the p-type base region 16 is suppressed. That is, this structure also improves the latch-up resistance.
[0032]
As a result, the collector current density is 200 A / cm. 2 With a fall time of 300 nsec, the latch-up resistance could be improved by 10% or more compared to the conventional case.
In the above example, the p-type base region 16 is stepped by RIE. + Although bonded to the shaped emitter regions 15a and 15b, the bonded portion may be tapered as shown in FIG. This tapered shape can be formed by LOCOS oxidation and removal of the oxide film. In this case, there is an effect that defective filling of the emitter electrode 18 is reduced.
[0033]
Further, the configuration of the insulated gate semiconductor element in this embodiment can further reduce the on-voltage. It is n above + This is because the interelectrode distance L (carrier accumulation region 12A) can be reduced to the processing limit along with the configuration of the shape emitter regions 15a and 15b.
When the carrier accumulation region 12A is narrowed, holes are sufficiently accumulated. That is, the conductivity modulation is more sufficiently performed, and the on-voltage of the element is greatly reduced. FIG. 5 shows the relationship between the interelectrode distance L and the on-voltage. The horizontal axis is the interelectrode distance L, and the vertical axis is the ON voltage.
As can be seen from FIG. 5, when the interelectrode distance L is about 0.2 μm, the on-state voltage is 1.15V. As a result, the on-voltage was reduced by nearly 20% compared to the prior art.
Therefore, if an insulated gate semiconductor device is configured as described above, an excellent semiconductor device that can simultaneously achieve a high breakdown voltage, a high latch-up resistance, and a low on-voltage.
[0034]
Second embodiment
FIG. 6 shows a second embodiment of the insulated gate semiconductor device of the present invention. The figure is a structural sectional view. The feature of this embodiment is n narrowed by the plurality of gate electrodes 13a and 13b of the first embodiment. - That is, the carrier channel is narrowed by burying an electrical insulator 20 in the carrier channel 12A of the shaped base region 12. With this structure, p + Since the holes diffused from the collector region 10 are accumulated in the further narrowed flow path, the conductivity modulation effect is further enhanced. Therefore, the on-voltage can be reduced as compared with the first embodiment. In this case also, the p-type base region 16 and n + The junction with the shaped emitter regions 15a and 15b may be tapered. Regardless of the joint shape, if the electrical insulator 20 is embedded in the carrier flow path, the on-voltage can be reduced.
[0035]
Third embodiment
FIG. 7 shows a third embodiment of the insulated gate semiconductor device of the present invention. The figure is a structural sectional view. In this embodiment, the plurality of gate electrodes 13a and 13b of the first embodiment are formed in a wedge shape as shown in the figure, and the emitter regions 15a and 15b are formed at both ends on the electrical insulating films 14a and 14b, respectively. Is a feature. Even in such a configuration, the emitter regions 15a and 15b are located at locations away from the hole flow path, so that Rp can be reduced. Moreover, since the p base region can be set thick, a high breakdown voltage can be achieved as well as a high latch-up resistance.
Further, since holes of minority carriers are accumulated in the narrowed carrier accumulation region 12A as in the first embodiment, the conductivity modulation effect is enhanced and the on-voltage can be reduced.
Such a configuration is effective when a particularly high breakdown voltage is required for the insulated gate semiconductor device.
[0036]
Fourth embodiment
FIG. 8 shows a fourth embodiment of the insulated gate semiconductor device of the present invention. The figure is a structural sectional view. As shown in the figure, the feature of this embodiment is that the p-type base region 16 of the first embodiment is expanded to the carrier storage region 12A narrowed by the gate electrodes 13a and 13b, and the electric insulating film 14a on the flow path side is activated during operation. 14b, inversion layers 17a and 17b are formed. N + Similarly, the emitter regions 15a and 15b are formed on the electrical insulating films 14a and 14b on the emitter electrode 18 side.
Even in such a configuration, the n of the p base region 16 is increased. + Since the thickness of the portion in contact with the emitter regions 15a and 15b can be reduced to the processing limit, Rp can be reduced. Therefore, high latch-up withstand capability can be obtained similarly.
Similarly to the first embodiment, holes of minority carriers are accumulated in the narrowed carrier accumulation region 12A. Therefore, the ON voltage reduction effect is equivalent to that of the first embodiment.
[0037]
Example 5
FIG. 9 shows a fifth embodiment of the insulated gate semiconductor device of the present invention. The figure is a structural sectional view. As shown in the figure, the feature of this embodiment is n of the first embodiment. + Remove buffer area 11, p + N instead of the collector region 10 + A drain region 50 is formed and n - The shape base region 12 is n - The drain region 51 is formed, the emitter electrode 18 is a source electrode 180, the collector electrode 19 is a drain electrode 190, and the entire device is a field effect transistor (MOSFET).
[0038]
In MOSFETs, avalanche breakdown that occurs with the operation of a parasitic bipolar transistor is a major problem in driving an inductance load, and it is very important to improve resistance to this. As a technique for improving the avalanche resistance, n + Source regions 55a and 55b, p-type base region 56 and n - A method for making it difficult to turn on a parasitic bipolar npn transistor constituted by the drain region 51 is raised.
In the MOSFET of the present embodiment, since the resistance Rp of the p-type base region 56 can be made very small as in the first embodiment, the parasitic bipolar npn transistor is less likely to be turned on than in the prior art, and element breakdown is prevented. Can do.
Therefore, a higher avalanche resistance and a lower on-voltage can be realized as compared with the conventional MOSFET. Similarly, the embodiments shown in FIGS. 6, 7, and 8 may be MOSFETs having a source, gate, and channel structure.
In this case as well, the p-type base region 56 has a tapered shape at its end, and n + The emitter regions 55a and 55b may be joined. Regardless of the junction shape, a high avalanche resistance and a low on-voltage can be realized.
[0039]
Modified example
The present invention can be modified in various ways. For example, in the first embodiment, p + N above the collector region 10 + Although the buffer region 11 is provided, the present configuration works equally well for an insulated gate semiconductor device as shown in FIG. 10 by removing this, and a higher breakdown voltage, a higher latch-up volume, and a lower on-voltage. Can be realized. n + The same effect is obtained for the insulated gate semiconductor devices of the second to fourth embodiments from which the buffer region 11 is removed.
[0040]
In the first, second, and fifth embodiments, the end of the p-type base region has a stepped shape or a tapered shape in order to increase the breakdown voltage and increase the latch-up resistance. + Bonded to the emitter region. However, when high breakdown voltage is not required, the thickness of the p-type base region 16 (or 56) is set to n as shown in FIGS. + The thickness may be the same as that of the emitter regions 15a and 15b (or 55a and 55b). In this case, the etching process by RIE is simplified and the cost is reduced.
[0041]
In the first to fifth embodiments, a plurality of gate electrodes and a plurality of emitter regions are formed to form a bilaterally symmetric structure. However, when it is not necessary to obtain a large current, a structure on only one side may be used.
[0042]
In the present embodiment, the IGBT and MOSFET comprising the n-type field effect transistor Tr1 and the pnp-type bipolar transistor Tr2 have been described as examples. However, these polarities are reversed, and the p-type field-effect transistor Tr1 and the npn-type bipolar transistor Tr2 are reversed. It is good also as IGBT and MOSFET which consist of.
[0043]
Furthermore, in the present embodiment, the vertical IGBT has been described. However, as long as the characteristic operation principle claimed by the present invention is the same, the present invention is not limited to the vertical type, and various other forms such as a horizontal IGBT can be used. The present invention can be applied to an insulated gate semiconductor device having the same.
[Brief description of the drawings]
FIG. 1 is a structural cross-sectional view of an insulated gate semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a manufacturing process diagram of an insulated gate semiconductor device according to the first embodiment of the present invention.
FIG. 3 is an equivalent circuit diagram of an insulated gate semiconductor device according to the first embodiment of the present invention.
FIG. 4 is a structural cross-sectional view showing a modified example of the insulated gate semiconductor device according to the first embodiment.
FIG. 5 is a characteristic diagram showing the relationship between the interelectrode distance and the on-voltage in the insulated gate semiconductor device according to the first embodiment.
FIG. 6 is a cross-sectional view of an insulated gate semiconductor device according to a second embodiment of the present invention.
FIG. 7 is a structural cross-sectional view of an insulated gate semiconductor device according to a third embodiment of the present invention.
FIG. 8 is a structural sectional view of an insulated gate semiconductor device according to a fourth embodiment of the present invention.
FIG. 9 is a structural sectional view of an insulated gate semiconductor device according to a fifth embodiment of the invention.
FIG. 10 relates to a modification of the first embodiment, and n + FIG. 5 is a cross-sectional view of the configuration of an insulated gate semiconductor element excluding a buffer layer.
FIG. 11 relates to a modification of the first embodiment and relates to a p base region and n + FIG. 5 is a cross-sectional view of a configuration of an insulated gate semiconductor device in which the thickness of the emitter region is made equal.
FIG. 12 relates to a modification of the second embodiment and relates to a p base region and n + FIG. 5 is a cross-sectional view of a configuration of an insulated gate semiconductor device in which the thickness of the emitter region is made equal.
FIG. 13 relates to a modification of the fifth embodiment and relates to a p base region and n + FIG. 5 is a cross-sectional view of a configuration of an insulated gate semiconductor device in which the thickness of the emitter region is made equal.
FIG. 14 is a structural cross-sectional view of a conventional insulated gate semiconductor device.
[Explanation of symbols]
10 p + Collector area
11 n + Buffer area
12 n - Shape base area
12A Carrier accumulation area
13a Gate electrode
13b Gate electrode
14a Electrical insulation film
14b Electrical insulation film
15an + Emitter area
15b n + Emitter area
16 p-type base region
17a Inversion layer
17b Inversion layer
18 Emitter electrode
19 Collector electrode
20 Electrical insulation

Claims (2)

  1. An insulated gate semiconductor device, wherein a gate electrode with an electrical insulating film is provided on a side surface of a flow path of a first conduction type carrier and a second conduction type carrier, and an emitter electrode and a first conduction type emitter region are formed by a gate voltage. the second conductivity type base region on the electrically insulating layer, the first conductivity type carriers flows through a path of the first conductivity type base region, the gate voltage, a second conductivity type collector region from the collector electrode, the first conductivity-type base region, said second conductivity type base region, the insulated gate semiconductor element for controlling the current flowing in the path of the emitter electrode,
    It said gate electrode with said electrical insulating film, the upper surface is joined to the lower surface of the second conductive type base region, toward the emitter electrode from the collector electrode, in the direction perpendicular to the main surface of the collector electrode a current path that flows, said to narrow in the central portion of the surface parallel to the main surface, has a constant thickness in the horizontal direction, are formed extending from the periphery of the insulated gate semiconductor device,
    The emitter electrode includes an upper part of the narrowed current path , and is bonded to the entire upper surface of the first conduction type emitter region and the second conduction type base region,
    The collector electrode is formed on the entire surface of the lower surface of the second conductivity type collector region,
    In the junction surface between the second conductivity type base region and the emitter electrode, the second conductivity type base region has a step where the central portion side is thick and the first conductivity type emitter region side is thin,
    The first conductivity type emitter region is on the electrically insulating film of the gate electrode facing the emitter electrode, and at the position where an inversion layer is formed on the electrically insulating film, Formed to be joined to the second conductivity type base region;
    The insulated gate semiconductor device according to claim 1, wherein a thickness of the first conductivity type emitter region is smaller than a thickness at a central portion of the second conductivity type base region due to the step.
  2. The vicinity of the junction between the second conductivity-type base region of the first conductivity type base region, narrowing the current path leading to said second conductivity type base region of the second conductivity type carriers injected from the collector region 2. The insulated gate semiconductor device according to claim 1, wherein an electrically insulating region is formed.
JP15731299A 1999-06-04 1999-06-04 Insulated gate type semiconductor device Expired - Fee Related JP4696327B2 (en)

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GB0404751D0 (en) * 2004-03-03 2004-04-07 Koninkl Philips Electronics Nv Trench field effect transistor and method of making it
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH098304A (en) * 1995-06-19 1997-01-10 Siemens Ag Mos semiconductor element with good continuity characteristic
JPH0992828A (en) * 1995-09-27 1997-04-04 Hitachi Ltd Insulated bipolar transistor and its manufacture
JPH10294461A (en) * 1997-04-21 1998-11-04 Toyota Central Res & Dev Lab Inc Insulation gate type semiconductor element

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH098304A (en) * 1995-06-19 1997-01-10 Siemens Ag Mos semiconductor element with good continuity characteristic
JPH0992828A (en) * 1995-09-27 1997-04-04 Hitachi Ltd Insulated bipolar transistor and its manufacture
JPH10294461A (en) * 1997-04-21 1998-11-04 Toyota Central Res & Dev Lab Inc Insulation gate type semiconductor element

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