JP2000349284A - Insulated gate semiconductor element - Google Patents

Insulated gate semiconductor element

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Publication number
JP2000349284A
JP2000349284A JP11157312A JP15731299A JP2000349284A JP 2000349284 A JP2000349284 A JP 2000349284A JP 11157312 A JP11157312 A JP 11157312A JP 15731299 A JP15731299 A JP 15731299A JP 2000349284 A JP2000349284 A JP 2000349284A
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Japan
Prior art keywords
region
base region
emitter
conductivity type
type base
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JP11157312A
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JP4696327B2 (en
Inventor
Masayasu Ishiko
Sachiko Kawaji
Toshio Murata
年生 村田
佐智子 河路
雅康 石子
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Toyota Central Res & Dev Lab Inc
株式会社豊田中央研究所
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Abstract

(57) Abstract: Provided is an insulated gate semiconductor device having a high latch-up withstand voltage, a low on-voltage, and a high withstand voltage. An insulating film is provided on an n - base region.
The gate electrodes 13a and 13b accompanied by b are arranged so as to narrow the carrier diffusion channel. Also, n + emitter region 1
5a and 15b are arranged on both upper ends of the electrical insulating films 14a and 14b. Further, the p base region 16 is formed to have a thickness corresponding to a predetermined withstand voltage, and its end is formed thinner.
The junction is made with the n + emitter regions 15a and 15b. With such a structure, a high breakdown voltage can be achieved, and an increase in the potential of the p base region 16 can be suppressed. That is, the function of the parasitic transistor is suppressed, and the latch-up withstand capability is improved.
Also, the concentration of the carrier near the narrowed flow path increases,
The ON voltage is reduced by the conductivity modulation effect.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device for controlling a current flowing between two other electrodes by applying a voltage to a gate electrode. In particular, the present invention relates to a structure of an insulated gate semiconductor device for the purpose of achieving high latch-up resistance and low on-voltage.

[0002]

2. Description of the Related Art An insulated gate transistor changes the electric conductivity of a semiconductor by an electric field effect of a gate voltage and controls a current flowing between other regions provided at both ends of a gate region. For example, an IGBT (Insulated Gate Bipolar Transistor) is known for electric power. The IGBT controls a current of several tens of amps with a control voltage of tens of volts. However,
When a large current flows, a parasitic transistor described below operates due to the internal structure, and a latch-up state is brought about. Therefore, conventionally, a high latch-up withstand voltage and a low on-state voltage have been required. For example, there is a vertical IGBT as a semiconductor element in consideration of high latching resistance and low on-voltage. In addition, there is a semiconductor device (JP-A-1-198076) having substantially the same structure and featuring a gate electrode having a trench structure.

FIG. 14 shows a structure of a conventional vertical IGBT. Its equivalent circuit is the same as FIG. Vertical IGBT
Is a silicon substrate doped with p + -type impurities as a collector region 70, on which an n + -type silicon substrate is sequentially formed by a so-called planar technology such as an epitaxial growth technology, a lithography technology, an ion implantation technology, a diffusion technology, and an etching technology. buffer region 71, n - -type base region 72,
p-type base region 73, n + -type emitter region 74, p + -type emitter region 80, insulated gate film 76, and CVD (Ch
The gate electrode 75, the emitter electrode 77 and the collector electrode 78 are formed by emical vapor deposition. In some cases, the n-type buffer region 71 does not need to be formed.

Referring to FIGS. 14 and 3, in this device, an n + -type emitter region 74, a p-type base region 73,
n - field effect transistor in the form the base region 72 (Tr
1) is formed, and the p-type base region 73, the n -type base region 72, and the p + -type collector region 70 form a bipolar transistor (Tr2). This is a structure that controls the current flowing through Tr2 by controlling Tr1.
The bipolar transistor (Tr3) formed by the n + -type emitter region 74, the p-type base region 73, and the n -type base region 72 has a parasitic structure.

When a positive voltage of, for example, several hundred volts is applied to the collector electrode 78 and a positive voltage of several volts to tens of volts is applied to the gate electrode 75, the field effect transistor shown in FIG. Tr1) is turned on, and electrons flow into the n -type base region 72. As a result, holes are injected from the p + type collector region into the n − type base region 72,
A conductivity modulation effect occurs in which the electron concentration and the hole concentration in the high resistivity n -type base region 72 are increased equally. IG
The BT is an element that can reduce the ON voltage by the conductivity modulation effect. Its switching speed is one order of magnitude faster than power transistors, and its current capacity is MOS
It is one to two orders of magnitude larger than a transistor.
Since the switching speed is high, it is increasingly required in recent years to increase the current capacity.

[0006]

However, IGB
As described above, T has an npn-type parasitic transistor Tr3 including an n + emitter region 74, a p-type base region 73, and an n -type base region 72. When a large current flows to tr2, i.e. the n - type base from the area 72 when a large current flows to the p + emitter region 80, because of the resistance Rp on the p + emitter region 80, the emitter electrode 77 and the p-type base region 7
3, a potential difference of ΔV (= I · Rp) occurs. When this ΔV exceeds a threshold voltage (about 0.7 V), Tr
3 is turned on. That is, Tr2 and T shown in FIG.
There is a problem that the thyristor composed of r3 is turned on, current always flows, and the IGBT cannot be controlled with the gate voltage (latch-up state).

Therefore, in the conventional example, the resistance value Rp is reduced by providing a p + emitter region 80 with an even higher impurity concentration, or in some cases, the p + emitter region 80 is removed and replaced with a trench structure electrode (for example, Unexamined Japanese Patent Publication (Kokai) No. 1-198076), a method has been devised in which an electrode is directly joined to the p-type base region 73 to avoid latch-up. However, as in the conventional example, the p-type base region 73
And a structure in which a hole current is easily injected into the pn junction surface by the n + emitter region 74. When a larger current flows, the potential of the p-type base region 73 rises and the parasitic thyristor is turned on as before. Thus, higher latch-up withstand capability was not realized.

If the space between the gate electrodes 75 is reduced, p +
The holes injected from the collector region 70 are accumulated in the n base region 72 to improve the conductivity modulation effect, and as a result, the on-voltage can be reduced. However, the n + emitter region 74, the p-type base region 73,
In the conventional configuration in which the p + emitter region 80 is formed between the gate electrodes, there is a limit in narrowing the gap. That is, there is a limit in reducing the on-state voltage.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide an insulated gate semiconductor device, particularly an IGBT, with a positional relationship between an n + emitter region, a gate electrode, and a p-type base region. And n
+ Depending on the junction shape between the emitter region and p-type base region,
An object of the present invention is to provide an insulated gate semiconductor device which suppresses the flow of a hole current and is excellent in high latch-up withstand voltage, low on-voltage and high withstand voltage.

[0010]

In order to achieve this object, an insulated gate semiconductor device according to claim 1 is an insulated gate semiconductor device, comprising a first conductivity type carrier and a second conductivity type carrier. A gate electrode provided with an electrically insulating film on a side surface of the flow path, and a collector region, a second conductivity type base region, a first conductivity type base region,
An insulated gate semiconductor device for controlling a current flowing through a path of a second conductivity type base region and an emitter electrode, wherein the gate electrode with an electrically insulating film narrows the flow path of the carrier in a region near the emitter electrode. The first conductive type emitter region is formed in a predetermined shape and at a predetermined depth, and is formed by joining the emitter electrode and the second conductive type base region on the electrical insulating film of the gate electrode facing the emitter electrode. In addition, the thickness of the first conductivity type emitter region is not more than the thickness at the center of the second conductivity type base region.

According to a second aspect of the present invention, in the insulated gate semiconductor device, the second conductivity type base region is formed in a stepped or tapered shape at an end thereof and is joined to the first conductivity type emitter region. I do.

According to a third aspect of the present invention, there is provided an insulated gate semiconductor device, wherein the first conductive type base region has a second conductive type carrier injected from the collector region near the junction with the second conductive type base region. An electrically insulating region is formed so as to narrow a path leading to the two-conduction type base region.

[0013]

In the insulated gate semiconductor device according to the first aspect, the gate electrode with the electrically insulating film is
In a region near the emitter electrode, the carrier is formed in a predetermined shape and a predetermined depth so as to narrow the flow path of the first conductivity type carrier and the second conductivity type carrier. When the second conductivity type carriers injected from the second conductivity type collector region into the first conductivity type base region diffuse into the second conductivity type base region, it is difficult to reach the first conductivity type emitter region, and the emitter becomes difficult to reach. The first conductivity type emitter region is formed on the electrical insulating film of the gate electrode facing the emitter electrode and joined to the emitter electrode and the second conductivity type base region so as to easily reach the electrode. The thickness of the first conductivity type emitter region in the current direction is set to be equal to or less than the thickness of the second conductivity type base region.

When a voltage is applied to the gate electrode, first, a first conductivity type emitter region, a second conductivity type base region,
The field effect transistor formed of the conduction type base region is turned on, and the first conduction type carrier is injected from the first conduction type emitter region into the second conduction type base region. Accordingly, carriers of the second conductivity type are injected from the collector region of the second conductivity type into the base region of the first conductivity type, and diffuse into the base region of the first conductivity type. The diffused carriers of the second conductivity type pass through the channel narrowed by the gate electrode with the electric insulating film, and the position and direction of diffusion are restricted.

On the other hand, the first conduction type emitter region, the second conduction type base region and the first conduction type base region constitute a parasitic transistor. The first conductivity type emitter region also serving as the emitter of the parasitic transistor is formed at a position distant from the diffusion flow, that is, on the electrical insulating film of the gate electrode facing the emitter electrode side. Therefore, the minority carriers subject to this limitation hardly flow into the first conductivity type emitter region, and the majority flow directly into the emitter electrode. That is, the potential of the second conductivity type base region that is the base of the parasitic transistor does not rise. That is, the parasitic transistor does not turn on within the predetermined maximum current value. Therefore, high latch-up is realized.

At this time, it is desirable that the thickness of the first conductivity type emitter region in the current direction is set to be equal to or less than the thickness of the second conductivity type base region. When the thickness of the first conductivity type emitter region in the current direction is reduced, the resistance component is also reduced, and the potential increase of the second conductivity type base region due to the first conductivity type carrier is suppressed. Therefore, a larger current can be achieved. In other words, the ON voltage can be further reduced.

Further, since the flow path is narrowed by the gate electrode with the electrically insulating film, the density of the second conductive type carrier in the flow path in the first conductive type base region is increased. The conductivity modulation effect in the region near the emitter electrode in the base region is also increased, and the on-voltage can be substantially reduced.

According to a second aspect of the present invention, in the insulated gate semiconductor device, the second conductivity type base region is formed in a stepped or tapered shape at its end, and is joined with the same thickness as the first conductivity type emitter region. I have. Most of the second conductivity type carriers diffused from the first conductivity type base region to the second conductivity type base region are directed to the emitter electrode, but part of the carriers are directed to the first conductivity type base region.
To the conduction type emitter region. At this time, the thickness of the second conductivity type base region is not uniform, and is formed in a stepped or tapered shape at its end. That is, the emitter electrode is formed so as to narrow the path of the second conductivity type carrier. Therefore, the carrier heading for the first conductivity type emitter region is absorbed by the emitter electrode on the way.
In other words, the resistance between the second conductivity type base region and the first conductivity type emitter region is reduced. That is, the potential increase of the second conductivity type base region due to the second conductivity type carrier is suppressed. Therefore, for the same reason, the latch-up withstand capability is improved, and the current can be further increased. In addition, since the second conductivity type base region can be made thick, a high breakdown voltage can be achieved. As a result, an insulated gate semiconductor device having a high withstand voltage and a high latch-up withstand capability is obtained.

According to a third aspect of the present invention, in the insulated gate semiconductor device, the second conductivity type carrier injected from the collector region is located near the junction of the first conductivity type base region with the second conductivity type base region. An electrically insulating region that narrows the path to the two-conductivity base region is formed. Since the electrically insulating region is formed in the flow path of the second conductivity type carrier in the first conductivity type base region narrowed by the gate electrode, the second conductivity type carrier which is a minority carrier injected from the collector region Is accumulated in the high-resistance base region, which is the first conductivity type base region, and its concentration is improved. In the high-resistance base region near the emitter region, the concentration of minority carriers is improved, so that the conductivity modulation is increased, and as a result, the on-voltage is reduced. Therefore, claim 1
As in the case of the insulated gate semiconductor device described above, the enhancement of the latch-up withstand capability is maintained, and further lowering of the on-state voltage can be realized. In the above description, if the first conductivity type is n-type, the first conductivity type carrier is an electron, the second conductivity type is a p-type, and the second conductivity type carrier is a hole. Conversely, if the first conductivity type is p-type, the first conductivity type carrier is a hole, the second conductivity type is an n-type, and the second conductivity type carrier is an electron.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described based on specific embodiments. The present invention is not limited to the following examples. First Embodiment In the following description, the first conductivity type is an n-type, the first conductivity type carrier is an electron, the second conductivity type is a p-type, and the second conductivity type carrier is a hole. FIG. 1 shows a first embodiment of the IGBT according to the present invention. The figure is a sectional view showing the cell structure. The insulated gate semiconductor device of this embodiment has a p + -type collector region 1.
The n + -type buffer region 11 on the 0, the high resistance region is formed on the n + -type buffer region 11 n - base region 12
have. The cell pitch w is about 4 μm.

Further, a gate electrode 13 with electric insulating films 14a and 14b is provided on both upper side surfaces of the n - base region 12.
a and 13b, and both electrodes are formed with a distance L between the electrodes in the n base region 12 so as to narrow the flow path of the carrier. Further, the p-type base region 1 is in close contact with a part of the electrical insulating films 14a and 14b and the n -type base region 12.
And n + -type emitter regions 15a and 15b on the electrical insulating films 14a and 14b on both sides. At this time, the end of the p-type base region 16 is joined to the n + -type emitter regions 15a and 15b with a step. Further, an emitter electrode 18 is formed on the n + -type emitter regions 15a, 15b and the adjacent p-type base region 16,
+ Collector electrode 19 is formed in collector region 10. The insulated gate semiconductor device of this embodiment has such a structure.

FIG. 2 shows a method for manufacturing the insulated gate semiconductor device. The above structure is manufactured by a planar technology centering on a lithography technology and a solid phase epitaxial technology. In this embodiment, the process is divided into the following four steps (a) to (d). FIG. 2 shows a main part of the manufacturing process, and portions not shown are the same as those in FIG.
In step (a), first, the p + silicon substrate shown in FIG.
On the + collector region 10, for example, an n + epitaxial layer 11 having a thickness of 15 μm is formed. Next, an n epitaxial layer having a thickness of, for example, 60 μm is formed on the n + epitaxial layer 11, and an n base region 12 is formed (FIG. 2). At this time, the impurity concentration of n -type base region 12 is 1
× 10 14 / cm 3 . Next, heat treatment is performed in this state. Thereby, a silicon oxide film having a thickness of, for example, 100 nm is formed on the surface of n -type base region 12. The silicon oxide film becomes a part of an electrical insulating film 14b described later. Thereafter, phosphorus-doped polycrystalline Si having a thickness of, for example, 200 nm and a silicon oxide film having a thickness of 100 nm are sequentially deposited, and the central portion is removed by a patterning technique and an etching technique. As a result, the upper and lower portions are electrically insulating films 14.
Gate electrodes 13a and 13b sandwiched between the gate electrodes 13a and 14b are formed (FIG. 2A).

Next, in step (b), a silicon oxide film or the like is deposited on this substrate to a thickness of 50 to 200 nm. Then, R
The gate electrode 13a, IE (Reactive lon Etching)
A silicon oxide film is formed on the side wall 13b, and a side wall 14c is formed as an electrical insulating film (FIG. 2B).
. Next, the process proceeds to step (c). Note that the electrical insulating film 14
The thickness of each of a, 14b and 14c is about 0.1 μm.

In the step (c), thereafter, for example, the thickness of 1 μm
m amorphous Si by CVD or the like, and SPE
(Solid Phase Epitaxy) Single crystal Si layer 16A by technology etc.
To form Then, this single-crystal Si layer 16A is
According to IE, the thickness is 0. Reduce the thickness to 5 μm (Fig. 2 (c)).
Next, the process proceeds to step (d).

In the step (d), for example, boron is ion-implanted in the center by a resist pattern technique and an ion implantation technique to form a p base region 16. Further, for example, phosphorus is ion-implanted into both ends to form an n + emitter region 15.
a and 15b are formed. Then, a desired impurity profile is obtained by thermal diffusion or the like. After that, the n + -type emitter regions 15a,
The region 5b is etched to a predetermined thickness, for example, approximately 0.3 μm. At this time, the n + -type emitter region 15a,
The impurity surface concentration of 15b is 1 × 10 20 / cm 3 .
Thus, the basic structure of the insulated gate semiconductor device is manufactured. (FIG. 2 (d)). Incidentally, the etching in the step (d) includes the p-type base region 16 and the n + -type emitter region 15a,
15b. As will be described in detail later, such a structure realizes a high withstand voltage and a high latch-up withstand capability. This etching may be performed before the formation of the p base region 16 and the n + emitter regions 15a and 15b. The above is the manufacturing method of the insulated gate semiconductor device of the present embodiment.

Next, the operation of the insulated gate semiconductor device will be described with reference to FIGS. FIG. 3 is an equivalent circuit of the insulated gate semiconductor device having the above configuration. This element is designed to have a withstand voltage of 600 V and a cutoff voltage of 4 V. The emitter electrode 18 is grounded, a positive voltage of several hundred volts is applied to the collector electrode 19, and a positive voltage of several volts to tens of volts sufficiently higher than the cutoff voltage is applied to the gate electrodes 13a and 13b. At this time, first, the inversion layer 17 is formed on the boundary between the p-type base region 16 and the electrical insulating films 14a and 14b by the electric field effect.
a and 17b (FIG. 1). The electrons in the inversion layer 17
a, 17b through n + emitter regions 15a, 15b, respectively.
15b from n - flows to form the base region 12 (i.e. 3
Tr1 of the equivalent circuit shown in (1) turns ON), and is diffused toward the collector region 10 by a strong electric field.

On the other hand, when the diffusion of electrons proceeds sufficiently, n-Shape
The potential of the source region 12 decreases. n -Shape base region 12
Is lowered, the pn junction is biased in the forward direction.
Because p+Holes from the collector region 10-form
It is implanted in the base region 12. The injected holes are n
-The base region 12 is diffused in the direction of the emitter electrode 18.
And the carrier storage narrowed by the gate electrodes 13a and 13b.
It is collected in the product area 12A. As a result,
Carrier concentration is increased, and n-Shape
Therefore, the resistance value of the source region 12 is reduced. This
Large current flows into the emitter regions 15a and 15b,
And n-The holes in the base region 12 are also p-type as large current
It flows into the base region 16. That is, Tr2 is turned on.
Become.

At this time, usually, the p-type base region 16 has
There is a resistance Rp in the direction of the emitter electrode 18. There are two paths for passing carriers: a path directly toward the emitter electrode 18 and a path passing through the n + -type emitter regions 15a and 15b.
There is a route. That is, the resistance Rp is a combined resistance of the resistance values of the two paths. Thus, when a large current flows, the potential of the p-type base region 16 rises, and the n + -type emitter region 1
Parasitic Tr3 comprising 5a, 15b, p-type base region 16 and n -type base region 12 is turned on. That is, a latch-up state in which current cannot be controlled from Tr1 and current continues to flow is established.

In order not to generate this potential difference while securing a large current, it is necessary to make this Rp as small as possible. Therefore, in the present invention, the junction area between the p-type base region 16 and the emitter electrode 18 is set to be three times or more as compared with the conventional vertical gate structure in order to minimize the resistance value Rp. Since the resistance value is inversely proportional to the area, Rp is reduced as compared with the prior art, and latch-up hardly occurs. That is, the latch-up resistance is improved.

Further, the thickness of the p-type base region 16 is reduced (about 0.5 μm) to the withstand voltage limit. Since the resistance value is proportional to the resistance length, if the thickness of the p-type base region 16 is reduced to the withstand voltage limit, Rp is reduced as compared with the related art. Also,
The n + -type emitter regions 15a and 15b are
a, 14b are provided at both ends on the carrier flow path. Some of the holes flow into the n + -type emitter regions 15a and 15b, and the thickness is 0.3 μm, which is close to the processing limit. Therefore, the resulting resistance component is reduced to the limit. Therefore,
The high withstand voltage performance can be maintained, and the latch-up withstand capability can be further improved.

Further, the p-type base region 16 has a step structure at its end, and is joined to the n + -type emitter regions 15a and 15b with a thickness of 0.3 μm. Therefore, part of the holes directed to the n + -type emitter regions 15a and 15b are absorbed by these steps. That is, an increase in the potential of the p-type base region 16 is suppressed. That is, this structure also improves the latch-up resistance.

As a result, the collector current density was 200 A / c
With m 2 and a fall time of 300 nsec, the latch-up resistance was improved by 10% or more as compared with the conventional case.
In the above example, the p-type base region 16 is formed into a stepped shape by RIE and joined to the n + -type emitter regions 15a and 15b. However, as shown in FIG. 4, the joint may be tapered. This tapered shape can be formed by LOCOS oxidation and removal of the oxide film. In this case, there is an effect that the embedding failure of the emitter electrode 18 is reduced.

Further, the configuration of the insulated gate semiconductor device in this embodiment can further reduce the on-state voltage. The distance L between the electrodes (the carrier accumulation region 12A) is the same as the structure of the n + -type emitter regions 15a and 15b.
This is because it is possible to reduce the diameter to the processing limit. When the carrier accumulation region 12A is narrowed, holes are sufficiently accumulated. That is, the conductivity modulation is performed more sufficiently, and the ON voltage of the element is greatly reduced. FIG. 5 shows the relationship between the inter-electrode distance L and the ON voltage. The horizontal axis is the distance L between the electrodes, and the vertical axis is the on-voltage. As can be seen from FIG. 5, when the distance L between the electrodes is about 0.2 μm, the ON voltage is 1.15V. As a result, the on-state voltage was reduced by almost 20% compared to the related art. Therefore, when the insulated gate semiconductor device is configured as described above, it is an excellent semiconductor device that simultaneously realizes high withstand voltage, high latch-up withstand voltage, and low on-voltage.

Second Embodiment FIG. 6 shows a second embodiment of the insulated gate semiconductor device of the present invention. The figure is a configuration sectional view. This embodiment is characterized in that the carrier flow path 12A in the n -type base region 12 narrowed by the plurality of gate electrodes 13a and 13b of the first embodiment.
In addition, the electric insulator 20 is buried to narrow the carrier flow path. With such a structure, holes diffused from p + collector region 10 accumulate in a channel that is further narrowed, so that the conductivity modulation effect is further enhanced.
Therefore, the on-state voltage can be reduced as compared with the first embodiment. In this case, the junction between the p-type base region 16 and the n + -type emitter regions 15a and 15b may be tapered. Regardless of the joint shape, if the electrical insulator 20 is embedded in the carrier flow path, the ON voltage can be reduced.

Third Embodiment FIG. 7 shows a third embodiment of the insulated gate semiconductor device of the present invention. The figure is a configuration sectional view. In the present embodiment, the plurality of gate electrodes 13a and 13b of the first embodiment are formed in a wedge shape as shown, and the emitter regions 15a and 15b are formed at both ends on the electrical insulating films 14a and 14b, respectively. Is the feature. Even with such a configuration, the emitter region 1
Since 5a and 15b are located at locations away from the flow path of the hole, Rp can be reduced. Further, since the p base region can be set to be thick, a high withstand voltage as well as a high latch-up withstand capability can be realized. Further, similarly to the first embodiment, since the holes of the minority carriers are accumulated in the narrowed carrier accumulation region 12A, the conductivity modulation effect is enhanced, and the on-voltage can be reduced. Such a configuration is effective when a high withstand voltage is particularly required for the insulated gate semiconductor element.

Fourth Embodiment FIG. 8 shows a fourth embodiment of the insulated gate semiconductor device of the present invention. The figure is a configuration sectional view. The features of this embodiment are as follows.
As shown in the figure, the p-type base region 16 of the first embodiment is extended to the carrier accumulation region 12A narrowed by the gate electrodes 13a and 13b. , 17b. Also, the n + type emitter region 15
Similarly, a and 15b are formed on the electrical insulating films 14a and 14b on the emitter electrode 18 side. Even with such a configuration, the n + emitter region 15a of the p base region 16
Since the thickness of the portion in contact with 15b can be reduced to the processing limit, Rp can be reduced. Therefore,
Similarly, a high latch-up tolerance is obtained. As in the first embodiment, holes of minority carriers are accumulated in the narrowed carrier accumulation region 12A. Therefore, the effect of reducing the ON voltage is equivalent to that of the first embodiment.

Fifth Embodiment FIG. 9 shows a fifth embodiment of the insulated gate semiconductor device of the present invention. The figure is a configuration sectional view. The features of this embodiment are as follows.
As shown, the n + buffer region 11 of the first embodiment is removed, an n + type drain region 50 is formed in place of the p + collector region 10, and the n − type base region 12 is changed to n −.
Drain region 51, the emitter electrode 18 is a source electrode 180, the collector electrode 19 is a drain electrode 190, and the entire device is a field effect transistor (MOSFET).
It is what it was.

In a MOSFET, when driving an inductance load, avalanche destruction caused by the operation of a parasitic bipolar transistor is a serious problem, and it is very important to improve the resistance to this.
As one method for improving the avalanche resistance, n +
Source regions 55a and 55b, p-type base region 56 and n
- How to make it difficult to turn on the bipolar npn transistors of the parasitic composed of the form drain region 51 is raised. In the MOSFET of the present embodiment, as in the first embodiment, the resistance Rp of the p-type base region 56 can be made extremely small. Can be. Therefore, a higher avalanche withstand voltage and lower on-state voltage can be realized as compared with the conventional MOSFET. Similarly, the embodiment shown in FIGS. 6, 7, and 8 may be a MOSFET having a source, gate, and channel structure. In this case as well, the p-type base region 56 may be tapered at its end and joined to the n + -type emitter regions 55a and 55b.
Irrespective of the junction shape, a high avalanche resistance and a low on-voltage can be realized.

Modifications The present invention is capable of various other modifications.
For example, in the first embodiment, the p + collector region 10
The n + buffer region 11 is provided on the upper part of the semiconductor device. However, this structure is removed, and the present structure has the same effect on an insulated gate semiconductor device as shown in FIG. , Lower on-voltage can be realized. n +
Similar effects are obtained for the insulated gate semiconductor devices of the second to fourth embodiments in which the buffer region 11 is removed.

In the first, second, and fifth embodiments, the end of the p-type base region is formed to have a stepped or tapered shape in order to achieve a high withstand voltage and a high latch-up resistance. + Junction with emitter region. However, when high withstand voltage is not required, FIGS.
As shown in FIG. 13, the p-type base region 16 (or 56)
Of the n + emitter regions 15a, 15b (or 55
a, 55b). In this case, R
The etching process by the IE is simplified and the cost is reduced.

In the first to fifth embodiments, a plurality of gate electrodes and a plurality of emitter regions are formed to have a symmetrical structure. However, when it is not necessary to obtain a large current, a structure having only one side may be used. Good.

In this embodiment, the n-type field effect transistor Tr1 and the pnp type bipolar transistor T
Although the IGBT and MOSFET made of r2 have been described as examples, the IGBT and MOSFET may be made of p-type field effect transistor Tr1 and npn-type bipolar transistor Tr2 with their polarities reversed.

Further, in this embodiment, the vertical type IGBT has been described. However, as long as the characteristic operation principle claimed by the present invention is the same, the present invention is not limited to the vertical type IGBT.
The present invention can be applied to insulated gate semiconductor devices having various other forms such as GBT.

[Brief description of the drawings]

FIG. 1 is a configuration sectional view of an insulated gate semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a manufacturing process diagram of the insulated gate semiconductor device according to the first embodiment of the present invention.

FIG. 3 is an equivalent circuit diagram of the insulated gate semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a configuration sectional view showing a modification of the insulated gate semiconductor device according to the first embodiment.

FIG. 5 is a characteristic diagram showing a relationship between an inter-electrode distance and an on-voltage in the insulated gate semiconductor device of the first embodiment.

FIG. 6 is a configuration sectional view of an insulated gate semiconductor device according to a second embodiment of the present invention.

FIG. 7 is a configuration sectional view of an insulated gate semiconductor device according to a third embodiment of the present invention.

FIG. 8 is a sectional view showing the configuration of an insulated gate semiconductor device according to a fourth embodiment of the present invention.

FIG. 9 is a sectional view showing the configuration of an insulated gate semiconductor device according to a fifth embodiment of the present invention.

FIG. 10 is a cross-sectional view of a configuration of an insulated gate semiconductor device excluding an n + buffer layer according to a modification of the first embodiment.

FIG. 11 is a sectional view of a configuration of an insulated gate semiconductor device according to a modification of the first embodiment, in which the thicknesses of a p base region and an n + emitter region are equal.

FIG. 12 is a configuration sectional view of an insulated gate semiconductor device according to a modification of the second embodiment, in which the thicknesses of a p base region and an n + emitter region are equal.

FIG. 13 is a sectional view of a configuration of an insulated gate semiconductor device according to a modification of the fifth embodiment, in which the thicknesses of a p base region and an n + emitter region are equal.

FIG. 14 is a configuration sectional view of a conventional insulated gate semiconductor device.

[Explanation of symbols]

Reference Signs List 10 p + -type collector region 11 n + -type buffer region 12 n --type base region 12A Carrier accumulation region 13a Gate electrode 13b Gate electrode 14a Electrical insulating film 14b Electrical insulating film 15an + emitter region 15b n + emitter region 16p Base region 17a inversion layer 17b inversion layer 18 emitter electrode 19 collector electrode 20 electrical insulator

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Masayasu Ishiko 41-41, Yokomichi, Nagakute-cho, Aichi-gun, Aichi Prefecture Inside Toyota Central Research Laboratory Co., Ltd.

Claims (3)

[Claims]
1. An insulated gate semiconductor device, comprising: a gate electrode with an electric insulating film provided on a side surface of a flow path of a first conductivity type carrier and a second conductivity type carrier; An insulated gate semiconductor device for controlling a current flowing through a path of a conduction type collector region, a first conduction type base region, a second conduction type base region, and an emitter electrode, wherein the gate electrode with the electrically insulating film is the emitter The first conductive type emitter region is formed on the electrical insulating film of the gate electrode facing the emitter electrode so as to have a predetermined shape and a predetermined depth so as to narrow the flow path in a region near the electrode. An emitter electrode is formed so as to be joined to the second conductivity type base region, and the thickness of the first conductivity type emitter region is set at the center of the second conductivity type base region. Insulated gate semiconductor device which is characterized in that less than the thickness at.
2. The insulated gate according to claim 1, wherein the second conductivity type base region is formed in a step or tapered shape at an end thereof and is joined to the first conductivity type emitter region. Semiconductor device.
3. A path of the second conductivity type carrier injected from the collector region to the second conductivity type base region near the junction of the first conductivity type base region with the second conductivity type base region. 3. The insulated gate semiconductor device according to claim 1, wherein an electrically insulating region is formed to be narrow.
JP15731299A 1999-06-04 1999-06-04 Insulated gate type semiconductor device Expired - Fee Related JP4696327B2 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005088724A1 (en) * 2004-03-03 2005-09-22 Koninklijke Philips Electronics N.V. Trench field effect transistor and method of making it
JP2007043028A (en) * 2004-09-02 2007-02-15 Fuji Electric Holdings Co Ltd Semiconductor device and its manufacturing method

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH098304A (en) * 1995-06-19 1997-01-10 Siemens Ag Mos semiconductor element with good continuity characteristic
JPH0992828A (en) * 1995-09-27 1997-04-04 Hitachi Ltd Insulated bipolar transistor and its manufacture
JPH10294461A (en) * 1997-04-21 1998-11-04 Toyota Central Res & Dev Lab Inc Insulation gate type semiconductor element

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH098304A (en) * 1995-06-19 1997-01-10 Siemens Ag Mos semiconductor element with good continuity characteristic
JPH0992828A (en) * 1995-09-27 1997-04-04 Hitachi Ltd Insulated bipolar transistor and its manufacture
JPH10294461A (en) * 1997-04-21 1998-11-04 Toyota Central Res & Dev Lab Inc Insulation gate type semiconductor element

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005088724A1 (en) * 2004-03-03 2005-09-22 Koninklijke Philips Electronics N.V. Trench field effect transistor and method of making it
JP2007043028A (en) * 2004-09-02 2007-02-15 Fuji Electric Holdings Co Ltd Semiconductor device and its manufacturing method

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