JP2013214551A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can reduce on-resistance and provide a manufacturing method of the semiconductor device.SOLUTION: A manufacturing method of a semiconductor device which includes a semiconductor substrate 11 composed of a first conductivity type first semiconductor region, and a second electrode 17 formed in an insulation film in a first trench in an end region in such a manner that the insulation film on the end region side is thicker than the insulation film on a cell formation region side, comprises: a process of forming a second trench which is adjacent to the first trench and has a trench width smaller than that of the first trench and reaches the first semiconductor region; and a process of forming the insulation film s in the first trench and the second trench and integrating the insulation films in the first trench in the end region and in the second trench by a heat treatment.

Description

  Embodiments described herein relate generally to a semiconductor device and a method for manufacturing the same.

MOSFETs used in power switches, etc. (Metal-Oxide-Semiconductor Field Effe
Since ct Transistor) is often used under high voltage, high breakdown voltage characteristics are required. In addition, the MOSFET is also required to reduce the on-resistance in order to reduce switching loss.

JP-A-2005-217202 JP 2009-53850 A

The problem to be solved by the present invention is to provide a semiconductor device capable of reducing on-resistance and a method for manufacturing the same.

A semiconductor device according to an embodiment includes a semiconductor substrate having a first surface, a second surface, and a first semiconductor region of a first conductivity type, a first electrode provided on the first surface, and the second surface side. A second conductive type second semiconductor region provided on the second surface, a second conductive type third semiconductor region provided on the second surface so as to be in contact with the second semiconductor region, and a contact with the third semiconductor region , A fourth semiconductor region of a first conductivity type selectively provided on the second surface, and a first semiconductor region provided in the cell formation region and the end region so as to reach the first semiconductor region from the first surface. Among the insulating films provided in one trench and the first trench in the end region, the insulating film on the end region side is thicker than the insulating film on the cell formation region side. An insulating film provided in the trench, and provided in the first trench through the insulating film; A second electrode, and a third electrode provided on the second surface.

The method of manufacturing a semiconductor device according to the embodiment includes a step of forming a first electrode on the first surface of a semiconductor substrate having a first surface, a second surface, and a first conductivity type first semiconductor region; Second on the side of the face
Forming a conductive second semiconductor region; forming a second conductive third semiconductor region on the second surface so as to contact the second semiconductor region; and contacting the third semiconductor region As described above, the step of selectively forming the fourth semiconductor region of the first conductivity type on the second surface, and the first trench reaching the first semiconductor region from the first surface are divided into a cell formation region and an end region. And forming a second trench adjacent to the first trench, having a width smaller than that of the first trench, and reaching the first semiconductor region from the first surface in the end region. Forming an insulating film in the first trench and the second trench, and integrating the insulating film in the first trench and the second trench in the end region by heat treatment; and Area number Forming a second electrode in the insulating film so that the insulating film on the end region side is thicker than the insulating film on the cell forming region side in the trench; and Forming a third electrode.

1 is a cross-sectional view showing a cross-sectional structure of a semiconductor device 1a according to a first embodiment. 1 is a cross-sectional view showing a cross-sectional structure in an end region of a semiconductor device 1a according to a first embodiment. Sectional drawing which shows a cross-sectional structure for every manufacturing process of the semiconductor device 1a which concerns on 1st Embodiment. Sectional drawing which shows the cross-section in the edge part area | region of the semiconductor device 1b which concerns on a comparative example. Sectional drawing which shows the cross-section in the edge part area | region of the semiconductor device 1c which concerns on 2nd Embodiment. Sectional drawing which shows the cross-sectional structure in the edge part area | region of the semiconductor device 1d which concerns on 3rd Embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In this description, common parts are denoted by common reference numerals throughout the drawings. In this embodiment, the first conductivity type is described as N-type and the second conductivity type is defined as P-type. However, the present invention can be implemented even when the first conductivity type is P-type and the second conductivity type is N-type. . In the following description, the notations of N ⁺ and N, and the notations of P ⁺ and P represent relative levels of impurity concentration. That is, N ⁺ indicates that the N-type impurity concentration is relatively higher than that of N, and P ⁺ indicates that the P-type impurity concentration is relatively higher than that of P. Further, the dimensional ratios in the drawings are not limited to the illustrated ratios. In addition, this embodiment does not limit this invention.

[First Embodiment]
(Structure of the semiconductor device 1a)
The structure of the semiconductor device 1a according to the first embodiment will be described with reference to FIGS. 1 is a cross-sectional view showing a cross-sectional structure of a semiconductor device 1a according to the first embodiment, and FIG.
FIG. 2 is a sectional view showing a sectional structure in an end region of the semiconductor device 1a according to the first embodiment.

The semiconductor device 1a has a MOSFET structure. The semiconductor device 1a includes an N ⁺ type semiconductor substrate 10
(Semiconductor substrate), N-type drift layer 11 (first semiconductor region), P-type base layer 12 (second semiconductor region), P ⁺ -type contact layer 13 (third semiconductor region), N ⁺ -type source layer 14 (first 4 semiconductor region), trench 15 (first trench), field plate oxide film 16 (insulating film),
In-trench source electrode 17 (second electrode), gate electrode 18, external source electrode 19 (third electrode), drain electrode 20 (first electrode), and end trench 31 (first trench) are provided.

The N ⁺ type semiconductor substrate 10 has a first surface and a second surface opposite to the first surface. N
^{The +} type semiconductor substrate 10 has a cell formation region and an end region which is an end of the cell formation region. A plurality of trenches 15 are provided in the cell formation region, and only the end trench 31 is provided in the end region.

In the present embodiment, as an example, silicon (Si) is used for the N ⁺ type semiconductor substrate 10.
Including the second embodiment and the third embodiment, silicon carbide (SiC) is formed on the N ⁺ type semiconductor substrate 10.
Even when gallium nitride (GaN) or the like is used, implementation is possible.

The configuration of the semiconductor device 1a will be described. First, N 2 is formed on the second surface side of the N ⁺ type semiconductor substrate 10.
A type drift layer 11 is provided. A P-type base layer 12 is provided on the second surface side of the N ⁺ -type semiconductor substrate 10 so as to be in contact with the N-type drift layer 11.

A P ⁺ -type contact layer 13 is in contact with the P-type base layer 12 and on the second surface of the N ⁺ -type semiconductor substrate 10.
Is provided. An N ⁺ type source layer 14 is selectively provided on the second surface of the N ⁺ type semiconductor substrate 10 so as to sandwich the P ⁺ type contact layer 13.

A plurality of trenches 15 are provided so as to penetrate the N ⁺ type source layer 14 and the P type base layer 12 from the second surface of the N ⁺ type semiconductor substrate 10 to reach the N type drift layer 11. Only the end trench 31 is provided in the end region of the N ⁺ type semiconductor substrate 10.

In-trench source electrode 17 and gate electrode 18 are provided in trench 15 and end trench 31 via field plate oxide film 16. The in-trench source electrode 17 is located at the approximate center of the trench 15, and the gate electrode 18 is located between the N ⁺ -type source layer 14 and the in-trench source electrode 17. Further, the source electrode 17 and the gate electrode 18 in the trench are made of, for example, polysilicon.

Then, an external source electrode 19 is provided on the second surface of the N ⁺ type semiconductor substrate 10, that is, in contact with the P ⁺ type contact layer 13, the N ⁺ type source layer 14, and the field plate oxide film 16. A drain electrode 20 is provided on the first surface of the N ⁺ type semiconductor substrate 10. The in-trench source electrode 17 and the external source electrode 19 are electrically connected.

Here, the end trench 31 in the end region of the semiconductor device 1a having the above configuration will be described.

When the field plate oxide film 16 in the end trench 31 is divided into the end region side 310 and the cell formation region side 311 centering on the source electrode 17 in the trench, the end region side 310 The field plate oxide film 16 is thicker than the field plate oxide film 16 on the cell formation region side 311.

The thickness of the field plate oxide film 16 on the end region side 310 as described above is not particularly defined. However, in order to obtain the effects described later, the thickness of the field plate oxide film 16 on the end region side 310 is not limited. Increases by about 5% or more of the thickness of the field plate oxide film 16 on the cell formation region side 311 (that is, the field plate oxide film 16 on the cell formation region side 311).
It is desirable that the thickness is 1.05 times or more.

In the present embodiment, the MOSFET structure is described. However, the present invention is not limited to this, and for example, an insulated gate bipolar transistor (hereinafter referred to as IGB).
Even a structure of T) can be implemented. In that case, a P-type collector region is provided between the N ⁺ -type semiconductor substrate 10 and the drain electrode 20.

In the end trench 31, the field plate oxide film 16 on the end region side 310 is provided.
Although the depth of the field plate oxide film 16 on the cell formation region side 311 is shown to be substantially the same, it is not particularly limited.

(Operation of Semiconductor Device 1a)
Next, the operation of the semiconductor device 1a will be described.

The semiconductor device 1a has a MOSFET structure. For example, a positive voltage larger than the threshold voltage is applied to the gate electrode 18 with a positive potential applied to the drain electrode 20 with respect to the external source electrode 19. In this case, an inversion layer is formed on the P-type base layer 12. As a result, the semiconductor device 1a is turned on and an electronic current flows.

This electron current is applied to the N ⁺ type source layer 14, the N type inversion layer (that is, the channel of the semiconductor device 1 a) formed in the P type base region 12, the N type drift layer 11, and the N ⁺ type semiconductor substrate 1.
The current flows from the external source electrode 19 to the drain electrode 20 through 0.

Conversely, by applying zero or a negative voltage to the gate electrode 18, the inversion layer that is an electron path is eliminated, the electron current from the external source electrode 19 is cut off, and the semiconductor device 1 a is turned off ( Reverse bias applied state).

When the semiconductor device 1 a is turned off, the voltage applied between the external source electrode 19 and the drain electrode 20 moves from the interface between the N-type drift layer 11 and the P-type base layer 12 toward the N-type drift layer 11. The depletion layer spreads. Further, the source electrode 17 in the trench has a negative potential with respect to the drain electrode 20, the N-type drift layer 11 has the same potential as the drain electrode 20, and the carriers are mainly electrons. Therefore, since electrons are discharged and depleted near the source electrode 17 in the trench, a depletion layer is formed from the interface between the N-type drift layer 11 and the field plate oxide film 16 (trench 15) toward the N-type drift layer 11 as well. spread. That is, two trenches 1 are formed on the N-type drift layer 11 between the trenches 15 in the cell formation region from the P-type base layer 12 side.
A depletion layer is formed from a total of three directions from the five side surfaces.

By forming the source electrode 18 in the trench 15 through the field plate oxide film 16 in the trench 15 as described above, a depletion layer is formed from three directions with respect to the N-type drift layer 11 as described above, and as a result, the semiconductor The effect that makes it possible to increase the breakdown voltage of the device 1a is called a field plate effect.

On the other hand, the N-type drift layer 11 closer to the end region than the end trench 31 has an end trench 31.
A depletion layer is formed only from the side surface.

As described above, the semiconductor device 1 a operates by switching the on state and the off state by controlling the voltage of the gate electrode 18.

(Manufacturing method of the semiconductor device 1a)
Next, a method for manufacturing the semiconductor device 1a of the first embodiment will be described. (A) of FIG.
FIG. 4C is a cross-sectional view showing a cross-sectional structure for each manufacturing process of the semiconductor device 1a according to the first embodiment.

First, the N type drift layer 1 epitaxially grown on the second surface side of the N ⁺ type semiconductor substrate 10.
1 for photolithography and reactive ion etching (Reactive Ion Etching;
The trench 15 and the sub-trench 30 are formed by RIE. Specifically, a plurality of trenches 15 are formed in the cell formation region, and a plurality of sub-trench 30 adjacent to the trench 15 is provided in the end region.

It should be noted that the length between the trench 15 and the sub-trench 30 in the end region and the length between the sub-trench 30 are smaller than the opening width of the sub-trench 30 in the formation of the field plate oxide film 16 described later. Desirable from a viewpoint. Further, in FIG. 3A, the sub-trench 30 is illustrated as being two, but is merely an example, and the number of sub-trench 30 is not particularly limited.

Next, as shown in FIG. 3B, thermal oxidation is performed to oxidize the trench 15 other than the portion where the in-trench source electrode 17 is formed and the second surface side of the N-type drift layer 11. Then, the field plate oxide film 16 is formed. At this time, the trench 15 in the end region is formed.
And the length between the sub-trench 30, the length between the sub-trench 30, and the sub-trench 30
By appropriately selecting the opening width of the trench 15 and the sub-trench 3 in the end region
Oxidation is also performed including the N-type drift layer 11 between 0 and the sub-trench 30. That is, in the end region, the N-type drift layer 1 is formed such that the field plate oxide film 16 on the end region side 310 is thicker than the field plate oxide film 16 on the cell formation region side 311.
1 is oxidized and an end trench 31 is formed.

Thereafter, the in-trench source electrode 17 is formed in the trench 15 and the end trench 31 by a chemical vapor deposition (CVD) method or the like. As a material of the source electrode 17 in the trench, for example, polysilicon or amorphous silicon is used. For example, phosphorus (P) is implanted into the polysilicon, amorphous silicon, or the like and diffused to form the source electrode 17 in the trench.

After the source electrode 17 in the trench is etched to a predetermined position, the field plate oxide film 16 is etched to a predetermined position and shape, and the source electrode 17 in the trench and the trench side wall surface are thermally oxidized to obtain (c) in FIG. ) Is formed.

Thereafter, polysilicon is deposited, and phosphorus or the like is implanted and diffused to thereby form the gate electrode 1.
8 is formed. After the gate electrode 18 is etched to a predetermined position, boron (B), which is a P-type impurity, is implanted into the second surface side by an ion implantation method, thereby forming the P-type base layer 12. Then, N ⁺ type source layer 14 is formed by selectively injecting N-type impurities such as phosphorus and arsenic (As) into the second surface side by ion implantation.

A part of the field plate oxide film 16 is in contact with the N ⁺ type source layer 14.
A silicon oxide film is formed by CVD or the like, and etching is performed by RIE or the like. Then, P or the like, which is a P-type impurity, is selectively implanted into the second surface side by an ion implantation method.
^{A +} -type contact layer 13 is formed. Then, heat treatment is performed to activate the ion-implanted ions, and finally, the external source electrode 19 is formed on the second surface and the drain electrode 20 is formed on the first surface by sputtering or the like.

  Through the steps as described above, the semiconductor device 1a as shown in FIGS. 1 and 2 is formed.

The manufacturing method described above is merely an example. For example, in addition to the CVD method, an atomic layer deposition (ALD) capable of controlling the growth of a single atomic layer is possible as a film forming method.
Method, sputtering method, physical vapor deposition (PVD) method, coating method,
In addition, the spraying method can be used.

(Effects of the first embodiment)
The effect of the semiconductor device 1a of the first embodiment will be described with reference to a comparative example.

FIG. 4 is a sectional view showing a sectional structure in the end region of the semiconductor device 1b according to the comparative example. The comparative example is different from the first embodiment in that the structure of the end trench 31 of the semiconductor device 1b is the same as that of the trench 15 in the cell formation region. That is, when the field plate oxide film 16 in the end trench 31 is divided into the end region side 310 and the cell formation region side 311 with the in-trench source electrode 17 as the center, The field plate oxide film 16 on the side 310 is provided so that the thickness of the field plate oxide film 16 on the cell formation region side 311 is substantially equal.

The operation of the semiconductor device 1b of the comparative example is the N-type drift layer 11 between the trenches 15 in the cell formation region as described in the operation of the semiconductor device 1a when the reverse bias is applied (in the off state).
In this case, depletion layers are formed from a total of three directions from the P-type base layer 12 side and from the side surfaces of the two trenches 15. On the other hand, in the N-type drift layer 11 on the end region side of the end trench 31, a depletion layer is formed only from the side surface of the end trench 31.

In the N-type drift layer 11 in the cell formation region, a depletion layer easily spreads due to the field plate effect, and electric field concentration at the bottom and side surfaces of the trench 15 can be suppressed. However, the N-type drift layer 11 closer to the end region than the end trench 31 has a depletion layer formed only from the side surface of the end trench 31. Therefore, the depletion layer of the N-type drift layer 11 in the end region is not wider than the cell formation region, and the electric field concentration at the bottom and side surfaces of the end trench 31 is larger than that in the cell formation region.

In general, since the resistivity of a semiconductor is inversely proportional to the carrier concentration (impurity concentration), one method for reducing the resistance is to increase the impurity concentration. Therefore, if the N-type impurity concentration of the N-type drift layer 11 is increased for the purpose of reducing the on-resistance, excessive electric field concentration occurs at the bottom and side surfaces of the end trench 31 when a reverse bias is applied, and the semiconductor device 1b It may lead to destruction. Therefore, in the case of the semiconductor device 1b, the impurity concentration of the N-type drift layer 11 is restricted, and there is a problem that it is difficult to achieve on-resistance.

Here, the magnitude of the voltage that can be borne by the oxide film is determined by the product of the magnitude of the electric field applied to the oxide film and the thickness of the oxide film. Therefore, in the case of the semiconductor device of the first embodiment, the end trench 3
1, the field plate oxide film 16 on the end region side 310 is made thicker than the field plate oxide film 16 on the cell formation region side 311, thereby increasing the potential difference larger than that of the semiconductor device 1 b. 16 can bear. As a result, the electric field applied to the N-type drift layer 11 in the end region when a reverse bias is applied can be relaxed.

Therefore, according to the semiconductor device 1a of the first embodiment, since the electric field applied to the N-type drift layer 11 in the end region can be relaxed, the N-type impurity concentration of the N-type drift layer 11 is increased. Thus, it is possible to realize a low on-resistance of the semiconductor device 1a.

In addition, in order to obtain the effect of relaxing the electric field concentration applied to the end trench 31 described above,
The thickness of the field plate oxide film 16 on the end region side 310 is about 5% or more larger than the thickness of the field plate oxide film 16 on the cell formation region side 311 (that is, the field plate oxide film on the cell formation region side 311). It is desirable that it is 1.05 times the thickness of 16).

[Second Embodiment]
Hereinafter, the second embodiment will be described with reference to FIG. In addition, about 2nd Embodiment, description is abbreviate | omitted about the point similar to 1st Embodiment, and a different point is demonstrated.

(Structure of the semiconductor device 1c)
The structure of the semiconductor device 1c according to the second embodiment will be described with reference to FIG.
FIG. 5 is a cross-sectional view showing a cross-sectional structure in the end region of the semiconductor device 1c according to the second embodiment.

The semiconductor device 1c is different from the semiconductor device 1a of the first embodiment in that a floating electrode 40 (fourth electrode) adjacent to the in-trench source electrode 17 in the end trench 31 is provided. Specifically, the floating electrode 40 is provided adjacent to the end region side of the in-trench source electrode 17 in the end trench 31 of the semiconductor device 1a of the first embodiment. The floating electrode 40 is made of, for example, polysilicon and is not electrically connected to the outside. In FIG. 5, only one floating electrode 40 is shown.
The number is not limited, and a plurality may be provided.

The other structure is the same as that of the semiconductor device 1a of the first embodiment, and the MOSFE.
It has a T structure.

Although the MOSFET structure has been described in the second embodiment, the present invention is not limited to this, and the present invention can be implemented even with an IGBT structure, for example. In that case, a P-type collector region is provided between the N ⁺ -type semiconductor substrate 10 and the drain electrode 20.

(Operation of Semiconductor Device 1c)
The operation of the semiconductor device 1c is the same as that of the semiconductor device 1a.

When only the semiconductor device 1c is in operation (ON state), first, the external source electrode 19
On the other hand, a positive voltage larger than the threshold voltage is applied to the gate electrode 18 with a positive potential applied to the drain electrode 20. In this case, an inversion layer is formed on the P-type base layer 12. Thereby, the semiconductor device 1c is turned on and an electronic current flows.

This electron current is generated by the N ⁺ type source layer 14, the N type inversion layer (that is, the channel of the semiconductor device 1 c) formed in the P type base region 12, the N type drift layer 11, and the N ⁺ type semiconductor substrate 1.
The current flows from the external source electrode 19 to the drain electrode 20 through 0.

As described above, the semiconductor device 1c also operates by switching the ON state and the OFF state by controlling the voltage of the gate electrode 18.

(Method for Manufacturing Semiconductor Device 1c)
The manufacturing method of the semiconductor device 1c is substantially the same as the manufacturing method of the semiconductor device 1a, but includes a process for forming the floating electrode 40.

Specifically, in the same manner as in the method for manufacturing the semiconductor device 1a as shown in FIG. 3A, the N-type drift layer 11 epitaxially grown on the second surface side of the N ⁺ type semiconductor substrate 10 is subjected to photolithography and The trench 15 and the sub-trench 30 are formed by the RIE method.
In order to form the floating electrode 40, the opening width of the sub-trench 30 is provided to be wider than that of the first embodiment. That is, the sub-trench 30 is opened so as not to be completely embedded in the field plate oxide film 16 by thermal oxidation.

Then, after the field plate oxide film 16 is formed by thermal oxidation, the floating electrode 40 is formed using, for example, polysilicon or the like, similarly to the source electrode 17 in the trench. Thereafter, in the same manner as in the method for manufacturing the semiconductor device 1a, the P ⁺ -type contact layer 13, the N ⁺ -type source layer 14, the gate electrode 18, the external source electrode 19, and the drain electrode 20 are formed, thereby forming the semiconductor device 1c.

Regarding the film forming method of the manufacturing method of the second embodiment, in addition to the CVD method, an atomic layer growth ALD method capable of controlling the growth of a single atomic layer, a sputtering method, a physical vapor deposition PVD method, a coating method, In addition, the spraying method can be used.

(Effect of the semiconductor device 1c)
The effect of the semiconductor device 1c will be described.

Also in the semiconductor device 1c, it is possible to obtain the same effect as the semiconductor device 1a. That is, by providing the floating electrode 40 on the end region side 310 in the end trench 31, the potential difference larger than that in the semiconductor device 1 b is increased.
Can bear. As a result, the electric field applied to the N-type drift layer 11 in the end region when a reverse bias is applied can be relaxed.

Therefore, according to the semiconductor device 1c of the second embodiment, since the electric field applied to the N-type drift layer 11 in the end region can be relaxed, the N-type impurity concentration of the N-type drift layer 11 is increased. Thus, it is possible to reduce the on-resistance of the semiconductor device 1c.

Further, in the case of the semiconductor device 1 c, by providing the floating electrode 40 adjacent to the in-trench source electrode 17 in the end trench 31, it is possible to gradually add a potential difference on the side surface on the end region side of the end trench 31. Thus, the electric field concentration can be further suppressed.

If the field plate oxide film 16 on the end region side 310 of the end trench 31 is made too thick as in the case of the semiconductor device 1a, the N ⁺ type semiconductor is manufactured at the time of manufacturing the semiconductor device. The stress applied to the substrate 10 increases, leak current and N
There is a possibility that a manufacturing problem or the like may occur due to warpage of the ⁺ type semiconductor substrate 10. Semiconductor device 1c
Since the floating electrode 40 adjacent to the in-trench source electrode 17 of the end trench 31 is provided, the above-described problems can be suppressed.

[Third Embodiment]
The third embodiment will be described below with reference to FIG. In addition, about 3rd Embodiment, description is abbreviate | omitted about the point similar to 1st Embodiment, and a different point is demonstrated.

(Structure of the semiconductor device 1d)
The structure of the semiconductor device 1d according to the third embodiment will be described with reference to FIG.
FIG. 6 is a sectional view showing a sectional structure in the end region of the semiconductor device 1d according to the third embodiment.

The semiconductor device 1d is different from the semiconductor device 1a of the first embodiment in that the depth of the floating electrode 40 (the length of the floating electrode 40 in the first surface direction from the second surface of the N ⁺ type semiconductor substrate 10) is different. This is a point deeper than the source electrode 17 in the trench. In addition,
Although FIG. 6 shows that one floating electrode 40 is formed, the present invention can be implemented even when a plurality of floating electrodes 40 are provided.

The other structure is the same as that of the semiconductor device 1a of the first embodiment, and the MOSFE.
It has a T structure.

In the third embodiment, the MOSFET structure has been described. However, the present invention is not limited to this. For example, an IGBT structure can be used. In that case, a P-type collector region is provided between the N ⁺ -type semiconductor substrate 10 and the drain electrode 20.

(Operation of Semiconductor Device 1d)
The operation of the semiconductor device 1d is the same as that of the semiconductor device 1a.

To describe only the operation (on state) of the semiconductor device 1d, first, the external source electrode 19
On the other hand, a positive voltage larger than the threshold voltage is applied to the gate electrode 18 with a positive potential applied to the drain electrode 20. In this case, an inversion layer is formed on the P-type base layer 12. Thereby, the semiconductor device 1d is turned on, and an electronic current flows.

This electron current is generated by the N ⁺ type source layer 14, the N type inversion layer (that is, the channel of the semiconductor device 1 d) formed in the P type base region 12, the N type drift layer 11, and the N ⁺ type semiconductor substrate 1.
The current flows from the external source electrode 19 to the drain electrode 20 through 0.

As described above, the semiconductor device 1d also operates by switching the on state and the off state by controlling the voltage of the gate electrode 18.

(Method for Manufacturing Semiconductor Device 1d)
The manufacturing method of the semiconductor device 1d is substantially the same as the manufacturing method of the semiconductor device 1a, but the floating electrode 40 is formed so that the depth of the floating electrode 40 is deeper than the source electrode 17 in the trench.

Specifically, in the same manner as in the method for manufacturing the semiconductor device 1a as shown in FIG. 3A, the N-type drift layer 11 epitaxially grown on the second surface side of the N ⁺ type semiconductor substrate 10 is subjected to photolithography and The trench 15 and the sub-trench 30 are formed by the RIE method. At this time, at least one or more of the sub-trench 30 in the end region is formed to be deeper than the trench 15. Further, in order to form the floating electrode 40, the opening width of the sub-trench 30 is formed to be wider than the opening width of the semiconductor device 1a.

Then, after the field plate oxide film 16 is formed by thermal oxidation, the source electrode 17 in the trench is formed using, for example, polysilicon. Thereafter, similarly to the method for manufacturing the semiconductor device 1a, the P ⁺ -type contact layer 13, the N ⁺ -type source layer 14, the gate electrode 18, the external source electrode 19, and the drain electrode 20 are formed, thereby forming the semiconductor device 1d.

Regarding the film forming method of the manufacturing method of the third embodiment, in addition to the CVD method, an atomic layer growth ALD method capable of controlling the growth of a single atomic layer, a sputtering method, a physical vapor deposition PVD method, a coating method, In addition, the spraying method can be used.

(Effect of the semiconductor device 1d)
The effect of the semiconductor device 1d will be described.

Also in the semiconductor device 1d, it is possible to obtain the same effect as that of the semiconductor device 1a. That is, by providing the floating electrode 40 on the end region side 310 in the end trench 31, the potential difference larger than that in the semiconductor device 1 b is increased.
Can bear. As a result, the electric field applied to the N-type drift layer 11 in the end region when a reverse bias is applied can be relaxed.

Therefore, according to the semiconductor device 1d of the third embodiment, since the electric field applied to the N-type drift layer 11 in the end region can be relaxed, the N-type impurity concentration of the N-type drift layer 11 is increased. Thus, it is possible to realize a low on-resistance of the semiconductor device 1d.

Further, in the case of the semiconductor device 1d, by providing the floating electrode 40 adjacent to the in-trench source electrode 17 in the end trench 31, it is possible to gradually apply a potential difference on the side surface of the end trench 31 on the end region side. Thus, the electric field concentration can be further suppressed.

If the field plate oxide film 16 on the end region side 310 of the end trench 31 is made too thick as in the case of the semiconductor device 1a, the N ⁺ type semiconductor is manufactured at the time of manufacturing the semiconductor device. The stress applied to the substrate 10 increases, leak current and N
There is a possibility that a manufacturing problem or the like may occur due to warpage of the ⁺ type semiconductor substrate 10. Semiconductor device 1d
Since the floating electrode 40 adjacent to the in-trench source electrode 17 of the end trench 31 is provided, the above-described problems can be suppressed.

In addition, by providing the floating electrode 40 deeper than the in-trench source electrode 17 as in the semiconductor device 1d, the floating electrode is formed so as to cover the source electrode, thereby reducing the electric field on the trench bottom side. can do. That is, the source potential is shielded, and the electric field concentration at the bottom and side surfaces of the end trench 31 can be further reduced.

Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions can be made without departing from the spirit of the invention.
Can be replaced or changed. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and the equivalents thereof.

DESCRIPTION OF SYMBOLS 1a, 1b, 1c ... Semiconductor device, 10 ... N ^<+> type | mold semiconductor substrate (semiconductor substrate), 11 ... N type drift layer (1st semiconductor region), 12 ... P type base layer (2nd semiconductor region), 13 ... P Type contact layer (third semiconductor region), 14 ... N ⁺ type source layer (fourth semiconductor region), 15 ... trench (first trench), 16 ... field plate oxide film (insulating film), 17 ... source electrode in trench (Second electrode), 18 ... gate electrode, 19 ... external source electrode (third electrode), 20 ...
Drain electrode (first electrode), 30 ... sub-trench (second trench), 31 ... end trench (first trench), 40 ... floating electrode (fourth electrode), 310 ... end region side, 31
1 ... cell formation region side

Claims (12)

A semiconductor substrate having a first surface, a second surface, and a first semiconductor region of a first conductivity type;
A first electrode provided on the first surface;
A second semiconductor region of a second conductivity type provided on the second surface side;
A third semiconductor region of a second conductivity type provided on the second surface so as to be in contact with the second semiconductor region;
A fourth semiconductor region of a first conductivity type in contact with the third semiconductor region and selectively provided on the second surface;
A first trench provided in a cell formation region and an end region so as to reach the first semiconductor region from the first surface;
Among the insulating films provided in the first trench in the end region, the insulating film on the end region side is provided in the first trench so that the insulating film on the cell forming region side is thicker. An insulating film;
A second electrode provided in the first trench via the insulating film;
A third electrode provided on the second surface;
A semiconductor device. 2. The thickness of the insulating film on the end region side in the first trench in the end region is 1.05 times or more the thickness of the insulating film on the cell formation region side. Semiconductor device. 3. The semiconductor device according to claim 1, wherein in the first trench in the end region, a fourth electrode adjacent to the second electrode is provided on the end region side. 4. The semiconductor device according to claim 1, wherein a depth of the first trench in the end region becomes deeper toward the end region side. 5.   The semiconductor device according to claim 3, wherein the fourth electrode is deeper than the second electrode. In the first trench in the end region, the insulating film on the end region side and the fourth trench
6. The semiconductor device according to claim 3, wherein the sum of the thicknesses of the electrodes is 1.05 times or more of the thickness of the insulating film on the cell formation region side. Forming a first electrode on the first surface of the semiconductor substrate having a first surface, a second surface, and a first conductivity type first semiconductor region;
Forming a second conductive type second semiconductor region on the second surface side;
Forming a second conductivity type third semiconductor region on the second surface so as to be in contact with the second semiconductor region;
Selectively forming a fourth semiconductor region of the first conductivity type on the second surface so as to be in contact with the third semiconductor region;
Forming a first trench reaching the first semiconductor region from the first surface in a cell formation region and an end region;
Forming a second trench adjacent to the first trench in the end region, having a trench width smaller than the first trench and reaching the first semiconductor region from the first surface;
Forming an insulating film in the first trench and the second trench, and integrating the insulating films of the first trench and the second trench in the end region by heat treatment;
In the first trench in the end region, a second electrode is formed in the insulating film so that the insulating film on the end region side is thicker than the insulating film on the cell formation region side. Process,
Forming a third electrode on the second surface;
A method for manufacturing a semiconductor device comprising: The thickness of the insulating film on the end region side in the first trench in the end region is not less than 1.05 times the thickness of the insulating film on the cell formation region side. A method for manufacturing a semiconductor device. At least one of the second trenches is formed in the end region by the heat treatment.
The method further comprises forming a fourth electrode in the second trench in which the insulating film is not formed after the trench and the second trench are formed so as not to be integrated.
Or a method of manufacturing a semiconductor device according to 8; The method for manufacturing a semiconductor device according to claim 7, wherein a depth of the first trench in the end region becomes deeper toward the end region side. The method of manufacturing a semiconductor device according to claim 9, wherein the fourth electrode is formed deeper than the second electrode. The sum of the thicknesses of the insulating film and the fourth electrode on the end region side is 1.05 times or more the thickness of the insulating film on the cell formation region side. The manufacturing method of the semiconductor device as described in any one of Claims 1-3.

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