WO2021232801A1

WO2021232801A1 - Igbt device and manufacturing method therefor

Info

Publication number: WO2021232801A1
Application number: PCT/CN2020/140131
Authority: WO
Inventors: 方冬; 肖魁; 卞铮; 胡金节
Original assignee: 华润微电子（重庆）有限公司
Priority date: 2020-05-18
Filing date: 2020-12-28
Publication date: 2021-11-25
Also published as: CN113690293B; CN113690293A

Abstract

An IGBT device and a manufacturing method therefor. Said device comprises: a drift region (100); a body region (110) formed in the drift region (100); a first doped region (111) and a second doped region (112) formed in the body region (110); a trench, sequentially penetrating through the first doped region (111) and the body region (110) and extending into the drift region (100); a filling structure, comprising an oxide layer (121) formed on the inner wall of the trench, and a first conductive structure (122) and a second conductive structure (123) which are filled in the trench and are isolated from each other, the depth of the bottom of the first conductive structure (122) being greater than the depth of the bottom of the second conductive structure (123); an extension region (130), formed in the drift region (100) under the trench and surrounding the bottom of the trench; an emitter lead-out structure (310), being in contact with the first doped region (111) and the second doped region (112); and a gate lead-out structure, being in contact with the second conductive structure (123), the drift region (100) and the first doped region (111) having a first conductive type, and the body region (110), the second doped region (112) and the extension region (130) having a second conductive type.

Description

IGBT device and preparation method thereof

Cross-references to related applications

This application claims the priority of a Chinese patent application filed with the Chinese Patent Office with the application number 2020104184762 and the invention title "IGBT device and its preparation method" on May 18, 2020, the entire content of which is incorporated into this application by reference.

Technical field

This application relates to the field of semiconductors, and in particular to an IGBT device and a preparation method thereof.

Background technique

The statements here only provide background information related to this application, and do not necessarily constitute prior art.

IGBT (Insulated Gate Bipolar Transistor, insulated gate bipolar transistor) device is a bipolar device, which combines MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor, metal oxide semiconductor field effect transistor) and bipolar transistor. The working mechanism has the advantages of reduced conduction voltage, high pressure resistance and low power consumption. However, limited by the excess carriers in the drift region during the on-state, the switching speed of the IGBT device is slower.

Summary of the invention

Based on this, it is necessary to propose a new IGBT device and its preparation method for the current technical problem of the slow switching speed of IGBT devices.

An IGBT device including:

The drift zone has the first conductivity type;

The body region is formed in the drift region and has the second conductivity type;

The first doped region is formed in the body region and has the first conductivity type;

A second doped region formed in the body region and has a second conductivity type, and the doping concentration of the second doping region is greater than the doping concentration of the body region;

A trench sequentially penetrates the first doped region and the body region and extends to the drift region, and the second doped region is spaced apart from the trench;

The filling structure includes an oxide layer formed on the inner wall of the trench and a first conductive structure and a second conductive structure filled in the trench and isolated from each other. The bottom depth of the first conductive structure is greater than that of the second conductive structure. The depth of the bottom of the conductive structure;

An extension region, formed in the drift region under the trench and surrounding the bottom of the trench, having a second conductivity type, and the extension region is isolated from the first conductive structure by the oxide layer;

An emitter lead-out structure in contact with the first doped region and the second doped region; and

The gate lead structure is in contact with the second conductive structure.

An IGBT device preparation method, including:

Forming a drift region on the semiconductor substrate, opening a trench on the drift region, and forming an oxide layer on the inner wall of the trench, the drift region having the first conductivity type;

Forming an extension area in the drift zone below the trench, the extension area having the second conductivity type and surrounding the bottom of the trench;

Filling the trench with a first conductive structure and a second conductive structure that are isolated from each other, and the bottom depth of the first conductive structure is greater than the bottom depth of the second conductive structure;

Doping the drift region with the second conductivity type to form a body region, the body region is in contact with the inner wall of the trench, and the depth of the body region is smaller than the depth of the trench; and

The body region is doped with the first conductivity type and the second conductivity type respectively to form a first doped region and a second doped region. The first doped region is in contact with the trench, so The doping concentration of the second doping region is greater than the doping concentration of the body region, forming an emitter lead-out structure in contact with the first doping region and the second doping region, and forming a contact with the first doping region. The gate lead-out structure in contact with the two conductive structures.

The details of one or more embodiments of the present application are set forth in the following drawings and description. Other features, purposes and advantages of this application will become apparent from the description, drawings and claims.

Description of the drawings

Figure 1a is a partial side sectional view of an IGBT device in a cell area in an embodiment of the application;

Figure 1b is a partial side sectional view of an IGBT device outside the cell area in another embodiment of the application;

FIG. 2 is a flowchart of steps of a method for manufacturing an IGBT device in an embodiment of the application;

3a to 3h are structural cross-sectional views corresponding to relevant steps of the IGBT device manufacturing method in an embodiment of the application.

Label description

100 drift region; 110 body region; 111 first doped region; 112 second doped region; 121 oxide layer; 122 first conductive structure; 123 second conductive structure; 124 isolation structure; 130 expansion region; 140 buffer zone; 150 collector area; 200 interlayer dielectric layer; 310 emitter extraction structure; 320 emitter connection structure.

Detailed ways

As shown in FIG. 1a, the IGBT device includes a drift region 100 of the first conductivity type. The drift region 100 is formed on a semiconductor substrate. The drift region 100 may be formed by epitaxial growth of the semiconductor substrate. A body region 110 of the second conductivity type is formed on the upper surface of the drift region 100. A first doped region 111 and a second doped region 112 are formed in the body region 110. The first doped region 111 has a first conductivity type, the second doped region 112 has a second conductivity type, and the second doped region 112 has a second conductivity type. The doping concentration of the doping region 112 is greater than the doping concentration of the body region 110, and the first doping region 111 and the second doping region 112 are in contact with each other.

The first doped region 111 is provided with a trench that penetrates the first doped region 111 and the body region 110 and extends into the drift region 100, that is, the bottom end of the trench is located in the drift region 100, and the trench and the second doped region The zones 112 are arranged at intervals. The trench is filled with a filling structure, and the filling structure includes an oxide layer 121 formed on the inner wall of the trench, a first conductive structure 122 and a second conductive structure 123 that are isolated from each other. In the same trench, the extension depth of the first conductive structure 122 is greater than the extension depth of the second conductive structure 123, that is, the distance between the first conductive structure 122 and the bottom of the trench is smaller than the distance between the second conductive structure 123 and the bottom of the trench. Specifically, the oxide layer 121 is divided into an isolation oxide layer 121a and a gate oxide layer 121b. The oxide layer located between the first conductive structure 122 and the inner wall of the trench is the isolation oxide layer 121a, which is located between the second conductive structure 123 and the trench. The oxide layer between the inner walls is the gate oxide layer 121b. Specifically, the first conductive structure 122 and the second conductive structure 123 may be polysilicon. An expansion region 130 is also formed in the drift region 100. The expansion region 130 is located under the trench and surrounds the bottom of the trench. The expansion region 130 has the second conductivity type. The expansion region 130 is isolated from the first conductive structure 122 by the oxide layer 121.

The IGBT device further includes an emitter lead-out structure 310 and a gate lead-out structure (not shown in the figure). The emitter lead-out structure 310 and the gate lead-out structure may be metal pillars, and specifically may be tungsten metal. Wherein, the emitter lead structure 310 is in contact with the first doped region 111 and the second doped region 112, and the gate lead structure is in contact with the second conductive structure 123 in the trench.

Wherein, the first conductivity type is N type, and the second conductivity type is P type; or, the first conductivity type is P type, and the second conductivity type is N type.

It is understandable that the front side of the above-mentioned IGBT device should also have an emitter metal layer and a gate metal layer which are isolated from each other. The above-mentioned emitter extraction structures 310 are all connected to the emitter metal layer, and the above-mentioned gate extraction structures are all connected to the gate metal layer. connect. It can be understood that the IGBT device further includes a buffer region 140 isolated from the body region and a collector region 150 in contact with the buffer region 140.

In the above-mentioned IGBT device, the oxide layer located between the second conductive structure 123 and the sidewall of the trench is the gate oxide layer 121b, and the gate oxide layer 121b and the second conductive structure 123 inside the trench form a trench gate structure. Voltage, a conduction channel is formed in the body region 110 on both sides of the trench, so as to provide a drift region current for the drift region 100 to turn on the IGBT. At the same time, a first conductive structure 122 is also formed at the bottom of the trench. The first conductive structure 122 and the isolation oxide layer 121a in the drift region 100 form an internal field plate, which can adjust the electric field distribution in the drift region 100 to make it compatible with the internal field plate. The contact drift region forms a depletion region, which improves the device withstand voltage level. At the same time, forming the first conductive structure 122 at the bottom of the trench can also reduce the switching capacitance of the IGBT device and reduce the turn-on voltage drop of the device. Since the extended region 130 is also formed in the drift region 100, the extended region 130 surrounds the bottom of the trench and the conductivity type is opposite to that of the drift region 100. When the IGBT device changes from the on state to the off state, the extended region 130 and the drift region 100 carry residual current Sub-combination speeds up the switching speed. In addition, by forming the expansion region 130, the problem of electric field concentration at the bottom of the trench can be solved. When the device is reverse withstand voltage, the breakdown position can be transferred from the trench to the interface between the expansion region 130 and the drift region 100.

Wherein, the first conductive structure 122 may be a floating structure, or may be electrically connected to the emitter to obtain the emitter potential. In one embodiment, as shown in FIG. 1b, outside the cell area, the first conductive structure 122 is drawn from the end of the trench, that is, at the end of the trench, the first conductive structure 122 extends to the top of the trench and is located at the top of the trench. The emitter connection structure 320 contacts to obtain the emitter potential, thereby enhancing the ability of the inner field plate and the expansion region 130 to adjust the electric field. In another embodiment, the first conductive structure 122 is a floating structure, the first conductive structure 122 is drawn from the end of the trench, the first conductive structure 122 is not in contact with the emitter connection structure 320, and there is a certain amount between the two. Thickness of the interlayer dielectric layer 200, but the first conductive structure 122 can obtain the induced potential of the emitter, so that the first conductive structure 122 is charged, and since the electrical connection with the emitter is achieved through induction, the emitter can be cut off , The leakage path of the first conductive structure avoids the leakage of the emitter. In another embodiment, the first conductive structure 122 is a floating structure and is not electrically connected to the emitter, and the potential of the emitter cannot be obtained. Therefore, the first conductive structure 122 is not charged.

In one embodiment, as shown in FIG. 1 a, the second doped region 112 is located in the body region 110 at the bottom of the first doped region 111, and the second doped region 112 may be in contact with the first doped region 111. In this structure, the emitter extraction structure 310 can penetrate the first doped region 111 from the top of the structure and extend into the second doped region 112 to realize the emitter and the first doped region 111 and the second doped region 112 Electrical connection. Further, the width of the second doped region 112 is greater than the width of the emitter lead-out structure 310, the emitter lead-out structure 310 extends into the second doped region 112, and the bottom of the emitter lead-out structure 310 is surrounded by the second doped region 112 , In order to reduce the contact resistance between the emitter lead structure 310 and the body region 110.

In an embodiment, as shown in FIG. 1a, an interlayer dielectric layer 200 is further formed on the first doped region 111 and the trench, and the interlayer dielectric layer 200 may specifically be silicon oxide. The emitter extraction structure 310 penetrates the interlayer dielectric layer 200 and the first doped region 111 on the one hand and extends into the second doped region 112 so as to be in contact with the first doped region 111 and the second doped region. The aspect also penetrates the interlayer dielectric layer 200 and contacts the first conductive structure 122 in the trench. The gate lead structure is formed directly above the trench, which penetrates the interlayer dielectric layer 200 and contacts the second conductive structure 123 in the trench. Further, the gate lead-out structure and the emitter lead-out structure are staggered so as to be connected to the gate metal layer and the emitter metal layer respectively.

Specifically, the distribution of the first conductive structure 122 and the second conductive structure 123 in the trench has various designs.

In one embodiment, as shown in FIG. 1a, in the trench, the first conductive structure 122 is distributed at the bottom of the trench, the second conductive structure 123 is distributed at the top of the trench, and the first conductive structure 122 and the second conductive structure 122 are distributed on the top of the trench. The conductive structures 123 are isolated by an isolation structure 124, wherein an oxide layer 121 is formed between the first conductive structure 122 and the inner wall of the trench and between the second conductive structure 123 and the inner wall of the trench. Specifically, the oxide layer located between the first conductive structure 122 and the inner wall of the trench is an isolation oxide layer 121a, and the oxide layer located between the second conductive structure 123 and the inner wall of the trench is a gate oxide layer 121b. Specifically, the isolation structure 124 is silicon oxide. In this embodiment, the first conductive structure 122 at the bottom of the trench can not only adjust the electric field of the drift region, enhance the depletion of the drift region, but also reduce the switching capacitance and improve the performance of the device. Further, as shown in FIG. 1a, in the trench, the top surface of the first conductive structure 122 and the bottom surface of the second conductive structure 123 are approximately flat surfaces. In another embodiment, in the trench, the middle of the top surface of the first conductive structure 122 bulges outward, and the middle of the bottom surface of the second conductive structure 123 is recessed inward to match the bulge of the first conductive structure 122 .

In another embodiment, in the trench, the first conductive structure 122 extends from the top of the trench to the bottom of the trench, and an oxide layer 121 is formed between the first conductive structure 122 and the inner wall of the trench, and the second conductive structure 123 Formed in the oxide layer 121 on both sides of the first conductive structure 122, the first conductive structure 122 and the second conductive structure 123 are separated by the oxide layer 121, and the depth of the first conductive structure 122 extending toward the bottom of the trench is greater than that of the second conductive structure 123 The depth extending to the bottom of the trench. In this embodiment, the second conductive structure 123 is disposed in the oxide layer 121 to increase the thickness of the oxide layer 121, thereby enhancing the withstand voltage of the device.

In one embodiment, as shown in FIG. 1a, the buffer area 140 of the aforementioned IGBT device is formed on the side of the drift region 100 away from the body region 110, and the collector region 150 is formed on the side of the buffer area 140 away from the drift region 140. The region 140 has the first conductivity type and the doping concentration of the buffer zone 140 is greater than the doping concentration of the drift region 100. The collector region has the second conductivity type, thereby forming a vertical channel IGBT device and increasing the conduction current.

Since the expansion region 130 and the body region 110 have the second conductivity type, the drift region 100 has the first conductivity type. The expansion region 130, the body region 110, and the drift region 100 sandwiched between the two form a junction field effect transistor. The existence of the type field effect transistor will limit the channel current. Therefore, in one embodiment, increasing the doping concentration of the drift region above the extension region 130 can reduce the influence of the junction field effect transistor and increase the channel current.

In the above IGBT device, by forming a trench and filling the first conductive structure and the second conductive structure in the trench, and at the same time forming an expansion area surrounding the bottom of the trench at the bottom of the trench, the switching capacitance of the IGBT device and the conduction of the device can be reduced. Voltage drop, and solve the problem of electric field concentration at the bottom of the trench, and improve the reliability of the device.

This application also relates to a method for manufacturing an IGBT device. As shown in FIG. 2, the manufacturing method includes the following steps:

Step S210: forming a drift region on the semiconductor substrate, opening a trench on the drift region, and forming an oxide layer on the inner wall of the trench, the drift region having the first conductivity type.

As shown in FIG. 3a, the drift region 100 of the first conductivity type is formed on the semiconductor substrate. Specifically, an epitaxial layer is grown on the semiconductor substrate and the epitaxial layer is doped with the first conductivity type to form the drift region 100. After the drift region 100 is formed, a hard mask is formed on the drift region 100, an etching window is defined by the hard mask, the drift region 100 is etched, and a trench is opened on the drift region 100. An oxide layer 121 is formed on the inner wall of the trench. Specifically, the oxide layer 121 may be formed on the inner wall of the trench by a thermal oxidation process. At this time, the oxide layer 121 covers the inner wall and bottom of the trench.

Step S220: forming an extension area in the drift zone below the trench, the extension area having the second conductivity type and surrounding the bottom of the trench.

As shown in FIG. 3b, with the hard mask as a barrier layer, the second conductivity type ion implantation is performed on the drift region 100 below the trench through the trench, and an expansion region 130 is formed in the drift region 100 below the trench. Surround the bottom of the trench.

Step S230: Fill the trench with a first conductive structure and a second conductive structure that are isolated from each other, and the bottom depth of the first conductive structure is greater than the bottom depth of the second conductive structure.

In an embodiment, step S330 specifically includes:

Step S231: Fill the trench with a first conductive structure, etch the first conductive structure and the oxide layer at the top of the trench, and retain the first conductive structure and the oxide layer at the bottom of the trench.

As shown in FIG. 3c, the first conductive structure is filled into the trench by a deposition process, and the first conductive structure and oxide layer on the top of the trench are etched away by an etch-back process, exposing the first conductive structure 122 and the oxide layer at the bottom of the trench. Oxide layer 121.

Step S232: forming an isolation structure in the trench, the isolation structure covering the first conductive structure at the bottom of the trench and not filling the trench.

Specifically, as shown in FIG. 3d, an isolation structure 124 is formed in the trench. Specifically, the isolation structure may be filled in the trench by a deposition process, and then a part of the isolation structure at the top of the trench is etched back, leaving the isolation structure 124 at the bottom. In an embodiment, the isolation structure may be silicon oxide, and the hard mask may be silicon oxide or silicon nitride. During the etching of the isolation structure, the hard mask is also removed.

Step S233: forming an oxide layer on the inner wall of the trench above the isolation structure and filling the trench with a second conductive structure.

As shown in FIG. 3e, continue to form an oxide layer on the inner wall of the trench above the isolation structure 124 and fill the second conductive structure 123 in the trench. At this time, the oxide layer located between the first conductive structure 122 and the inner wall of the trench To isolate the oxide layer 121a, the oxide layer located between the second conductive structure 123 and the inner wall of the trench is the gate oxide layer 121b.

Through step S331 to step S333, a filling structure is formed in the trench. Since the extension area 130 is isolated from the first conductive structure 122, the leakage path from the first conductive structure 122 to the extension area 130 is cut off, and the leakage can be reduced.

Step S240: Doping the drift region with the second conductivity type to form a body region, the body region is in contact with the trench, and the depth of the body region is smaller than the depth of the trench.

As shown in FIG. 3f, the upper surface layer of the drift region 100 is doped with the second conductivity type to form the body region 110, the body region 100 and the trench structure, and the depth of the body region 110 is less than the depth of the trench. Through the trench gate, a conduction channel can be formed in the body region 110 on both sides of the trench.

In an embodiment, the process of forming the body region 110 is a high-temperature push-well process, wherein the temperature and time of the high-temperature push-well can be adjusted according to the doping depth and doping concentration of the body region. Specifically, the temperature range of the high-temperature push-well It can be controlled between 900 ℃ and 1200 ℃, and the time range of high temperature pushing trap can be controlled between 10 min and 180 min. While pushing the well at high temperature, the doped ions in the expansion region 130 diffuse outward, so that the expansion region 130 expands outward, thereby increasing the volume of the expansion region 130.

In one embodiment, after step S330 and before step S340, the method further includes: doping the drift region with the first conductivity type to increase the doping concentration of the drift region 100 to increase the on-current of the IGBT device .

Step S250: Doping the body region with the first conductivity type and the second conductivity type respectively to form a first doped region and a second doped region, the first doped region and the trench Contact, the doping concentration of the second doping region is greater than the doping concentration of the body region, forming an emitter extraction structure in contact with the first doping region and the second doping region, and forming a The gate lead-out structure contacted by the second conductive structure.

In a specific embodiment, step S250 specifically includes:

Step S251: Doping the upper surface layer of the body region with the first conductivity type to form a first doped region.

As shown in FIG. 3f, the upper surface layer of the body region 110 is doped with the first conductivity type, and a first doped region 111 is formed on the upper surface layer of the body region 110.

Step S252: forming an interlayer dielectric layer covering the first doped region and the trench on the first doped region, and openings sequentially penetrate the interlayer dielectric layer and the first doped region and extend to The emitter contact hole in the body region is provided with a gate contact hole penetrating the interlayer dielectric layer.

As shown in FIG. 3g, the interlayer dielectric layer 200 covering the first doped region 111 and the trench is continuously formed on the first doped region 111. The interlayer dielectric layer 200, the first doped region 111 and part of the body region 110 are sequentially etched to form an emitter contact hole that sequentially penetrates the interlayer dielectric layer 200, the first doped region 111 and extends into the body region 110, passing through The emitter contact hole may expose the body region 110. It can be understood that when the emitter contact hole is formed, a gate contact hole (not shown in the figure) is also formed. The gate contact hole penetrates the interlayer dielectric layer 200 and exposes the second conductive structure 123.

Step S253: Doping the body region with the second conductivity type through the emitter contact hole to form a second doped region.

After the emitter contact hole is formed, the body region 110 can be exposed through the emitter contact hole, and the body region is doped through the emitter contact hole, and a second doped region 112 can be formed in the body region at the bottom of the emitter contact hole. .

Step S254: Fill the emitter contact hole with a conductive material to form an emitter lead-out structure, and fill the gate contact hole with a conductive material to form a gate lead-out structure.

Continuing to refer to FIG. 3g, the emitter contact hole is filled with conductive material to form an emitter lead-out structure 310 that is in contact with the first doped region 111 and the second doped region 112. It can be understood that while the emitter contact hole is filled with conductive material, the gate contact hole is also filled with conductive material to form a gate lead structure (not shown in the figure).

It is understandable that the IGBT device also includes a buffer zone and a collector area, therefore, in addition to the above steps, a step of forming a buffer zone and collector area should also be included.

In an embodiment, after step S250, the method further includes:

Step S260: forming a first conductivity type buffer zone on the side of the substrate away from the body region, and forming a second conductivity type collector region on the side of the buffer zone away from the body region.

As shown in FIG. 3h, a first conductivity type buffer zone 140 is formed on the side of the drift region away from the body region 110, and a second conductivity type collector region is formed on the side of the buffer zone 140 away from the body region 110, thereby forming a vertical trench Road of IGBT devices.

It can be understood that, as shown in FIG. 3h, the IGBT device further includes an emitter metal layer and a gate metal layer on the top surface and a collector metal layer on the bottom surface.

The above IGBT device preparation method, forming a trench gate structure and forming an expansion region 130 surrounding the bottom of the trench in the drift region 100, can increase the switching speed, while reducing the switching capacitance of the IGBT device and reducing the device conduction voltage drop. The electric field concentration problem at the bottom of the trench improves the reliability of the device.

The above examples only express several implementation manners of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the scope of the invention patent. It should be pointed out that for those of ordinary skill in the art, without departing from the concept of this application, several modifications and improvements can be made, and these all fall within the protection scope of this application. Therefore, the scope of protection of the patent of this application shall be subject to the appended claims.

Claims

An IGBT device including:

The drift zone has the first conductivity type;

The body region is formed in the drift region and has the second conductivity type;

The first doped region is formed in the body region and has the first conductivity type;

A second doped region formed in the body region and has a second conductivity type, and the doping concentration of the second doping region is greater than the doping concentration of the body region;

A trench sequentially penetrates the first doped region and the body region and extends to the drift region, and the second doped region is spaced apart from the trench;

The filling structure includes an oxide layer formed on the inner wall of the trench and a first conductive structure and a second conductive structure filled in the trench and isolated from each other. The bottom depth of the first conductive structure is greater than that of the second conductive structure. The depth of the bottom of the conductive structure;

An extension region formed in the drift region below the trench and surrounding the bottom of the trench, having a second conductivity type, and the extension region is isolated from the first conductive structure by the oxide layer;

An emitter lead-out structure in contact with the first doped region and the second doped region; and

The gate lead structure is in contact with the second conductive structure.
The IGBT device according to claim 1, wherein the second doped region is located in a body region at the bottom of the first doped region, and the emitter extraction structure penetrates the first doped region and Extending to the second doped region.
3. The IGBT device of claim 2, wherein the second doped region surrounds the bottom of the emitter lead structure.
The IGBT device of claim 2, further comprising:

The interlayer dielectric layer covers the first doped region and the trench, the emitter extraction structure also penetrates the interlayer dielectric layer and is in contact with the emitter on the interlayer dielectric layer, and the gate leads The structure also penetrates the interlayer dielectric layer and is in contact with the gate on the interlayer dielectric layer.
The IGBT device of claim 1, wherein the first conductive structure and the second conductive structure are formed at the bottom and the top of the trench, respectively, and the first conductive structure and the second conductive structure An isolation structure is formed between the conductive structures to isolate the first conductive structure and the second conductive structure.
The IGBT device of claim 1, wherein the doping concentration of the drift region located above the extension region is higher than the doping concentration of the drift region located below the extension region.
8. The IGBT device of claim 1, wherein the first conductive structure is an uncharged floating structure.
8. The IGBT device of claim 1, wherein the first conductive structure is drawn from an end of the trench and is electrically connected to the emitter lead structure.
The IGBT device of claim 1, wherein the oxide layer comprises:

An isolation oxide layer, located between the first conductive structure and the inner wall of the trench; and

The gate oxide layer is located between the second conductive structure and the inner wall of the trench.
The IGBT device of claim 1, wherein the first conductive structure extends from the top of the trench to the bottom of the trench, and the first conductive structure is formed between the sidewalls of the trench There is the oxide layer, and the second conductive structure is formed in the oxide layer on both sides of the first conductive structure.
The IGBT device of claim 1, wherein the first conductivity type is N-type, and the second conductivity type is P-type.
An IGBT device preparation method, including:

Forming a drift region on the semiconductor substrate, opening a trench on the drift region, and forming an oxide layer on the inner wall of the trench, the drift region having the first conductivity type;

Forming an extension area in the drift zone below the trench, the extension area having the second conductivity type and surrounding the bottom of the trench;

Filling the trench with a first conductive structure and a second conductive structure that are isolated from each other, and the bottom depth of the first conductive structure is greater than the bottom depth of the second conductive structure;

Doping the drift region with the second conductivity type to form a body region, the body region is in contact with the trench, and the depth of the body region is smaller than the depth of the trench; and

The body region is doped with the first conductivity type and the second conductivity type respectively to form a first doped region and a second doped region. The first doped region is in contact with the trench, so The doping concentration of the second doping region is greater than the doping concentration of the body region, forming an emitter lead-out structure in contact with the first doping region and the second doping region, and forming a contact with the first doping region. The gate lead-out structure in contact with the two conductive structures.
The preparation method according to claim 12, wherein before the second conductivity type doping is performed on the drift region to form the body region, the method further comprises: doping the drift region with the first conductivity type to improve the body region. The concentration of the drift zone above the expansion zone.
The manufacturing method according to claim 12, wherein the step of filling the first conductive structure and the second conductive structure isolated from each other in the trench comprises:

Filling the first conductive structure into the trench;

Etching the first conductive structure and the oxide layer at the top of the trench, leaving the first conductive structure and the oxide layer at the bottom of the trench;

Forming an isolation structure in the trench; the isolation structure covers the first conductive structure at the bottom of the trench and does not fill the trench;

An oxide layer is formed on the inner wall of the trench above the isolation structure and a second conductive structure is filled into the trench.
The preparation method of claim 12, wherein the first conductivity type doping and the second conductivity type doping are respectively performed on the body region to correspondingly form a first doped region and a second doped region The steps include:

Doping the upper surface layer of the body region with the first conductivity type to form the first doped region;

Forming an interlayer dielectric layer covering the first doped region and the trench on the first doped region;

Opening an emitter contact hole that sequentially penetrates the interlayer dielectric layer and the first doped region and extends to the body region, and a gate contact hole that penetrates the interlayer dielectric layer;

Doping the body region with the second conductivity type through the emitter contact hole to form the second doped region;

The step of forming an emitter extraction structure in contact with the first doped region and the second doped region, and forming a gate extraction structure in contact with the second conductive structure includes:

The emitter contact hole and the gate contact hole are filled with conductive material to form an emitter lead structure and a gate lead structure.