JPH09260648A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a vertical IGBT(insulated gate bipolar transistor) for power use of a trench gate structure, which can be reduced its on-voltage, without causing a reduction in its breakdown voltage and breakdown strength. SOLUTION: A low-concentration drift region 21 is formed on a drift region 12, base regions 13 are formed in this region 21 and emitter regions 14 are respectively formed in each of these regions 13. Trench gate regions 15 are formed to a depth, which penetrates the regions 14 and 13 to reach the region 21 and does not reach the region 12. Depletion layers in the vicinities of the regions 15 are easily spread by the region 21, and even if the regions 15 are deeply formed, a field concentration can be relaxed. Therefore, as a reduction in the breakdown strength of an insulated gate bipolar transistor is hardly caused and the regions 15 can be deeply formed, the storage effect and conductivity modulation effect of carriers in the vicinities of the base regions 13 can be increased, and the on-state voltage of the insulated gate bipolar transistor can be reduced, without causing a reduction in the breakdown voltage and breakdown strength of the transistor.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a power vertical insulated gate bipolar transistor (IGBT) having a trench gate structure.

[0002]

2. Description of the Related Art A vertical MOSFET for electric power employs a trench gate structure capable of reducing a gate length (LG) in order to reduce an on-voltage. FIG. 6 shows a vertical power MOS using such a trench gate structure.
It is a cross-sectional block diagram of FET. In FIG. 6, 1 is an N-type high-concentration drain region, 2 is an N-type drift region, 3 is a P-type base region, 4 is an N-type source region, 5 is a trench gate region, 6 is a gate insulating film, and 7 is a gate electrode. , 8 is a source metal electrode, 9 is a gate metal electrode, and 10 is a drain metal electrode.

In such a structure, since the gate electrode 7 is embedded in the groove formed through the source region 4 and the base region 3, in the case of the N-channel type, carriers in the ON state ( Electrons) flow vertically from the source region 4 to the drain region 1 through the channel formed along the sidewall of the groove facing the gate electrode 7 in the base region 3.

Therefore, the planar type MOSF shown in FIG.
Accumulation of carriers in the base region 3 like ET hardly occurs. By the way, since a power vertical insulated gate bipolar transistor (IGBT) has a composite structure of a vertical MOSFET and a thyristor, it is considered that improvement of the characteristics of the MOSFET will improve the characteristics of the IGBT. Therefore, as shown in FIG. 8, a miniaturized trench gate structure similar to that of the vertical power MOSFET is adopted.
In FIG. 8, 11 is a P-type collector region (P-type semiconductor substrate), 12 is an N-type drift region, 13 is a P-type base region, 14 is an N-type emitter region, 15 is a trench gate region, 16 is a gate insulating film, 17 is a buried gate electrode,
18 is an emitter metal electrode, 19 is a gate metal electrode, 20
Is a collector metal electrode.

As described above, since the number of carriers related to the on-voltage is one in the MOSFET, the on-voltage can be reduced by reducing the resistance to the carrier. Therefore, the on-voltage can be reduced by reducing the gate area by increasing the trench gate and increasing the channel width. However, the IGBT is a bipolar element, and it is necessary to optimize the distribution of two carriers in order to reduce the ON voltage. In the miniaturized trench gate structure as shown in FIG. 8, the accumulation of the first-conductivity type carriers in the base region 13 which is a problem in the planar type is small.
The accumulation of conductive carriers is also reduced. This leads to a decrease in the conductivity modulation effect in the vicinity of the base region 13, and especially when the carrier lifetime is shortened to increase the switching speed, the on-voltage rises.

In order to solve this problem, the width of the trench gate may be widened, the amount of protrusion of the trench gate region 15 from the base region 13 may be increased (the trench gate region 15 may be deepened), but both of them have a breakdown voltage. There is a problem that it lowers. Since the decrease of the breakdown voltage depends on the impurity concentration of the drift region 12, the decrease of the breakdown voltage is remarkable in the low breakdown voltage type product in which the impurity concentration of the drift region 12 is high. Further, if the impurity concentration of the drift region 12 as a whole is lowered, the depletion layer is likely to expand, and reach through is performed at a low voltage, so that the sustaining voltage is lowered. As a result, there is a problem that the breakdown withstand voltage at the time of applying a reverse bias is reduced and the safe operation area is narrowed.

Further, the above-mentioned IG having the trench gate structure.
When manufacturing a BT, it is necessary to adjust the impurity concentration and diffusion conditions of the base region 13 according to the breakdown voltage, which causes a problem that the use efficiency of the equipment is reduced and the manufacturing cost is increased.

[0008]

As described above, the conventional IGBT having the trench gate structure has a problem that when the ON voltage is reduced, the breakdown voltage and the breakdown resistance are reduced. Further, when manufacturing a conventional IGBT having a trench gate structure, it is necessary to adjust the impurity concentration and diffusion conditions of the base region according to the breakdown voltage, which reduces the efficiency of use of equipment and raises the manufacturing cost. was there.

The present invention has been made in view of the above circumstances. An object of the present invention is to provide a semiconductor device capable of reducing the on-voltage without lowering the breakdown voltage or the breakdown resistance. It is in. Another object of the present invention is to provide a method of manufacturing a semiconductor device, which can simplify the manufacturing process, achieve high mass productivity and reduce manufacturing cost.

[0010]

According to a first aspect of the present invention, there is provided a semiconductor device having a first conductivity type collector region and a second conductivity type first drift region formed on the collector region. , A second drift region formed on the first drift region and having a second conductivity type and an impurity concentration lower than that of the first drift region, and a surface region of the second drift region. A first conductivity type base region, a second conductivity type emitter region selectively formed in the base region, a second conductivity type emitter region penetrating the emitter region and the base region, and reaching the second drift region, and A groove having a depth that does not reach the first drift region, a gate insulating film formed on the inner wall of the groove, a gate electrode embedded in the groove, and an insulation provided on the second drift region. Membrane and insulation A source metal electrode formed on the insulating film, the source metal electrode short-circuiting the base region and the source region through the first opening formed on the insulating film; and the source metal electrode formed on the insulating film and formed on the insulating film. A gate metal electrode electrically connected to the gate electrode embedded in the groove through the second opening, and a collector metal electrode formed on the back surface side of the collector region. There is.

According to a second aspect of the present invention, the semiconductor device further comprises a high-concentration buffer layer of the second conductivity type provided between the collector region and the first drift region.

According to the above structure, the depletion layer in the vicinity of the trench gate region is easily extended by providing the second drift region having a low impurity concentration on the first drift region, and the trench gate region is deepened. Even if formed, the electric field concentration can be relaxed. Therefore, the breakdown voltage is less likely to occur,
Since the trench gate region can be deepened, the effect of accumulating carriers near the base region can be increased and the effect of conductivity modulation can be increased. Further, since the breakdown voltage can be secured in the first drift region, the on-voltage can be reduced without lowering the breakdown voltage or the breakdown withstand voltage.

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a first drift region of the second conductivity type is formed on a semiconductor substrate of the first conductivity type serving as a collector region by a vapor phase growth method. And a step of forming a second drift region of a second conductivity type having an impurity concentration lower than that of the first drift region on the first drift region by a vapor phase growth method, and the second drift Forming a base region of the first conductivity type in the surface region of the region, selectively forming an emitter region of the second conductivity type in the base region, and anisotropically etching the emitter region and Forming a groove having a depth penetrating the base region to reach the second drift region and not reaching the first drift region; and forming a gate oxide film on an inner wall of the trench. ,Before Filling the trench with a conductive layer to be a gate electrode; forming an insulating film on the second drift region; forming first and second openings in the insulating film; Forming a metal layer on the film and in the first and second openings, patterning the metal layer, and through the first opening formed in the insulating film, the base region and the source region Forming a source metal electrode short-circuiting the gate electrode and a gate metal electrode electrically connected to the gate electrode embedded in the groove through a second opening formed in the insulating film; And a step of forming a collector metal electrode on the back surface side of the collector region.

Further, as described in claim 4, the method further comprises the step of forming a second conductivity type high concentration buffer layer on the semiconductor substrate by a vapor phase growth method, and the vapor phase is formed on the high concentration buffer layer. It is characterized in that the first drift region is formed by a growth method.

According to the manufacturing method as described above, since the second drift region having a low impurity concentration is provided on the first drift region, the base region of the base region which has conventionally been required to be adjusted according to the breakdown voltage. Concentration and diffusion conditions can be unified. As a result, even products with different withstand voltages can be formed by the same impurity diffusion process, and the manufacturing process can be simplified, so that high mass productivity and manufacturing cost reduction can be achieved.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a first embodiment of the present invention.
FIG. 6 is a cross-sectional configuration diagram of the semiconductor device according to the embodiment of the present invention, showing an N-channel power vertical insulated gate bipolar transistor (IGBT) having a trench gate structure. In FIG. 1, 11 is a P-type collector region (P-type semiconductor substrate), 12 is an N-type drift region (first drift region), 13 is a P-type base region, 14 is an N-type emitter region, and 15 is a trench gate region. , 16 is a gate insulating film,
17 is a buried gate electrode, 18 is an emitter metal electrode,
19 is a gate metal electrode, 20 is a collector metal electrode, 21
Is an N-type low concentration drift region (second drift region).

An N-type drift region 12 is formed on the P-type semiconductor substrate 11 serving as a P-type collector region with a concentration and thickness according to the breakdown voltage, and a collector metal electrode 20 is formed on the back surface side of the substrate 11. Has been done. The drift region 1
An N-type low-concentration drift region 21 is formed on the surface 2 with a predetermined concentration and a thickness, and a P-type base region 13 is formed with a predetermined depth in the surface region of the low-concentration drift region 21.
An N-type emitter region 14 is selectively formed in the surface region of the base region 13. A trench gate region 15 is formed at a depth penetrating the emitter region 14 and the base region 13 to reach the low concentration drift region 21 and not to reach the drift region 12. An insulating film 23 is formed on the low concentration drift region 21, and the insulating film 2
Opening portions are formed in the contact portion of the emitter metal electrode 18 and the contact portion of the gate metal electrode 19, respectively. The emitter metal electrode 18 is formed so as to short-circuit the N-type emitter region 14 and the P-type base region 13 through the opening formed in the insulating film 23, and the gate metal electrode 19 is formed in the insulating film 23. It is electrically connected to the gate electrode 17 through the formed opening.

In the above structure, since the N type low concentration drift region 21 is provided on the N type drift region 12, the depletion layer in the vicinity of the trench gate region 15 is easily extended and the electric field concentration can be relaxed. Therefore, the N-type drift region 12
It is possible to form the trench gate region 15 deep even in a low breakdown voltage product having a high impurity concentration. Therefore, the breakdown voltage is less likely to occur, and the trench gate region 1
Since 5 can be made deeper, the effect of accumulating carriers near the base region 13 can be increased, and the effect of conductivity modulation can be increased. Further, the breakdown voltage can be secured in the N-type drift region 12 having a high impurity concentration. Therefore, the on-voltage can be reduced without lowering the breakdown voltage and the breakdown resistance.

FIG. 2 is a view for explaining a semiconductor device according to a second embodiment of the present invention, which is an N-channel vertical power IGBT having a trench gate structure.
FIG. 2, the same components as those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted. That is, the N-type high concentration buffer layer 22 is formed between the P-type collector region 11 and the N-type drift region 12 in FIG. Even in the IGBT having such a structure, the action of the N-type low concentration drift region 21 is substantially the same as that of the first embodiment, and the same effect can be obtained.

Next, a method of manufacturing the IGBT shown in FIG. 2 will be described with reference to FIGS. 3 (a) to 3 (f). Here, an IGBT having a breakdown voltage of 600 V is taken as an example. First, as shown in FIG. 3A, the phosphorus concentration is 1 × 10 ¹⁷ to 1 × 10 on the P-type semiconductor substrate 11 serving as a collector region.
An N-type high-concentration buffer layer 22 having a thickness of ¹⁸ atoms / cm ³ and a thickness of about 10 μm is formed by a vapor phase growth method, and a phosphorus concentration of 1 × 10 ^{14 to} 5 × 10 ¹⁴ atoms / is formed on the buffer layer 22.
Withstand voltage of cm ³ and thickness of about 40 μm (600 V here)
The N-type drain region 12 having a concentration and a thickness corresponding to is formed by the vapor phase epitaxy method. Then, the N-type drain region 1
An N-type low-concentration drift region 21 having a phosphorus concentration of 8 × 10 ¹³ atoms / cm ³ or less and a thickness of about 20 μm, which is thicker than the depth of the trench gate region 15, is formed on the second layer 2 by vapor phase epitaxy. The impurity concentration and thickness of the low concentration drift region 21 are determined by the width and depth of the trench gate region 15.

In this way, the N-type high-concentration buffer layer 2
2, the N-type drift region 12 and the N-type low-concentration drift region 21 are sequentially stacked in the surface region of the N-type low-concentration drift region 21 in the semiconductor wafer, as shown in FIG. Etc., the impurities such as boron are selectively diffused to form the P-type base region 13. Then, an impurity such as arsenic is selectively diffused into the base region 13 by an ion implantation method or the like to form an N-type emitter region 14
To form

Thereafter, as shown in FIG. 3C, anisotropic etching such as RIE is performed using an oxide film or the like as a mask material,
The emitter region 14 and the base region 13 are penetrated to reach the N-type low concentration drift region 21, and the N-type drift region 12
A trench is formed to a depth that does not reach.

Subsequently, the inner wall of the groove is thermally oxidized to form a gate oxide film 16 having a thickness of about 100 nm, and the inside of the groove is filled with a polysilicon layer (conductive layer) to be a gate electrode 17, thereby forming a trench. The gate region 15 is formed (see FIG. 3D).

Thereafter, as shown in FIG. 3E, an insulating film 23 is formed on the entire surface of the drift region 21 by the CVD method or the like, and the portions connected to the metal electrodes of the emitter and the gate are selectively etched. And removed to form an opening. Subsequently, a metal such as Al is formed on the insulating film 23 by a sputtering method or the like and patterned to form an emitter metal electrode 18 and a gate metal electrode 19, respectively. Next, a metal such as Au is formed on the front surface of the P-type collector region 11 (back surface of the semiconductor substrate) by a sputtering method or the like to form the collector metal electrode 20.

Then, the semiconductor wafer on which the IGBT element is formed as described above is cut into a predetermined size and separated to complete an IGBT chip. According to the manufacturing method as described above, by forming the N-type low-concentration drift layer 21 on the N-type drift region 12, the impurity concentration and diffusion conditions of the base region 13 which have conventionally been required to be adjusted by the breakdown voltage can be improved. Can be unified. As a result, even products with different withstand voltages can be formed by the same impurity diffusion process, and the use efficiency of the equipment is improved, so that the manufacturing cost can be reduced.

FIG. 4 shows the relationship between the ON voltage and the switching time depending on the depth of the trench. The horizontal axis is the switching time, the vertical axis is the on-voltage, and the trench depth is 4
The relationship is for μm, 6 μm, and 8 μm. As is clear from FIG. 4, the deeper the trench, that is, the trench gate region 15, is, the lower the on-voltage can be.

Further, FIG. 5 compares the safe operating area for application of a reverse bias voltage between the IGBT of the present invention and the conventional IGBT (when the N type drift region 12 in FIG. 8 is formed to have a low impurity concentration). Shows. In FIG. 5, the horizontal axis is the collector-emitter voltage, the vertical axis is the collector current, and the safe operation area (guaranteed range) is the area outside the broken line. Although the conventional products are close to the limit of the guarantee range and some are out of the guarantee range, all the products of the present invention are within the guarantee range, and the safe operation region is formed by forming the N-type drift region 12 in a low impurity concentration. It can be seen that it spreads significantly compared to the case.

In the first and second embodiments, the N-channel type IGBT has been described as an example.
It is needless to say that the conductivity type of each active region is reversed to be applicable to the P channel type.

[0029]

As described above, according to the present invention, it is possible to obtain a semiconductor device capable of reducing the on-voltage without lowering the breakdown voltage and the breakdown withstand voltage. Further, it is possible to obtain a method for manufacturing a semiconductor device, which can simplify the manufacturing process, achieve high mass productivity, and reduce manufacturing cost.

[Brief description of drawings]

FIG. 1 is a cross-sectional configuration diagram of a power vertical IGBT having a trench gate structure for explaining a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional configuration diagram of a vertical power IGBT having a trench gate structure for explaining a semiconductor device according to a second embodiment of the present invention.

3A to 3D are cross-sectional views sequentially showing manufacturing steps of the IGBT shown in FIG.

FIG. 4 is a diagram showing a relationship between an on-voltage and a switching time depending on a depth of a trench gate region.

FIG. 5 is a diagram for explaining a safe operation region for application of a reverse bias voltage of the IGBT of the present invention and the conventional IGBT.

FIG. 6 is a cross-sectional configuration diagram of a trench gate vertical MOSFET for explaining a conventional semiconductor device.

FIG. 7 is a cross-sectional configuration diagram of a planar MOSFET for explaining a conventional semiconductor device.

FIG. 8 is a cross-sectional configuration diagram of a trench gate vertical IGBT for explaining a conventional semiconductor device.

[Explanation of symbols]

11 ... P-type collector region (P-type semiconductor substrate), 12 ... N
Type drift region, 13 ... P type base region, 14 ... N type emitter region, 15 ... Trench gate region, 16 ... Gate insulating film, 17 ... Embedded gate electrode, 18 ... Emitter metal electrode, 19 ... Gate metal electrode, 20 ... Collector metal electrode, 21 ... N type low concentration drift region, 22 ... N type high concentration buffer layer, 23 ... Insulating film.

Claims (4)

[Claims] 1. A collector region of a first conductivity type, a first drift region of a second conductivity type formed on the collector region, and a collector region of a second conductivity type formed on the first drift region. A second drift region having an impurity concentration lower than that of the first drift region, a first conductivity type base region formed in a surface region of the second drift region, and selectively in the base region. A second conductive type emitter region to be formed, a groove penetrating the emitter region and the base region to reach the second drift region and not to reach the first drift region, A gate insulating film formed on the inner wall of the groove, a gate electrode embedded in the groove, an insulating film provided on the second drift region, and an insulating film formed on the insulating film and formed on the insulating film. Through the first opening A source metal electrode that short-circuits the base region and the source region, and a gate electrode that is formed on the insulating film and is embedded in the groove through a second opening formed in the insulating film. And a collector metal electrode formed on the back surface side of the collector region. 2. The semiconductor device according to claim 1, further comprising a second-conductivity-type high-concentration buffer layer provided between the collector region and the first drift region. 3. A step of forming a first drift region of a second conductivity type on a semiconductor substrate of the first conductivity type, which acts as a collector region, by a vapor phase epitaxy method, and a vapor phase on the first drift region. Forming a second drift region of the second conductivity type having a lower impurity concentration than that of the first drift region by a growth method; and forming a base region of the first conductivity type in a surface region of the second drift region. Forming, a step of selectively forming a second conductivity type emitter region in the base region, and anisotropic etching to penetrate the emitter region and the base region to form the second drift region. Forming a groove having a depth that reaches the first drift region and does not reach the first drift region, forming a gate oxide film on the inner wall of the groove, and filling the inside of the groove with a conductive layer serving as a gate electrode. And the above Forming an insulating film on the second drift region; forming first and second openings in the insulating film; and forming a metal layer on the insulating film and in the first and second openings. And a source metal electrode that short-circuits the base region and the source region through the first opening formed in the insulating film by patterning the metal layer, and the insulating film. Forming a gate metal electrode electrically connected to the gate electrode embedded in the groove through the second opening, and forming a collector metal electrode on the back surface side of the collector region. A method for manufacturing a semiconductor device, comprising: 4. The method further comprises the step of forming a second conductivity type high concentration buffer layer on the semiconductor substrate by a vapor phase growth method, wherein the first drift is formed on the high concentration buffer layer by a vapor phase growth method. A region is formed to form a region.
A method of manufacturing a semiconductor device according to item 1.