WO2021232813A1

WO2021232813A1 - Trench gate metal oxide semiconductor field effect transistor, and manufacturing method thereof

Info

Publication number: WO2021232813A1
Application number: PCT/CN2020/140672
Authority: WO
Inventors: 方冬; 肖魁
Original assignee: 华润微电子（重庆）有限公司
Priority date: 2020-05-18
Filing date: 2020-12-29
Publication date: 2021-11-25
Also published as: CN114361247A

Abstract

A trench gate metal oxide semiconductor field effect transistor and a manufacturing method thereof. The trench gate metal oxide semiconductor field effect transistor comprises: a drift region (100) having a first conductivity type; a bulk region (110) having a second conductivity type and formed in the drift region (100); a source region (111) having the first conductivity type and formed in the bulk region (110), wherein the source region (111) is provided with a trench extending into the drift region (100), the trench is filled with a first conductive structure (130) and a second conductive structure (140) isolated from each other, a bottom portion of the first conductive structure (130) has a depth greater than a depth of a bottom portion of the second conductive structure (140), and a field plate adjustment structure is defined as a portion of the first conductive structure (130) that is at a depth greater than the depth of the bottom portion of the second conductive structure (140); and a first doping region (160) having the second conductivity type, formed in the drift region (100), and abutting the bulk region (110), wherein a bottom portion of the first doping region (160) has a depth greater than a depth of a top portion of the field plate adjustment structure, the source region (111) and the bulk region (110) are connected to a source, and the second conductive structure (140) is connected to a gate.

Description

Trench gate metal oxide semiconductor field effect tube and preparation method thereof

Cross-references to related applications

This application claims the priority of a Chinese patent application filed with the Chinese Patent Office, the application number is 2020104188763, and the invention title is "Trench Gate Metal Oxide Semiconductor Field Effect Transistor and Its Preparation Method" on May 18, 2020, and its entire contents Incorporated in this application by reference.

Technical field

This application relates to the field of semiconductors, and in particular to a trench gate metal oxide semiconductor field effect transistor and a preparation method thereof.

Background technique

The statements here only provide background information related to this application, and do not necessarily constitute prior art.

In MOS (Metal Oxide Semiconductor Field Effect Transistor, MOSFET), a conduction channel is formed between the source and drain. The existence of the conduction channel makes the metal oxide semiconductor field effect transistor have For a certain on-resistance, the greater the on-resistance, the greater the power consumption. Therefore, it is necessary to reduce the on-resistance as much as possible. At present, metal oxide semiconductor field effect transistors with a trench gate structure are usually used to form trenches. The gate structure changes the conduction channel from the horizontal to the vertical, which greatly increases the cell density and reduces the on-resistance. However, on the basis of the trench gate metal oxide semiconductor field effect transistor, if you want to further reduce the on-resistance , The doping concentration of the drift region needs to be increased, and increasing the doping concentration will weaken the withstand voltage capability of the device. Therefore, due to the limitation of the withstand voltage capability, the on-resistance of the trench gate metal oxide semiconductor field effect transistor is further reduced. Becomes difficult.

Summary of the invention

Based on this, it is necessary to propose a new metal oxide semiconductor field effect transistor and its manufacturing method in view of the current technical problem that the trench gate metal oxide semiconductor field effect transistor is difficult to further reduce the on-resistance.

A trench gate metal oxide semiconductor field effect transistor, comprising: a drift region having a first conductivity type and formed on a semiconductor substrate; a body region having a second conductivity type and formed on an upper surface layer of the drift region; The source region has the first conductivity type and is formed on the upper surface layer of the body region; the trench penetrates the source region and the body region sequentially and extends to the drift region; the filling structure includes filling in the body region. The first conductive structure and the second conductive structure in the trench isolated from each other, and formed between the first conductive structure and the inner wall of the trench and between the second conductive structure and the inner wall of the trench The bottom depth of the first conductive structure exceeds the bottom depth of the second conductive structure, and the portion of the first conductive structure whose depth exceeds the bottom depth of the second conductive structure is defined as the field plate adjustment structure; the first doping Region, having the second conductivity type, formed in the drift region and in contact with the lower surface of the body region, the first doped region and the trench are spaced apart, the first doped region The bottom depth exceeds the top depth of the field plate adjustment structure; the source extraction structure is connected to the source region and the body region; and the gate extraction structure is connected to the second conductive structure.

A method for preparing a trench gate metal oxide semiconductor field effect transistor includes:

A semiconductor substrate is provided and a drift region with the first conductivity type is formed on the semiconductor substrate; a trench is opened on the drift region, an oxide layer is formed on the inner wall of the trench, and the trench Filled with a first conductive structure and a second conductive structure that are isolated from each other, the bottom depth of the first conductive structure is greater than the bottom depth of the second conductive structure, and the depth of the first conductive structure exceeds the depth of the bottom of the second conductive structure. Part of it is a field plate adjustment structure; the upper surface layer of the drift region is doped to form a body region of the second conductivity type in contact with the sidewall of the trench, the depth of the body region is less than the depth of the trench Doping the upper surface layer of the body region to form a source region of the first conductivity type in contact with the sidewall of the trench; forming a first doped region of the second conductivity type in the drift region, The first doped region is connected to the body region, the first doped region is spaced apart from the trench, and the bottom depth of the first doped region exceeds the top depth of the field plate adjustment structure And forming a source lead-out structure connected to the source region and the body region, and a gate lead-out structure connected to the second conductive structure.

The details of one or more embodiments of the present application are set forth in the following drawings and description. Other features, purposes and advantages of this application will become apparent from the description, drawings and claims.

Description of the drawings

FIG. 1 is a partial side cross-sectional view of a trench gate metal oxide semiconductor field effect transistor cell region in an embodiment of this application;

2 is a partial side cross-sectional view of a trench gate metal oxide semiconductor field effect transistor cell region in another embodiment of the application;

FIG. 3a is a cross-sectional view of a trench gate metal oxide semiconductor field effect transistor along the line A-A' in FIG. 1 in an embodiment of the application;

FIG. 3b is a cross-sectional view of a trench gate metal oxide semiconductor field effect transistor along the A-A' section line in FIG. 1 in another embodiment of the application;

4a is a schematic diagram of the structure in the trench in an embodiment of the application;

4b is a schematic diagram of the structure in the trench in another embodiment of the application;

5 is a flow chart of the steps of a method for manufacturing a trench gate metal oxide semiconductor field effect transistor in an embodiment of the application;

6a to 6h are structural cross-sectional views corresponding to relevant steps of a method for manufacturing a trench gate metal oxide semiconductor field effect transistor in an embodiment of the application;

7a to 7c are cross-sectional views of the structure corresponding to the steps of forming the first doped region in an embodiment of the application.

Label description

100 drift region; 101 first epitaxial layer; 102 second epitaxial layer; 110 body region; 111 source region; 112 second doped region; 120 oxide layer; 130 first conductive structure; 140 second conductive structure; 150 isolation structure ; 160 first doped region; 200 interlayer dielectric layer; 310 source lead structure.

Detailed ways

In order to facilitate the understanding of the application, the application will be described in a more comprehensive manner with reference to the relevant drawings. The preferred embodiment of the application is shown in the accompanying drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of this application more thorough and comprehensive.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field of this application. The terms used in the specification of the application herein are only for the purpose of describing specific embodiments, and are not intended to limit the application. The term "and/or" as used herein includes any and all combinations of one or more related listed items.

As shown in conjunction with FIG. 1, the trench gate metal oxide semiconductor field effect transistor includes a drift region 100 formed on a semiconductor substrate, and the drift region may specifically be formed by epitaxial growth of the semiconductor substrate. A body region 110 is formed on the upper surface of the drift region 100, and an active region 111 is formed on the upper surface of the body region 110.

The source region 111 is provided with a trench that penetrates the source region 111 and the body region 110 and extends into the drift region 100, that is, the bottom end of the trench is located in the drift region 100. The trench is filled with a first conductive structure 130 and a second conductive structure 140 that are isolated from each other. An oxide layer 120 is formed between the first conductive structure 130 and the inner wall of the trench and between the second conductive structure 140 and the inner wall of the trench. Wherein, the oxide layer 120 located between the first conductive structure 130 and the inner wall of the trench is a gate oxide layer, and the oxide layer located between the second conductive structure 140 and the inner wall of the trench is an isolation oxide layer, which is filled in the trench The oxide layer 120 and the first conductive structure 130 and the second conductive structure 140 isolated from each other together form a filling structure. In the same trench, the depth of the first conductive structure 130 is greater than the depth of the second conductive structure 140, that is, the distance between the first conductive structure 130 and the bottom of the trench is smaller than the distance between the second conductive structure 140 and the bottom of the trench, which defines the first A portion of the conductive structure 130 whose depth exceeds the depth of the bottom of the second conductive structure 140 is a field plate adjustment structure, that is, the portion of the first conductive structure under the second conductive structure 140 is a field plate adjustment structure.

A first doped region 160 is also formed in the drift region 100. The top of the first doped region 160 is connected to the body region 110, and the first doped region 160 is spaced apart from the trench. The bottom of the first doped region 160 is deep Exceeding the top depth of the field plate adjustment structure, that is, the lateral projection of the first doped region 160 and the field plate adjustment structure has an overlapping area.

The trench gate metal oxide semiconductor field effect transistor also includes a source lead-out structure 310 and a gate lead-out structure (not shown in the figure). The source lead-out structure 310 and the gate lead-out structure can be metal pillars, specifically tungsten metal . Wherein, the source lead structure 310 is connected to the source region 111 and the body region 110, and the gate lead structure is connected to the second conductive structure 140 in the trench.

The drift region 100 and the source region 111 have a first conductivity type, and the body region 110 and the first doped region 160 have a second conductivity type. Wherein, the first conductivity type is N type, and the second conductivity type is P type; or, the first conductivity type is P type, and the second conductivity type is N type. It is understandable that the front side of the trench gate metal oxide semiconductor field effect transistor should also have a source metal layer and a gate metal layer that are isolated from each other. The source extraction structure 310 is connected to the source metal layer. The lead structures are all connected with the gate metal layer, and a drain metal layer is also formed on the back of the trench gate metal oxide semiconductor field effect transistor.

In the above trench gate MOSFET, on the one hand, the top source region 111 is connected to the source metal layer through the source extraction structure 310, and the bottom drift region 100 is used as the drain region to connect to the drain metal layer, and the middle The body region 110 forms a channel region. The trench penetrates the body region 110 and extends into the drift region 100. There is an oxide layer 120 and a second conductive structure 140 in the trench. The electrode metal layer is connected, that is, the trench and the gate oxide layer inside the trench and the second conductive structure 140 form a trench gate structure, thereby forming a trench gate metal oxide semiconductor field effect transistor. Through this trench gate structure, a longitudinal conductive channel can be formed in the body region 110.

On the other hand, a first conductive structure 130 is also formed in the bottom of the trench. The first conductive structure part located under the second conductive structure 140 is a field plate adjustment structure, and the field plate adjustment structure and the isolation oxide layer in contact therewith are formed The inner field plate can adjust the electric field distribution inside the drift region 100, so that the drift region in contact with the inner field plate forms a depletion region, thereby enhancing the depletion of the drift region 100. In addition, a first doped region 160 is formed in the drift region 100. The first doped region 160 has a source potential and has a conductivity type opposite to that of the drift region 100. The first doped region 160 and the drift region 100 form a reverse PN Therefore, the drift region in contact with the first doped region 160 also forms a depletion region, which further enhances the depletion of the drift region 100. At the same time, in the present application, the depth of the bottom of the first doping region 160 exceeds the depth of the top of the field plate adjustment structure, so that the depletion region formed by the first doping region 160 and the depletion region formed by the inner field plate are laterally distributed side by side, The withstand voltage of the drift region 100 is further increased. Compared with ordinary trench gate metal oxide semiconductor field effect transistors, the trench gate metal oxide semiconductor field effect transistors in this application have a higher breakdown voltage, that is, under the condition of ensuring the same breakdown voltage Next, the drift region 100 of the trench gate MOSFET in the present application can have a higher doping concentration. Therefore, the trench gate MOSFET in the present application also has a lower doping concentration.的 On-resistance. At the same time, in the trench, the first conductive structure 130 connected to the source metal layer is closer to the bottom of the trench than the second conductive structure 140 connected to the gate, which can reduce the parasitic capacitance between the gate and drain, so that The device has better characteristics.

In one embodiment, as shown in FIG. 2, the sidewall of the first doped region 160 includes a first portion 161 extending downward from the bottom of the body region 110 and a first portion 162 extending downward from the first portion, wherein the first portion 161 is parallel to the sidewall of the trench, the longitudinal section of the first part 161 is rectangular, and the distance between the first part 161 and the sidewall of the trench is equal; the second part 162 gradually moves from top to bottom to the inside of the first doped region 160 Inclined, the longitudinal section of the second part 162 is inverted trapezoid or inverted triangle, and the distance between the second part 162 and the sidewall of the trench gradually increases from top to bottom. At the same time, the interface between the first part 161 and the second part 162 (the dotted line shown in FIG. 2) passes through the field plate adjustment structure, that is, passes through the first conductive structure 130 in the trench but does not pass through the second conductive structure 140. In this application, the first doped region 160 needs to be spaced apart from the trench, that is, the first doped region 160 needs to be spaced apart from the trench gate to allow current between the drain and the source to pass. In the metal oxide semiconductor field effect transistor, since the body region 110 only forms a narrow channel region near the sidewall of the trench for current to pass, in the drift region 100, the current density near the trench is also the largest. The farther the trench is, the lower the current density. The first doped region 160 can be located in a region with a low current density to reduce the blocking effect on current, that is, to increase the distance between the first doped region 160 and the trench is It is beneficial to reduce the on-resistance of VDMOS. However, the greater the distance between the first doped region 160 and the field plate adjustment structure, the greater the distance between adjacent depletion layers, and thus the weaker the voltage withstand capability. In this embodiment, by further improving the shape of the first doped region 160, the distance between the upper sidewall of the first doped region 160 and the field plate adjustment structure is smaller, and a densely distributed depletion layer is formed, while the lower part The sidewalls are gradually inclined inward to increase the distance between the first doped region and the trench, that is, to reduce the area of the first doped region 160, so as to ensure the withstand voltage capability and reduce the on-resistance of the device. Further, the depletion layer formed in the first doped region 160 and the depletion layer formed in the inner field plate extend around and connect to each other. In this case, the voltage withstand effect is better.

In one embodiment, as shown in FIG. 1, the metal oxide semiconductor field effect transistor has a plurality of first doped regions 160, and a plurality of the above-mentioned trenches are opened, and each trench is filled with the above-mentioned filling structure. The first doped regions 160 and the trenches are alternately arranged at intervals. In this embodiment, multiple trenches are provided to form multiple trench gate structures, which can increase the current density. A first doped region is provided between each trench. Under the joint action of the board, the distribution density of the depletion zone is increased, thereby further improving the pressure resistance.

Further, as shown in FIG. 3a, it is a cross-sectional view taken along the section line AA' in FIG. A plurality of first doped regions 160 are arranged side by side and spaced in the longitudinal direction. In this embodiment, the first doped regions 160 arranged between adjacent trenches are arranged in sections to reduce the space occupied by the first doped regions 160, thereby reducing the on-resistance of the device. In one embodiment, the depletion regions formed by the adjacent first doped regions 160 extend around and are connected to each other, so as to reduce the on-resistance and increase the voltage resistance of the device.

In another embodiment, as shown in FIG. 3b, it is a cross-sectional view taken along the section line AA' in FIG. There is a first doped region 160, and the first doped region 160 is elongated. In this embodiment, an elongated first doped region 160 is provided between adjacent trench gate structures, which can enhance the depletion capability of the first doped region 160 to the drift region 100 and enhance the withstand voltage of the device.

In one embodiment, as shown in FIG. 1, an interlayer dielectric layer 200 is also formed on the source region 111 and the trench. The interlayer dielectric layer 200 may specifically be silicon oxide, and the source extraction structure 310 penetrates the interlayer dielectric. The layer 200 and the source region 111 extend into the body region 110 to be connected to the source region 111 and the body region 110. The gate lead structure is formed directly above the trench, which penetrates the interlayer dielectric layer 200 and is connected to the second conductive structure 140 in the trench. Further, the gate lead-out structure and the source lead-out structure are staggered so as to be connected to the gate metal layer and the source metal layer respectively. The first conductive structure 130 may be an uncharged floating structure to form a floating inner field plate, or it may be electrically connected to the source to form a charged inner field plate.

In one embodiment, when preparing the source extraction structure 310, a source contact hole needs to be opened. In the actual process, the first doped region 160 is formed by implanting doped ions into the drift region through the source contact hole. The first doped region 160 is specifically formed in the orthographic projection area of the source extraction structure 310, or covers the orthographic projection area of the source extraction structure 310 and spreads evenly around the orthographic projection area from the orthographic projection area.

In one embodiment, as shown in FIG. 1, a second doped region 112 is further formed in the body region 110, the second doped region 112 has the second conductivity type, and the doping concentration of the second doped region 112 Higher than the doping concentration of the body region 110, the second doped region 112 is specifically located below the source region 111 and is spaced apart from the trench. The source extraction structure 310 penetrates the source region 111 and extends into the second doped region 112. The source lead-out structure 310 is connected to the source region 111, and its bottom is surrounded by the second doped region 112, thereby reducing the contact resistance between the source lead-out structure 310 and the body region 110.

The distribution of the first conductive structure 130 and the second conductive structure 140 of the trench 120 has various designs. In one embodiment, as shown in FIG. 1, in the trench, the first conductive structure 130 is distributed on the bottom of the trench, the second conductive structure 140 is distributed on the top of the trench, and the first conductive structure 130 and the second conductive structure 130 are distributed on the top of the trench. The conductive structures 140 are isolated by the isolation structure 150, wherein an oxide layer 120 is formed between the first conductive structure 130 and the inner wall of the trench and between the second conductive structure 140 and the inner wall of the trench. Specifically, the isolation structure 150 is silicon oxide. In this embodiment, the first conductive structure 130 at the bottom of the trench can not only adjust the electric field of the drift region, enhance the depletion of the drift region, but also reduce the parasitic capacitance between the gate and drain, and improve the performance of the device. Further, as shown in FIG. 1, in the trench, the top surface of the first conductive structure 130 and the bottom surface of the second conductive structure 140 are approximately flat surfaces. In another embodiment, as shown in FIG. 4a, in the trench, the middle of the top surface of the first conductive structure 130 is convex outward, and the middle of the bottom surface of the second conductive structure 140 is concave inward, so as to be consistent with the first conductive structure. The protrusion of 130 adapts.

In one embodiment, as shown in FIG. 4b, in the trench, the first conductive structure 130 extends from the top of the trench to the bottom of the trench, and an oxide layer 120 is formed between the first conductive structure 130 and the inner wall of the trench. The second conductive structure 140 is formed in the oxide layer 120 on both sides of the first conductive structure 130, the first conductive structure 130 and the second conductive structure 140 are separated by the oxide layer 120, and the first conductive structure 130 extends to the depth of the trench bottom It is greater than the depth of the second conductive structure 140 extending toward the bottom of the trench. In this embodiment, the second conductive structure 140 is provided in the oxide layer 120 to increase the thickness of the oxide layer 120, thereby enhancing the withstand voltage of the device.

This application also relates to a manufacturing method of a trench gate metal oxide semiconductor field effect transistor. As shown in FIG. 5, the manufacturing method includes the following steps:

Step S510: providing a semiconductor substrate and forming a drift region having the first conductivity type on the semiconductor substrate.

Step S520: Open a trench on the drift region, form an oxide layer on the inner wall of the trench, and fill the trench with a first conductive structure and a second conductive structure that are isolated from each other. The bottom depth of the conductive structure is greater than the bottom depth of the second conductive structure, and a portion of the first conductive structure whose depth exceeds the bottom depth of the second conductive structure is defined as a field plate adjustment structure.

As shown in FIG. 6a, the drift region 100 having the first conductivity type is formed by doping the semiconductor substrate. Specifically, the epitaxial layer on the semiconductor substrate may be doped to form the drift region 100 on the epitaxial layer.

Through photolithography and etching processes, a trench is opened on the drift region 100, and a filling structure is filled in the trench. Since the structures of the first conductive structure 130 and the second conductive structure 140 in the trench have various forms, correspondingly, the step of forming the first conductive structure 130 and the second conductive structure 140 in the trench also has various embodiments. In a specific embodiment, step S520 may include the following steps:

Step S521: A trench is opened on the drift region, and an oxide layer is formed on the inner wall of the trench.

As shown in FIG. 6a, an oxide layer 120 is formed on the inner wall of the trench. Specifically, the oxide layer 120 may be formed by thermal oxidation.

Step S522: Fill the trench with a first conductive structure.

Step S523: etch the first conductive structure and oxide layer at the top of the trench, and retain the first conductive structure and oxide layer at the bottom of the trench.

As shown in FIG. 6b, the first conductive structure 130 is filled into the trench. Specifically, the above-mentioned first conductive structure may be formed by a deposition process. The first conductive structure and the oxide layer on the top of the trench are etched, and the first conductive structure 130 at the bottom of the trench and the oxide layer 120 between the first conductive structure 130 and the sidewall of the trench are retained.

Step S524: forming an isolation structure in the trench, the isolation structure covering the first conductive structure at the bottom of the trench and not filling the trench.

As shown in FIG. 6c, a layer of isolation structure 150 is deposited in the trench through a deposition process. The isolation structure 150 may specifically be silicon oxide. The isolation structure 150 covers the first conductive structure 130 and does not fill the trench. .

Step S525: forming an oxide layer on the sidewall of the trench above the isolation structure and filling the trench with a second conductive structure.

As shown in FIG. 6d, an oxide layer is formed on the sidewall of the trench above the isolation structure 150 and the second conductive structure 140 is filled in the trench. The second conductive structure 140 is isolated from the inner wall of the trench by the oxide layer 120, and The second conductive structure 140 is isolated from the first conductive structure 130 by the isolation structure 150. In the filling structure formed through the above steps S521 to S525, the first conductive structure 130 located at the bottom of the trench is the field plate adjustment structure.

Step S530: Doping the upper surface layer of the drift region to form a body region with the second conductivity type in contact with the sidewall of the trench, the depth of the body region being smaller than the depth of the trench; The upper surface layer of the body region is doped to form a source region having the first conductivity type in contact with the sidewall of the trench.

As shown in FIG. 6e, the upper surface layer of the drift region 100 is doped to form a body region 110 of the second conductivity type in contact with the sidewall of the trench. The depth of the body region 110 is less than the depth of the trench, that is, the depth of the trench The bottom is still located in the drift zone 100. The upper surface layer of the body region 110 is doped to form a source region 111 having the first conductivity type in contact with the sidewall of the trench.

Step S540: forming a first doped region having a second conductivity type in the drift region, the first doped region is in contact with the body region, and the first doped region is spaced from the trench It is provided that the depth of the bottom of the first doped region exceeds the depth of the top of the field plate adjustment structure.

As shown in FIGS. 6e and 6f, in one embodiment, between step S530 and step S540, it further includes forming an interlayer dielectric layer 200 on the source region 111 and the trench, and etching the layers on both sides of the trench in turn The inter-dielectric layer 200, the source region 111 and the body region 110 form a source contact hole, and the source contact hole is spaced apart from the trench. In step S540, specifically, doping ions of the second conductivity type are injected into the drift region through the source contact hole, and a first doped region 160 in contact with the body region 110 is formed in the drift region. At this time, the first doped region The projected area of 160 is the same as the projected area of the source contact hole. In one embodiment, when dopant ions with the second conductivity type are implanted through the source contact hole to form the first doped region 160 in the drift region 100, the dopant with the second conductivity type is further injected through the source contact hole. The impurity ions form a second doped region 112 on the surface of the body region.

Step S550: forming a source extraction structure connected to the source region and the body region, and forming a gate extraction structure connected to the second conductive structure.

As shown in FIG. 6h, a source lead-out structure 310 connected to the source region 111 and the body region 110 is formed, and a gate lead-out structure connected to the second conductive structure 140 (not shown in the figure) is formed. In one embodiment, when the active contact hole is formed before step S550, in step S550, specifically, the source contact hole is filled with conductive material to form the source lead-out structure 310. In one embodiment, when the second doped region 112 is formed in the body region 110 through the source contact hole, the source contact hole is filled with conductive material to form the source lead-out structure 310, and the bottom of the source lead-out structure 310 is second Surrounding the doped region 112 can reduce the contact resistance between the source lead structure 310 and the body region.

In the above embodiment, the first doped region 160 is formed in the drift region 100 by the implantation process at the source contact hole. In other embodiments, the drift region 100 is grown by an epitaxial process. During the epitaxial growth The formation of the first doped region 160 can be specifically carried out in two ways:

The first way:

Epitaxially growing a first epitaxial layer on the semiconductor substrate;

Doping the first epitaxial layer to form a first doped region having a second conductivity type;

A second epitaxial layer is continuously grown epitaxially on the first epitaxial layer and the first doped region, and the drift region includes the first epitaxial layer and the second epitaxial layer.

As shown in FIGS. 7a to 7c, a first epitaxial layer 101 is epitaxially grown on a semiconductor substrate, and then a specific area of the first epitaxial layer 101 is doped with the second conductivity type to form a first epitaxial layer with the second conductivity type. Doped region 160, continue epitaxial growth of the second epitaxial layer 102 on the first epitaxial layer 101 and the first doped region 160, the first epitaxial layer 101 and the second epitaxial layer 102 will form the required drift region 110, at this time , The first doped region 160 is formed inside the drift region 110.

The second way:

Epitaxially growing a first epitaxial layer on the semiconductor substrate;

A shallow groove is formed on the first epitaxial layer, and a first doped region with a second conductivity type is epitaxially grown in the shallow groove;

The difference between the above-mentioned second method and the above-mentioned first method lies in the method of forming the first doped region 160 in the first epitaxial layer 101. In the first method, the specific area of the first epitaxial layer 101 is directly processed. Doping forms the first doped region 160. In the second method, a shallow trench is first opened in a specific area, and then the first doped region 160 with the second conductivity type is epitaxially grown in the shallow trench. It should be noted that the first doping regions can be formed in any of the above-mentioned methods, which can be flexibly selected according to specific conditions.

The above examples only express several implementation manners of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the scope of the invention patent. It should be pointed out that for those of ordinary skill in the art, without departing from the concept of this application, several modifications and improvements can be made, and these all fall within the protection scope of this application. Therefore, the scope of protection of the patent of this application shall be subject to the appended claims.

Claims

A trench gate metal oxide semiconductor field effect transistor, including:

The drift region has the first conductivity type and is formed on the semiconductor substrate;

The body region has the second conductivity type and is formed on the upper surface layer of the drift region;

The source region has the first conductivity type and is formed on the upper surface layer of the body region;

A trench that penetrates the source region and the body region in sequence and extends into the drift region;

The filling structure includes a first conductive structure and a second conductive structure filled in the trench and isolated from each other, and formed between the first conductive structure and the inner wall of the trench and the second conductive structure and In the oxide layer between the inner walls of the trench, the depth of the bottom of the first conductive structure exceeds the depth of the bottom of the second conductive structure, and the part of the first conductive structure that exceeds the depth of the bottom of the second conductive structure is a field Board adjustment structure;

The first doped region has the second conductivity type, is formed in the drift region and is in contact with the lower surface of the body region, the first doped region is spaced apart from the trench, and the first The depth of the bottom of the doped region exceeds the depth of the top of the field plate adjustment structure;

A source lead structure connected to the source region and the body region; and

The gate lead structure is connected to the second conductive structure.
The metal oxide semiconductor field effect transistor of claim 1, wherein the sidewall of the first doped region comprises a first portion extending downward from the bottom of the body region and parallel to the sidewall of the trench, and A second part extending downward from the first part and gradually inclined toward the inside of the first doped region, and an interface between the first part and the second part passes through the field plate adjusting structure.
7. The metal oxide semiconductor field effect transistor of claim 1, wherein the metal oxide semiconductor field effect transistor has a plurality of the first doped regions and is provided with a plurality of the trenches, each trench The groove is filled with the filling structure, and the first doped region and the groove are alternately arranged at intervals along the width direction of the groove.
The metal oxide semiconductor field effect transistor of claim 3, wherein the cross section of the trench is elongated, and adjacent trenches are arranged side by side and spaced along the length of the trench. Of the plurality of first doped regions.
The metal oxide semiconductor field effect transistor of claim 3, wherein the cross section of the trench is elongated, and the first elongated groove is formed between adjacent grooves. Doped area.
5. The metal oxide semiconductor field effect transistor of claim 1, further comprising:

An interlayer dielectric layer formed on the top surface of the source region and the trench;

Wherein, the source lead-out structure penetrates the interlayer dielectric layer and the source region and extends into the body region so as to be connected to the source region and the body region respectively; the gate lead-out structure It penetrates the interlayer dielectric layer and is connected to the second conductive structure.
3. The metal oxide semiconductor field effect transistor of claim 1, wherein the first conductive structure is an uncharged floating structure to form a floating inner field plate.
The metal oxide semiconductor field effect transistor of claim 1, wherein the first conductive structure is distributed on the bottom of the trench, the second conductive structure is distributed on the top of the trench, and the metal The oxide semiconductor field effect transistor also includes an isolation structure that isolates the first conductive structure from the second conductive structure.
The metal oxide semiconductor field effect transistor of claim 1, wherein the first conductive structure extends from the top of the trench to the bottom of the trench, and the second conductive structure is formed on the In the oxide layer on both sides of the first conductive structure, the first conductive structure and the second conductive structure are separated by the oxide layer, and the depth of the first conductive structure extending toward the bottom of the trench is greater than that of the trench. The depth of the second conductive structure extending toward the bottom of the trench.
The metal oxide semiconductor field effect transistor of claim 1, wherein a second doped region is formed in the body region, the second doped region has a second conductivity type, and the second doped region The doping concentration of the impurity region is higher than the doping concentration of the body region, the second doping region is located below the source region and spaced apart from the trench, and the source extraction structure penetrates the source And extend to the second doped area.
The metal oxide semiconductor field effect transistor of claim 1, wherein the first conductivity type is N-type, and the second conductivity type is P-type.
A method for preparing a trench gate metal oxide semiconductor field effect transistor includes:

Providing a semiconductor substrate and forming a drift region having a first conductivity type on the semiconductor substrate;

A trench is opened on the drift region, an oxide layer is formed on the inner wall of the trench, and a first conductive structure and a second conductive structure isolated from each other are filled in the trench, and the bottom of the first conductive structure The depth is greater than the depth of the bottom of the second conductive structure, and a portion of the first conductive structure whose depth exceeds the depth of the bottom of the second conductive structure is defined as a field plate adjustment structure;

The upper surface layer of the drift region is doped to form a body region with the second conductivity type in contact with the sidewall of the trench, the depth of the body region is smaller than the depth of the trench; The upper surface layer is doped to form a source region with the first conductivity type in contact with the sidewall of the trench;

A first doped region having a second conductivity type is formed in the drift region, the first doped region is in contact with the lower surface of the body region, and the first doped region is spaced from the trench Provided that the depth of the bottom of the first doped region exceeds the depth of the top of the field plate adjustment structure; and

A source lead-out structure connected to the source region and the body area is formed, and a gate lead-out structure connected to the second conductive structure is formed.
The preparation method according to claim 12, characterized in that, after the step of doping the upper surface layer of the body region to form the source region of the first conductivity type in contact with the sidewall of the trench, the method further comprises :

Forming an interlayer dielectric layer on the source region and the trench; and

Etching the interlayer dielectric layer, the source region and the body region sequentially to form a source contact hole that penetrates the dielectric layer and the source region and extends to the body region;

The forming a first doped region in the drift region that is in contact with the lower surface of the body region includes: implanting dopant ions of the second conductivity type into the drift region through the source contact hole, Forming a first doped region in the drift region that is in contact with the lower surface of the body region;

The forming the source lead-out structure connected with the source region, the body region and the first conductive structure includes: filling the source contact hole with a conductive material to form the source lead-out structure.
The manufacturing method according to claim 12, wherein forming a first doped region with the second conductivity type in the drift region comprises:

Epitaxially growing a first epitaxial layer on the semiconductor substrate;

Doping the first epitaxial layer to form a first doped region having a second conductivity type; and

A second epitaxial layer is continuously grown epitaxially on the first epitaxial layer and the first doped region, and the drift region includes the first epitaxial layer and the second epitaxial layer.
The manufacturing method according to claim 12, wherein forming a first doped region with the second conductivity type in the drift region comprises:

Epitaxially growing a first epitaxial layer on the semiconductor substrate;

A shallow trench is formed on the first epitaxial layer, and a first doped region having a second conductivity type is epitaxially grown in the shallow trench; and

A second epitaxial layer is continuously grown epitaxially on the first epitaxial layer and the first doped region, and the drift region includes the first epitaxial layer and the second epitaxial layer.