WO2021232813A1 - Transistor à effet de champ à semi-conducteur à oxyde métallique à grille en tranchée et son procédé de fabrication - Google Patents

Transistor à effet de champ à semi-conducteur à oxyde métallique à grille en tranchée et son procédé de fabrication Download PDF

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WO2021232813A1
WO2021232813A1 PCT/CN2020/140672 CN2020140672W WO2021232813A1 WO 2021232813 A1 WO2021232813 A1 WO 2021232813A1 CN 2020140672 W CN2020140672 W CN 2020140672W WO 2021232813 A1 WO2021232813 A1 WO 2021232813A1
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region
trench
conductive structure
source
conductivity type
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PCT/CN2020/140672
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Chinese (zh)
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方冬
肖魁
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华润微电子（重庆）有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • This application relates to the field of semiconductors, and in particular to a trench gate metal oxide semiconductor field effect transistor and a preparation method thereof.
  • MOS Metal Oxide Semiconductor Field Effect Transistor
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • a conduction channel is formed between the source and drain.
  • MOS Metal Oxide Semiconductor Field Effect Transistor
  • the existence of the conduction channel makes the metal oxide semiconductor field effect transistor have For a certain on-resistance, the greater the on-resistance, the greater the power consumption. Therefore, it is necessary to reduce the on-resistance as much as possible.
  • metal oxide semiconductor field effect transistors with a trench gate structure are usually used to form trenches.
  • the gate structure changes the conduction channel from the horizontal to the vertical, which greatly increases the cell density and reduces the on-resistance.
  • the on-resistance of the trench gate metal oxide semiconductor field effect transistor is further reduced. Becomes difficult.
  • a trench gate metal oxide semiconductor field effect transistor comprising: a drift region having a first conductivity type and formed on a semiconductor substrate; a body region having a second conductivity type and formed on an upper surface layer of the drift region;
  • the source region has the first conductivity type and is formed on the upper surface layer of the body region;
  • the trench penetrates the source region and the body region sequentially and extends to the drift region;
  • the filling structure includes filling in the body region.
  • the first conductive structure and the second conductive structure in the trench isolated from each other, and formed between the first conductive structure and the inner wall of the trench and between the second conductive structure and the inner wall of the trench
  • the bottom depth of the first conductive structure exceeds the bottom depth of the second conductive structure, and the portion of the first conductive structure whose depth exceeds the bottom depth of the second conductive structure is defined as the field plate adjustment structure;
  • the first doping Region having the second conductivity type, formed in the drift region and in contact with the lower surface of the body region, the first doped region and the trench are spaced apart, the first doped region
  • the bottom depth exceeds the top depth of the field plate adjustment structure;
  • the source extraction structure is connected to the source region and the body region; and the gate extraction structure is connected to the second conductive structure.
  • a semiconductor substrate is provided and a drift region with the first conductivity type is formed on the semiconductor substrate; a trench is opened on the drift region, an oxide layer is formed on the inner wall of the trench, and the trench Filled with a first conductive structure and a second conductive structure that are isolated from each other, the bottom depth of the first conductive structure is greater than the bottom depth of the second conductive structure, and the depth of the first conductive structure exceeds the depth of the bottom of the second conductive structure.
  • the upper surface layer of the drift region is doped to form a body region of the second conductivity type in contact with the sidewall of the trench, the depth of the body region is less than the depth of the trench Doping the upper surface layer of the body region to form a source region of the first conductivity type in contact with the sidewall of the trench; forming a first doped region of the second conductivity type in the drift region, The first doped region is connected to the body region, the first doped region is spaced apart from the trench, and the bottom depth of the first doped region exceeds the top depth of the field plate adjustment structure And forming a source lead-out structure connected to the source region and the body region, and a gate lead-out structure connected to the second conductive structure.
  • FIG. 1 is a partial side cross-sectional view of a trench gate metal oxide semiconductor field effect transistor cell region in an embodiment of this application;
  • FIG. 2 is a partial side cross-sectional view of a trench gate metal oxide semiconductor field effect transistor cell region in another embodiment of the application;
  • FIG. 3a is a cross-sectional view of a trench gate metal oxide semiconductor field effect transistor along the line A-A' in FIG. 1 in an embodiment of the application;
  • FIG. 3b is a cross-sectional view of a trench gate metal oxide semiconductor field effect transistor along the A-A' section line in FIG. 1 in another embodiment of the application;
  • 4a is a schematic diagram of the structure in the trench in an embodiment of the application.
  • 4b is a schematic diagram of the structure in the trench in another embodiment of the application.
  • FIG. 5 is a flow chart of the steps of a method for manufacturing a trench gate metal oxide semiconductor field effect transistor in an embodiment of the application;
  • 6a to 6h are structural cross-sectional views corresponding to relevant steps of a method for manufacturing a trench gate metal oxide semiconductor field effect transistor in an embodiment of the application;
  • 7a to 7c are cross-sectional views of the structure corresponding to the steps of forming the first doped region in an embodiment of the application.
  • drift region 101 first epitaxial layer; 102 second epitaxial layer; 110 body region; 111 source region; 112 second doped region; 120 oxide layer; 130 first conductive structure; 140 second conductive structure; 150 isolation structure ; 160 first doped region; 200 interlayer dielectric layer; 310 source lead structure.
  • the trench gate metal oxide semiconductor field effect transistor includes a drift region 100 formed on a semiconductor substrate, and the drift region may specifically be formed by epitaxial growth of the semiconductor substrate.
  • a body region 110 is formed on the upper surface of the drift region 100, and an active region 111 is formed on the upper surface of the body region 110.
  • the source region 111 is provided with a trench that penetrates the source region 111 and the body region 110 and extends into the drift region 100, that is, the bottom end of the trench is located in the drift region 100.
  • the trench is filled with a first conductive structure 130 and a second conductive structure 140 that are isolated from each other.
  • An oxide layer 120 is formed between the first conductive structure 130 and the inner wall of the trench and between the second conductive structure 140 and the inner wall of the trench.
  • the oxide layer 120 located between the first conductive structure 130 and the inner wall of the trench is a gate oxide layer
  • the oxide layer located between the second conductive structure 140 and the inner wall of the trench is an isolation oxide layer, which is filled in the trench.
  • the depth of the first conductive structure 130 is greater than the depth of the second conductive structure 140, that is, the distance between the first conductive structure 130 and the bottom of the trench is smaller than the distance between the second conductive structure 140 and the bottom of the trench, which defines the first A portion of the conductive structure 130 whose depth exceeds the depth of the bottom of the second conductive structure 140 is a field plate adjustment structure, that is, the portion of the first conductive structure under the second conductive structure 140 is a field plate adjustment structure.
  • a first doped region 160 is also formed in the drift region 100.
  • the top of the first doped region 160 is connected to the body region 110, and the first doped region 160 is spaced apart from the trench.
  • the bottom of the first doped region 160 is deep Exceeding the top depth of the field plate adjustment structure, that is, the lateral projection of the first doped region 160 and the field plate adjustment structure has an overlapping area.
  • the trench gate metal oxide semiconductor field effect transistor also includes a source lead-out structure 310 and a gate lead-out structure (not shown in the figure).
  • the source lead-out structure 310 and the gate lead-out structure can be metal pillars, specifically tungsten metal .
  • the source lead structure 310 is connected to the source region 111 and the body region 110, and the gate lead structure is connected to the second conductive structure 140 in the trench.
  • the drift region 100 and the source region 111 have a first conductivity type, and the body region 110 and the first doped region 160 have a second conductivity type.
  • the first conductivity type is N type
  • the second conductivity type is P type
  • the first conductivity type is P type
  • the second conductivity type is N type.
  • the front side of the trench gate metal oxide semiconductor field effect transistor should also have a source metal layer and a gate metal layer that are isolated from each other.
  • the source extraction structure 310 is connected to the source metal layer.
  • the lead structures are all connected with the gate metal layer, and a drain metal layer is also formed on the back of the trench gate metal oxide semiconductor field effect transistor.
  • the top source region 111 is connected to the source metal layer through the source extraction structure 310, and the bottom drift region 100 is used as the drain region to connect to the drain metal layer, and the middle
  • the body region 110 forms a channel region.
  • the trench penetrates the body region 110 and extends into the drift region 100.
  • the electrode metal layer is connected, that is, the trench and the gate oxide layer inside the trench and the second conductive structure 140 form a trench gate structure, thereby forming a trench gate metal oxide semiconductor field effect transistor.
  • a longitudinal conductive channel can be formed in the body region 110.
  • a first conductive structure 130 is also formed in the bottom of the trench.
  • the first conductive structure part located under the second conductive structure 140 is a field plate adjustment structure, and the field plate adjustment structure and the isolation oxide layer in contact therewith are formed
  • the inner field plate can adjust the electric field distribution inside the drift region 100, so that the drift region in contact with the inner field plate forms a depletion region, thereby enhancing the depletion of the drift region 100.
  • a first doped region 160 is formed in the drift region 100.
  • the first doped region 160 has a source potential and has a conductivity type opposite to that of the drift region 100.
  • the first doped region 160 and the drift region 100 form a reverse PN Therefore, the drift region in contact with the first doped region 160 also forms a depletion region, which further enhances the depletion of the drift region 100.
  • the depth of the bottom of the first doping region 160 exceeds the depth of the top of the field plate adjustment structure, so that the depletion region formed by the first doping region 160 and the depletion region formed by the inner field plate are laterally distributed side by side, The withstand voltage of the drift region 100 is further increased.
  • the trench gate metal oxide semiconductor field effect transistors in this application have a higher breakdown voltage, that is, under the condition of ensuring the same breakdown voltage
  • the drift region 100 of the trench gate MOSFET in the present application can have a higher doping concentration. Therefore, the trench gate MOSFET in the present application also has a lower doping concentration. ⁇ On-resistance.
  • the first conductive structure 130 connected to the source metal layer is closer to the bottom of the trench than the second conductive structure 140 connected to the gate, which can reduce the parasitic capacitance between the gate and drain, so that The device has better characteristics.
  • the sidewall of the first doped region 160 includes a first portion 161 extending downward from the bottom of the body region 110 and a first portion 162 extending downward from the first portion, wherein the first portion 161 is parallel to the sidewall of the trench, the longitudinal section of the first part 161 is rectangular, and the distance between the first part 161 and the sidewall of the trench is equal; the second part 162 gradually moves from top to bottom to the inside of the first doped region 160 Inclined, the longitudinal section of the second part 162 is inverted trapezoid or inverted triangle, and the distance between the second part 162 and the sidewall of the trench gradually increases from top to bottom.
  • the interface between the first part 161 and the second part 162 passes through the field plate adjustment structure, that is, passes through the first conductive structure 130 in the trench but does not pass through the second conductive structure 140.
  • the first doped region 160 needs to be spaced apart from the trench, that is, the first doped region 160 needs to be spaced apart from the trench gate to allow current between the drain and the source to pass.
  • the metal oxide semiconductor field effect transistor since the body region 110 only forms a narrow channel region near the sidewall of the trench for current to pass, in the drift region 100, the current density near the trench is also the largest. The farther the trench is, the lower the current density.
  • the first doped region 160 can be located in a region with a low current density to reduce the blocking effect on current, that is, to increase the distance between the first doped region 160 and the trench is It is beneficial to reduce the on-resistance of VDMOS. However, the greater the distance between the first doped region 160 and the field plate adjustment structure, the greater the distance between adjacent depletion layers, and thus the weaker the voltage withstand capability.
  • the distance between the upper sidewall of the first doped region 160 and the field plate adjustment structure is smaller, and a densely distributed depletion layer is formed, while the lower part
  • the sidewalls are gradually inclined inward to increase the distance between the first doped region and the trench, that is, to reduce the area of the first doped region 160, so as to ensure the withstand voltage capability and reduce the on-resistance of the device.
  • the depletion layer formed in the first doped region 160 and the depletion layer formed in the inner field plate extend around and connect to each other. In this case, the voltage withstand effect is better.
  • the metal oxide semiconductor field effect transistor has a plurality of first doped regions 160, and a plurality of the above-mentioned trenches are opened, and each trench is filled with the above-mentioned filling structure.
  • the first doped regions 160 and the trenches are alternately arranged at intervals.
  • multiple trenches are provided to form multiple trench gate structures, which can increase the current density.
  • a first doped region is provided between each trench. Under the joint action of the board, the distribution density of the depletion zone is increased, thereby further improving the pressure resistance.
  • FIG. 3a it is a cross-sectional view taken along the section line AA' in FIG.
  • a plurality of first doped regions 160 are arranged side by side and spaced in the longitudinal direction.
  • the first doped regions 160 arranged between adjacent trenches are arranged in sections to reduce the space occupied by the first doped regions 160, thereby reducing the on-resistance of the device.
  • the depletion regions formed by the adjacent first doped regions 160 extend around and are connected to each other, so as to reduce the on-resistance and increase the voltage resistance of the device.
  • FIG. 3b it is a cross-sectional view taken along the section line AA' in FIG.
  • an elongated first doped region 160 is provided between adjacent trench gate structures, which can enhance the depletion capability of the first doped region 160 to the drift region 100 and enhance the withstand voltage of the device.
  • an interlayer dielectric layer 200 is also formed on the source region 111 and the trench.
  • the interlayer dielectric layer 200 may specifically be silicon oxide, and the source extraction structure 310 penetrates the interlayer dielectric.
  • the layer 200 and the source region 111 extend into the body region 110 to be connected to the source region 111 and the body region 110.
  • the gate lead structure is formed directly above the trench, which penetrates the interlayer dielectric layer 200 and is connected to the second conductive structure 140 in the trench. Further, the gate lead-out structure and the source lead-out structure are staggered so as to be connected to the gate metal layer and the source metal layer respectively.
  • the first conductive structure 130 may be an uncharged floating structure to form a floating inner field plate, or it may be electrically connected to the source to form a charged inner field plate.
  • the first doped region 160 is formed by implanting doped ions into the drift region through the source contact hole.
  • the first doped region 160 is specifically formed in the orthographic projection area of the source extraction structure 310, or covers the orthographic projection area of the source extraction structure 310 and spreads evenly around the orthographic projection area from the orthographic projection area.
  • a second doped region 112 is further formed in the body region 110, the second doped region 112 has the second conductivity type, and the doping concentration of the second doped region 112 Higher than the doping concentration of the body region 110, the second doped region 112 is specifically located below the source region 111 and is spaced apart from the trench.
  • the source extraction structure 310 penetrates the source region 111 and extends into the second doped region 112.
  • the source lead-out structure 310 is connected to the source region 111, and its bottom is surrounded by the second doped region 112, thereby reducing the contact resistance between the source lead-out structure 310 and the body region 110.
  • the distribution of the first conductive structure 130 and the second conductive structure 140 of the trench 120 has various designs.
  • the first conductive structure 130 is distributed on the bottom of the trench
  • the second conductive structure 140 is distributed on the top of the trench
  • the first conductive structure 130 and the second conductive structure 130 are distributed on the top of the trench.
  • the conductive structures 140 are isolated by the isolation structure 150, wherein an oxide layer 120 is formed between the first conductive structure 130 and the inner wall of the trench and between the second conductive structure 140 and the inner wall of the trench.
  • the isolation structure 150 is silicon oxide.
  • the first conductive structure 130 at the bottom of the trench can not only adjust the electric field of the drift region, enhance the depletion of the drift region, but also reduce the parasitic capacitance between the gate and drain, and improve the performance of the device.
  • the top surface of the first conductive structure 130 and the bottom surface of the second conductive structure 140 are approximately flat surfaces.
  • the middle of the top surface of the first conductive structure 130 is convex outward, and the middle of the bottom surface of the second conductive structure 140 is concave inward, so as to be consistent with the first conductive structure.
  • the protrusion of 130 adapts.
  • the first conductive structure 130 extends from the top of the trench to the bottom of the trench, and an oxide layer 120 is formed between the first conductive structure 130 and the inner wall of the trench.
  • the second conductive structure 140 is formed in the oxide layer 120 on both sides of the first conductive structure 130, the first conductive structure 130 and the second conductive structure 140 are separated by the oxide layer 120, and the first conductive structure 130 extends to the depth of the trench bottom It is greater than the depth of the second conductive structure 140 extending toward the bottom of the trench.
  • the second conductive structure 140 is provided in the oxide layer 120 to increase the thickness of the oxide layer 120, thereby enhancing the withstand voltage of the device.
  • This application also relates to a manufacturing method of a trench gate metal oxide semiconductor field effect transistor. As shown in FIG. 5, the manufacturing method includes the following steps:
  • Step S510 providing a semiconductor substrate and forming a drift region having the first conductivity type on the semiconductor substrate.
  • Step S520 Open a trench on the drift region, form an oxide layer on the inner wall of the trench, and fill the trench with a first conductive structure and a second conductive structure that are isolated from each other.
  • the bottom depth of the conductive structure is greater than the bottom depth of the second conductive structure, and a portion of the first conductive structure whose depth exceeds the bottom depth of the second conductive structure is defined as a field plate adjustment structure.
  • the drift region 100 having the first conductivity type is formed by doping the semiconductor substrate.
  • the epitaxial layer on the semiconductor substrate may be doped to form the drift region 100 on the epitaxial layer.
  • step S520 may include the following steps:
  • Step S521 A trench is opened on the drift region, and an oxide layer is formed on the inner wall of the trench.
  • an oxide layer 120 is formed on the inner wall of the trench.
  • the oxide layer 120 may be formed by thermal oxidation.
  • Step S522 Fill the trench with a first conductive structure.
  • Step S523 etch the first conductive structure and oxide layer at the top of the trench, and retain the first conductive structure and oxide layer at the bottom of the trench.
  • the first conductive structure 130 is filled into the trench.
  • the above-mentioned first conductive structure may be formed by a deposition process.
  • the first conductive structure and the oxide layer on the top of the trench are etched, and the first conductive structure 130 at the bottom of the trench and the oxide layer 120 between the first conductive structure 130 and the sidewall of the trench are retained.
  • Step S524 forming an isolation structure in the trench, the isolation structure covering the first conductive structure at the bottom of the trench and not filling the trench.
  • a layer of isolation structure 150 is deposited in the trench through a deposition process.
  • the isolation structure 150 may specifically be silicon oxide.
  • the isolation structure 150 covers the first conductive structure 130 and does not fill the trench. .
  • Step S525 forming an oxide layer on the sidewall of the trench above the isolation structure and filling the trench with a second conductive structure.
  • an oxide layer is formed on the sidewall of the trench above the isolation structure 150 and the second conductive structure 140 is filled in the trench.
  • the second conductive structure 140 is isolated from the inner wall of the trench by the oxide layer 120, and
  • the second conductive structure 140 is isolated from the first conductive structure 130 by the isolation structure 150.
  • the first conductive structure 130 located at the bottom of the trench is the field plate adjustment structure.
  • Step S530 Doping the upper surface layer of the drift region to form a body region with the second conductivity type in contact with the sidewall of the trench, the depth of the body region being smaller than the depth of the trench; The upper surface layer of the body region is doped to form a source region having the first conductivity type in contact with the sidewall of the trench.
  • the upper surface layer of the drift region 100 is doped to form a body region 110 of the second conductivity type in contact with the sidewall of the trench.
  • the depth of the body region 110 is less than the depth of the trench, that is, the depth of the trench The bottom is still located in the drift zone 100.
  • the upper surface layer of the body region 110 is doped to form a source region 111 having the first conductivity type in contact with the sidewall of the trench.
  • Step S540 forming a first doped region having a second conductivity type in the drift region, the first doped region is in contact with the body region, and the first doped region is spaced from the trench It is provided that the depth of the bottom of the first doped region exceeds the depth of the top of the field plate adjustment structure.
  • step S530 and step S540 it further includes forming an interlayer dielectric layer 200 on the source region 111 and the trench, and etching the layers on both sides of the trench in turn
  • the inter-dielectric layer 200, the source region 111 and the body region 110 form a source contact hole, and the source contact hole is spaced apart from the trench.
  • step S540 specifically, doping ions of the second conductivity type are injected into the drift region through the source contact hole, and a first doped region 160 in contact with the body region 110 is formed in the drift region. At this time, the first doped region
  • the projected area of 160 is the same as the projected area of the source contact hole.
  • the dopant with the second conductivity type when dopant ions with the second conductivity type are implanted through the source contact hole to form the first doped region 160 in the drift region 100, the dopant with the second conductivity type is further injected through the source contact hole.
  • the impurity ions form a second doped region 112 on the surface of the body region.
  • Step S550 forming a source extraction structure connected to the source region and the body region, and forming a gate extraction structure connected to the second conductive structure.
  • a source lead-out structure 310 connected to the source region 111 and the body region 110 is formed, and a gate lead-out structure connected to the second conductive structure 140 (not shown in the figure) is formed.
  • the source contact hole is filled with conductive material to form the source lead-out structure 310.
  • the source contact hole is filled with conductive material to form the source lead-out structure 310, and the bottom of the source lead-out structure 310 is second Surrounding the doped region 112 can reduce the contact resistance between the source lead structure 310 and the body region.
  • the first doped region 160 is formed in the drift region 100 by the implantation process at the source contact hole.
  • the drift region 100 is grown by an epitaxial process. During the epitaxial growth The formation of the first doped region 160 can be specifically carried out in two ways:
  • a second epitaxial layer is continuously grown epitaxially on the first epitaxial layer and the first doped region, and the drift region includes the first epitaxial layer and the second epitaxial layer.
  • a first epitaxial layer 101 is epitaxially grown on a semiconductor substrate, and then a specific area of the first epitaxial layer 101 is doped with the second conductivity type to form a first epitaxial layer with the second conductivity type.
  • Doped region 160 continue epitaxial growth of the second epitaxial layer 102 on the first epitaxial layer 101 and the first doped region 160, the first epitaxial layer 101 and the second epitaxial layer 102 will form the required drift region 110, at this time , The first doped region 160 is formed inside the drift region 110.
  • a shallow groove is formed on the first epitaxial layer, and a first doped region with a second conductivity type is epitaxially grown in the shallow groove;
  • a second epitaxial layer is continuously grown epitaxially on the first epitaxial layer and the first doped region, and the drift region includes the first epitaxial layer and the second epitaxial layer.
  • the difference between the above-mentioned second method and the above-mentioned first method lies in the method of forming the first doped region 160 in the first epitaxial layer 101.
  • the specific area of the first epitaxial layer 101 is directly processed. Doping forms the first doped region 160.
  • the second method a shallow trench is first opened in a specific area, and then the first doped region 160 with the second conductivity type is epitaxially grown in the shallow trench. It should be noted that the first doping regions can be formed in any of the above-mentioned methods, which can be flexibly selected according to specific conditions.

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  • Electrodes Of Semiconductors (AREA)

Abstract

L'invention concerne un transistor à effet de champ à semi-conducteur à oxyde métallique à grille en tranchée et son procédé de fabrication. Le transistor à effet de champ à semi-conducteur à oxyde métallique à grille en tranchée comprend : une région de dérive (100) ayant un premier type de conductivité ; une région massive (110) ayant un second type de conductivité et étant formée dans la région de dérive (100) ; une région de source (111) ayant le premier type de conductivité et étant formée dans la région massive (110), la région de source (111) étant pourvue d'une tranchée s'étendant dans la région de dérive (100), la tranchée étant remplie d'une première structure conductrice (130) et d'une seconde structure conductrice (140) isolées l'une de l'autre, une partie de fond de la première structure conductrice (130) ayant une profondeur supérieure à une profondeur d'une partie de fond de la seconde structure conductrice (140), et une structure de réglage de plaque de champ étant définie en tant que partie de la première structure conductrice (130) qui a une profondeur supérieure à la profondeur de la partie de fond de la seconde structure conductrice (140) ; et une première région de dopage (160) ayant le second type de conductivité, formée dans la région de dérive (100), et venant en butée contre la région massive (110), une partie de fond de la première région de dopage (160) ayant une profondeur supérieure à une profondeur d'une partie supérieure de la structure de réglage de plaque de champ, la région de source (111) et la région massive (110) étant connectées à une source, et la seconde structure conductrice (140) étant connectée à une grille.
PCT/CN2020/140672 2020-05-18 2020-12-29 Transistor à effet de champ à semi-conducteur à oxyde métallique à grille en tranchée et son procédé de fabrication WO2021232813A1 (fr)

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