CN102610643A - 沟槽金属氧化物半导体场效应晶体管器件 - Google Patents

沟槽金属氧化物半导体场效应晶体管器件 Download PDF

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CN102610643A
CN102610643A CN2011104288550A CN201110428855A CN102610643A CN 102610643 A CN102610643 A CN 102610643A CN 2011104288550 A CN2011104288550 A CN 2011104288550A CN 201110428855 A CN201110428855 A CN 201110428855A CN 102610643 A CN102610643 A CN 102610643A
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epitaxial loayer
insulating barrier
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CN102610643B (zh
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张磊
唐纳德·R·迪斯尼
李铁生
马荣耀
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Chengdu Monolithic Power Systems Co Ltd
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Abstract

公开了一种沟槽金属氧化物半导体场效应晶体管器件。该器件包括：衬底；外延层；沟槽；第一绝缘层，其覆盖所述沟槽的下部分内表面；第二绝缘层，其覆盖所述沟槽的上部分内表面和所述第一绝缘层，其中，所述第二绝缘层的厚度小于所述第一绝缘层的厚度；多晶硅区域，位于所述沟槽内，且下表面被所述第一绝缘层覆盖，其侧壁被所述第一绝缘层或第二绝缘层覆盖；栅极，其侧壁和下表面被所述第二绝缘层覆盖；至少一个柱状结构，位于所述外延层内，且其侧壁和下表面被所述外延层覆盖，其中，所述至少一个柱状结构沿外延层纵向排列；体区；重掺杂区域和源极。本发明提出的沟槽金属氧化物半导体场效应晶体管器件，可提高击穿电压和降低导通电阻。

Description

沟槽金属氧化物半导体场效应晶体管器件
技术领域
本发明的实施例涉及半导体器件，更具体地，本发明的实施例涉及沟槽金属氧化物半导体场效应晶体管器件。
背景技术
目前，功率器件被广泛应用于开关电源、汽车电子、工业控制等领域。沟槽金属氧化物半导体场效应晶体管(Trench-gate MOSFET)由于提高了单位面积芯片内的沟道总宽度，从而减小了漏源导通电阻Rds(on)而得到广泛应用。然而，在传统的沟槽MOSFET器件中，存在击穿电压BV和导通电阻Rds(on)之间相互制约的问题，提高击穿电压BV和降低导通电阻Rds(on)往往不能同时实现，这就导致器件在大电压下工作时会有很大的能量损耗。
发明内容
针对现有技术中的一个或多个问题，本发明的目的是提供一种沟槽金属氧化物半导体场效应晶体管器件，包括：第一导电类型的衬底；第一导电类型的外延层，位于所述衬底上，且其掺杂浓度小于所述衬底的掺杂浓度；沟槽，从所述外延层的上表面垂直向所述外延层的下表面延伸，且其未接触所述衬底的表面；第一绝缘层，位于所述沟槽内，且覆盖所述沟槽的下部分内表面；第二绝缘层，位于所述沟槽内，且覆盖所述沟槽的上部分内表面和所述第一绝缘层，其中，所述第二绝缘层的厚度小于所述第一绝缘层的厚度；多晶硅区域，位于所述沟槽内，且下表面被所述第一绝缘层覆盖，其侧壁被所述第一绝缘层或第二绝缘层覆盖；栅极，位于所述沟槽内，从所述外延层的上表面垂直向所述外延层的下表面延伸，且其侧壁和下表面被所述第二绝缘层覆盖；至少一个第二导电类型的柱状结构，位于所述外延层内，且其侧壁和下表面被所述外延层覆盖，其中，所述至少一个第二导电类型的柱状结构沿外延层纵向排列；第二导电类型的体区，其侧壁和所述沟槽的相邻侧壁相接触，且体区的下表面距离外延层上表面的距离小于栅极下表面距离外延层上表面的距离，其中，所述体区的掺杂浓度大于所述柱状结构的掺杂浓度；第一导电类型的重掺杂区域，其位于所述体区内且和所述沟槽的相邻侧壁相邻，且其掺杂浓度大于所述外延层的掺杂浓度；和源极，其位于所述体区内，从所述外延层的上表面垂直向所述体区延伸，且与第一导电类型的重掺杂区域相接触。
依据本发明提出的沟槽金属氧化物半导体场效应晶体管器件，可提高击穿电压和降低导通电阻。
附图说明
下面的附图表明了本发明的实施方式。这些附图和实施方式以非限制性、非穷举性的方式提供了本发明的一些实施例，其中：
图1示意性地示出了依据本发明一实施例的N沟道沟槽MOSFET器件；
图2示意性地示出了依据本发明一优选实施例的N沟道沟槽MOSFET器件；
图3示意性地示出了依据本发明另一实施例的N沟道沟槽MOSFET器件；
图4示意性地示出了依据本发明另一实施例的N沟道沟槽MOSFET器件；
图5示意性地示出了依据本发明另一实施例的N沟道沟槽MOSFET器件；以及
图6示意性地示出了在生产制造中，依据本发明实施例的具有多个重复单元的N沟道沟槽MOSFET器件。
具体实施方式
以下将参照附图更详细地描述本发明。在各个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的各个部分没有按比例绘制。
下面详细说明本发明实施例的新型沟槽MOSFET器件。在接下来的说明中，一些具体的细节，例如实施例中的具体掺杂类型，都用于对本发明的实施例提供更好的理解。本技术领域的技术人员可以理解，即使在缺少一些细节或者其他方法、材料等结合的情况下，本发明的实施例也可以被实现。
为减小击穿电压BV与导通电阻Rds(on)之间的矛盾，本发明提出了一种新型的沟槽金属氧化物半导体场效应晶体管(MOSFET)器件，其包括超结(super junction)结构和容性耗尽(capacitively depleted)结构。利用该包括超结结构和容性耗尽结构的沟槽MOSFET器件，可以有效减少击穿电压BV和导通电阻Rds(on)之间的矛盾，提高器件性能。
在接下来的描述中，以N沟道沟槽MOSFET器件为例，对其结构和性能进行详细描述。然而，本领域技术人员应当理解，所述结构和性能同样适用于P沟道沟槽MOSFET器件，为避免累述，本发明不再详细描述。
图1示出依据本发明一实施例的N沟道沟槽MOSFET器件。如图1所示，所述N沟道沟槽MOSFET器件包括N+衬底100以及形成于N+衬底100上的N-外延层101。该N沟道沟槽MOSFET器件还包括沟槽102，其从所述N-外延层101的上表面垂直向下延伸至所述N+衬底100上方，且其未接触所述N+衬底100的表面。沟槽102内包括第一绝缘层103和第二绝缘层109，其分别覆盖所述沟槽的下部分内表面和上部分内表面，其中，所述第一绝缘层103的厚度大于第二绝缘层109的厚度。沟槽102内还包括多晶硅区域104，所述多晶硅区域104被所述第一绝缘层103完全覆盖。沟槽102内还包括栅极G，其从所述沟槽102的上表面垂直向下延伸至所述多晶硅区域104上方，且其侧壁和下表面分别被所述第二绝缘层109和所述第一绝缘层103覆盖。所述N沟道沟槽MOSFET器件还包括P型柱状结构105，其形成于所述N-外延层101内，且其侧壁和下表面被所述N-外延层101覆盖。所述N沟道沟槽MOSFET器件还包括P型体区106，下表面覆盖所述柱状结构的上表面且和所述外延层相接触，其侧壁和所述沟槽的相邻侧壁相接触，且体区的下表面距离外延层上表面的距离小于栅极下表面距离外延层上表面的距离，其中，所述P型体区106的浓度大于所述P型柱状结构105的浓度。所述N沟道沟槽MOSFET器件还包括位于所述P型体区106内的P型重掺杂区107，其未接触P型体区106的表面，且所述P型重掺杂区107的掺杂浓度大于所述P型体区106。P型体区106内还包括N型重掺杂区108，其位于所述P型重掺杂区107的上方且由所述N沟道沟槽MOSFET器件的上表面垂直向下延伸，所述N型重掺杂区108与沟槽102的相邻侧壁相接触，其中，所述N型重掺杂区108的掺杂浓度大于所述N-外延层101的浓度。所述N沟道沟槽MOSFET器件还包括位于所述P型体区106内的源极金属接触S，其从所述N-外延层101的上表面垂直向下延伸至和所述P型重掺杂区107以及N型重掺杂区108相接触。
对于传统N沟道沟槽MOSFET，在截止状态下，源极S接地，漏极D加上正向电压，所加电压主要由P型体区和N型外延层所形成的PN结承担。如图1所示，依据该实施例的N沟道沟槽MOSFET器件具有由P型柱状结构105形成的超结结构。由于设置了相对P型体区106浓度较低的P型柱状结构105，因此，P型柱状结构105和N-外延层101形成的PN结能承受较大的电压，因而形成的击穿电压BV比传统N沟道沟槽MOSFET的击穿电压BV增大。另一方面，和传统沟槽MOSFET相比，超结沟槽MOSFET的外延层掺杂浓度可以更高，因而，在导通状态，传导电流流过外延层时的导通电阻Rds(on)将更小。
如图1所示，依据该实施例的N沟道沟槽MOSFET器件具有由多晶硅区域104、第一绝缘层103以及N-外延层101构成的容性耗尽结构。由MOS电容器原理可知，多晶硅区域104、第一绝缘层103以及N-外延层101构成电容器，其中，多晶硅区域104和N-外延层101是该电容器的极板，第一绝缘层103是该电容器的电介质。在图1所示实施例中，将多晶硅区域104连接至源极，则当漏极D加上正电压，源极S连接至地时，N-外延层101中将出现由多晶硅区域104、第一绝缘层103以及N-外延层101作用而形成的容性耗尽区域。该容性耗尽区域和P型体区106与N-外延层101以及P型柱状结构105与N-外延层101形成的PN结一起作用，使得在相同外加漏极电压下，依据本实施例的器件内的耗尽区域比传统结构器件的耗尽区域更宽，从而提高了击穿电压BV。另外，利用本发明提出的器件，N-外延层101的掺杂浓度可以更高，从而降低导通电阻，该作用在高电压应用场合尤其明显。另外，由于在沟槽中增加多晶硅区域，则由栅极、漏极以及N型外延层形成的寄生电容很小。
优选地，P型体区106、P型柱状结构105以及N-外延层101选择合适的浓度与宽度，则在某一外加漏极电压下，P型柱状结构105和多晶硅区域104之间的N-外延层101被完全耗尽，从而使器件获得更大击穿电压BV。
在图1所示实施例中，多晶硅区域104连接至源极，并连接至地。但在其它实施例中，多晶硅区域104亦可单独连接至一小于外加漏极电压值的电压。而对于P沟道沟槽MOSFET器件，多晶硅区域亦可单独连接至一大于外加漏极电压值的电压。
图1所示实施例详细描述了由P型体区106、P型重掺杂区107、N型重掺杂区108以及金属源极S构成的有源区的一种结构，本领域的技术人员应当理解，即使改变P型体区106、P型重掺杂区107、N型重掺杂区108以及金属源极S的形状、结构或相对位置，甚至在缺少P型重掺杂区107的情况下，有源区仍然可由具有相同功能的结构实现。
图2示出依据本发明一优选实施例的N沟道沟槽MOSFET器件。和图1所示实施例中的N沟道沟槽MOSFET器件相比，该优选实施例的N沟道沟槽MOSFET器件中的P型柱状结构105、沟槽102以及多晶硅区域104深入N-外延层101至接近N-外延层101表面处，以使得耗尽区域纵向较大，从而获得较大的击穿电压BV。
图3示出依据本发明另一实施例的N沟道沟槽MOSFET器件。和图1所示实施例相比，图3所示实施例中的多晶硅区域104和栅极G的位置有所不同。具体地，如图3所示，在沟槽102中填充第一绝缘层103和第二绝缘层109，其分别覆盖所述沟槽的下部分内表面和上部分内表面，其中，所述第一绝缘层103的厚度大于第二绝缘层109的厚度。沟槽102中包括多晶硅区域104，其从所述N-外延层101的上表面垂直向下延伸，其下部分侧壁和下表面被所述第一绝缘层103覆盖，且其上部分侧壁被所述第二绝缘层109覆盖。沟槽102中还包括栅极G，其从所述N-外延层101的上表面垂直向下延伸，其侧壁被所述第一绝缘层103覆盖，且其下表面被所述第二绝缘层109覆盖。
本领域技术人员应当理解，图1~3示出依据本发明实施例的两种超结沟槽MOSFET器件结构，该两种结构示出了沟槽内包括的多晶硅区域和栅极的不同形状或结构。然而，该两种结构并不用于限制本发明，本技术领域的技术人员应当理解，在改变多晶硅区域和栅极的形状、结构或相对位置的情况下，本发明亦可采用任何其它变形结构得以实现。
图4示出依据本发明另一实施例的N沟道沟槽MOSFET器件。如图4所示，和图1所示实施例相比，依据图4所示实施例的N沟道沟槽MOSFET器件中包括多个多晶硅区域104，其位于沟槽102内，且被第一绝缘层103覆盖，多个多晶硅区域104沿沟槽纵向排列。和前述原理相同，多个多晶硅区域104和第一绝缘层103以及N-外延层101之间形成电容器，从而产生容性耗尽区域。所述容性耗尽区域和P型体区106与N-外延层101以及P型柱状结构105与N-外延层101形成的PN结一起作用，使得在相同外加漏极电压下，依据本实施例的器件内的耗尽区域比传统结构器件的耗尽区域更宽，从而提高了击穿电压BV。
图5示出依据本发明另一实施例的N沟道沟槽MOSFET器件。如图5所示，和图1所示实施例相比，依据图5所示实施例的N沟道沟槽MOSFET器件中包括多个P型柱状结构105，其位于N-外延层101内，且所有P型柱状结构105被N-外延层101覆盖，多个P型柱状结构105沿沟槽纵向排列。多个柱状结构105和N-外延层101形成多个PN结，承受电压，从而和传统N沟道沟槽MOSFET器件相比，其提高了击穿电压BV。
以上实施例以单元N沟道沟槽MOSFET器件为例，对其结构和性能进行了描述。图6示出了在生产制造中，依据本发明实施例的具有多个重复单元的N沟道沟槽MOSFET器件，单元N沟道沟槽MOSFET器件的结构和性能对其同样适用。
上述本发明的说明书和实施方式仅仅以示例性的方式对本发明实施例的MOSFET器件及其制作方法进行了说明，并不用于限定本发明的范围。对于公开的实施例进行变化和修改都是可能的，其他可行的选择性实施例和对实施例中元件的等同变化可以被本技术领域的普通技术人员所了解。本发明所公开的实施例的其他变化和修改并不超出本发明的精神和保护范围。

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1.一种沟槽金属氧化物半导体场效应晶体管器件，包括：
第一导电类型的衬底；
第一导电类型的外延层，位于所述衬底上，且其掺杂浓度小于所述衬底的掺杂浓度；
沟槽，从所述外延层的上表面垂直向所述外延层的下表面延伸，且其未接触所述衬底的表面；
第一绝缘层，位于所述沟槽内，且覆盖所述沟槽的下部分内表面；
第二绝缘层，位于所述沟槽内，且覆盖所述沟槽的上部分内表面和所述第一绝缘层，其中，所述第二绝缘层的厚度小于所述第一绝缘层的厚度；
多晶硅区域，位于所述沟槽内，且下表面被所述第一绝缘层覆盖，其侧壁被所述第一绝缘层或第二绝缘层覆盖；
栅极，位于所述沟槽内，从所述外延层的上表面垂直向所述外延层的下表面延伸，且其侧壁和下表面被所述第二绝缘层覆盖；
至少一个第二导电类型的柱状结构，位于所述外延层内，且其侧壁和下表面被所述外延层覆盖，其中，所述至少一个第二导电类型的柱状结构沿外延层纵向排列；
第二导电类型的体区，其侧壁和所述沟槽的相邻侧壁相接触，且体区的下表面距离外延层上表面的距离小于栅极下表面距离外延层上表面的距离，其中，所述体区的掺杂浓度大于所述柱状结构的掺杂浓度；
第一导电类型的重掺杂区域，其位于所述体区内且和所述沟槽的相邻侧壁相，且其掺杂浓度大于所述外延层的掺杂浓度；和
源极，其位于所述体区内，从所述外延层的上表面垂直向所述体区延伸，且与第一导电类型的重掺杂区域相接触。
2.如权利要求1所述的超结沟槽金属氧化物半导体场效应晶体管器件，其中，所述多晶硅区域的上表面和所述沟槽的上表面重合。
3.如权利要求1所述的超结沟槽金属氧化物半导体场效应晶体管器件，其中，所述多晶硅区域位于所述栅极下方，且其上表面被所述第一绝缘层覆盖。
4.如权利要求1所述的超结沟槽金属氧化物半导体场效应晶体管器件，其中，所述多晶硅区域的上表面被所述第二绝缘层覆盖。
5.如权利要求1所述的超结沟槽金属氧化物半导体场效应晶体管器件，其中，所述多晶硅区域连接至所述源极。
6.如权利要求1所述的超结沟槽金属氧化物半导体场效应晶体管器件，其中，当所述第一导电类型为N型时，所述多晶硅区域连接至低于漏极所加电位的低电位，当所述第一导电类型为P型时，所述多晶硅区域连接至高于漏极所加电位的高电位。
7.如权利要求1所述的超结沟槽金属氧化物半导体场效应晶体管器件，其中，所述第一导电类型的区域从所述外延层的上表面延伸至所述体区内，且与所述沟槽的相邻侧壁接触。
8.如权利要求1所述的超结沟槽金属氧化物半导体场效应晶体管器件，其中，所述沟槽金属氧化物半导体场效应晶体管器件还包括第二导电类型的重掺杂区域，其位于所述体区内，且其浓度大于所述体区的浓度，且与所述源极相接触。
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