CN102569404B - 低导通电阻的横向扩散mos半导体器件 - Google Patents

低导通电阻的横向扩散mos半导体器件 Download PDF

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CN102569404B
CN102569404B CN201210014741.6A CN201210014741A CN102569404B CN 102569404 B CN102569404 B CN 102569404B CN 201210014741 A CN201210014741 A CN 201210014741A CN 102569404 B CN102569404 B CN 102569404B
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陈伟元
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Abstract

本发明公开一种低导通电阻的横向扩散MOS半导体器件，包括：位于P型的衬底层内的P型阱层和N型轻掺杂层；源极区和N型轻掺杂层之间区域的P型阱层上方设有栅氧层；源极区与N型轻掺杂层之间且位于P型阱层上部开有至少两个凹槽，此凹槽的刻蚀深度为源极区结深的1/4～1/5之间；N型轻掺杂层由第一N型轻掺杂区、第二N型轻掺杂区和P型轻掺杂区组成；所述第一N型轻掺杂区的掺杂浓度高于所述P型轻掺杂区的掺杂浓度，所述P型轻掺杂区的掺杂浓度高于所述第二N型轻掺杂区的掺杂浓度；所述第一N型轻掺杂区与第二N型轻掺杂区的掺杂浓度比例范围为：1.2∶1～1.3∶1。本发明功率MOS半导体器件减小了器件体积，同时改善了器件的响应时间和频率特性，实现了器件性能参数的长时间稳定性。

Description

低导通电阻的横向扩散MOS半导体器件
技术领域
本发明涉及一种MOS器件，具体涉及一种金属氧化物功率MOS半导体器件。
背景技术
金属氧化物功率MOS半导体器件，随着半导体行业的迅猛发展，以大功率半导体器件为代表的电力电子技术迅速发展，应用领域不断扩大，如交流电机的控制，打印机驱动电路。在现今各种功率器件中，横向扩散MOS半导体器件LDMOS具有工作电压高，工艺相对简单，因此LDMOS具有广阔的发展前景。在LDMOS器件设计中，击穿电压和导通电阻一直都是人们设计此类器件时所关注的主要目标，外延层的厚度、掺杂浓度、漂移区的长度是LDMOS最重要的参数。可以通过增加漂移区的长度以提高击穿电压，但是这会增加芯片面积和导通电阻。耐压和导通电阻对于外延层的浓度和厚度的要求是矛盾的。高的击穿电压要求厚的轻掺杂外延层和长的漂移区，而低的导通电阻则要求薄的重掺杂外延层和短的漂移区，因此必须选择最佳外延参数和漂移区长度，以便在满足一定的源漏击穿电压的前提下，得到最小的导通电阻。RESURF(降低表面电场原理)一直被广泛应用于高压器件的设计中，此原理要求漂移区电荷和衬底电荷达到电荷平衡，以做到漂移区完全耗尽时可以承受较高耐压。
随着器件小型化的发展要求，现有的LDMOS设计占有的版图面积较大，这不利于其与其它功能器件集成进一步减小体积，从而扩展应用范围，因此，如何设计一种能有效降低现有的LDMOS的所占硅片的表面积，并能进一步改善器件的性能，成为技术障碍。
发明内容
本发明提供一种低导通电阻的横向扩散MOS半导体器件，此功率MOS半导体器件减小了器件体积，同时改善了器件的响应时间和频率特性，实现了器件性能参数的长时间稳定性。
为达到上述目的，本发明采用的技术方案是：
一种低导通电阻的横向扩散MOS半导体器件，包括：位于P型的衬底层内的P型阱层和N型轻掺杂层，所述P型阱层与N型轻掺杂层在水平方向相邻从而构成一PN结，一源极区位于所述P型阱层，一漏极区位于所述衬底层内，位于所述源极区和N型轻掺杂层之间区域的P型阱层上方设有栅氧层，此栅氧层上方设有一栅极区；所述源极区与N型轻掺杂层之间且位于P型阱层上部开有至少两个凹槽，此凹槽的刻蚀深度为源极区结深的1/4～1/5之间；
所述N型轻掺杂层由第一N型轻掺杂区、第二N型轻掺杂区和P型轻掺杂区组成；所述第一N型轻掺杂区的掺杂浓度高于所述P型轻掺杂区的掺杂浓度，所述P型轻掺杂区的掺杂浓度高于所述第二N型轻掺杂区的掺杂浓度；
所述第一N型轻掺杂区与第二N型轻掺杂区的掺杂浓度比例范围为：1.2∶1～1.3∶1；
所述第一N型轻掺杂区位于所述第二N型轻掺杂区上方；所述P型轻掺杂区在水平方向上位于所述第一N型轻掺杂区的中央区域且此P型轻掺杂区在垂直方向上位于所述第一N型轻掺杂区中央区域的中下部并与所述第二N型轻掺杂区表面接触。
作为优选，所述凹槽的侧墙区和顶墙区的掺杂浓度相等，且为凹槽的底部区杂浓度的86～94％之间。
作为优选，所述第一N型轻掺杂区与P型轻掺杂区的掺杂浓度比例为：1.08∶1。
作为优选，所述P型阱层和N型轻掺杂层的结深比例为2∶1。
作为优选，所述漏极区位于所述N型轻掺杂层内。
作为优选，所述N型轻掺杂层位于所述漏极区与所述P型阱层之间。
由于上述技术方案运用，本发明与现有技术相比具有下列优点和效果：
1、本发明开有至少两个凹槽，增加了沟道密度加倍，提高了栅宽，提高了轻掺杂层掺杂浓度的设计空间，利于器件整体性能的优化及体积减小，从而降低产业成本。
2、本发明凹槽的侧墙区和顶墙区的掺杂浓度相等，可有效避免侧墙区、顶墙区掺杂离子的扩散，实现了器件性能长时间的参数稳定性；其次，侧墙区和顶墙区的掺杂浓小于凹槽的底部区的掺杂浓度，克服了栅宽的影响，保证了器件的开启时间小，减小了高频时导通电阻和开关损耗。
3、本发明P型轻掺杂区在垂直方向上位于所述第一N型轻掺杂区中央区域的中下部并与所述第二N型轻掺杂区接触，经过仿真测试降低了栅漏电容Cgd，截止频率提高了8％左右，形成两条电流支路，进一步降低了比导通电阻。
4、本发明所述第一N型轻掺杂区、P型轻掺杂区和第二N型轻掺杂区的掺杂浓度依次降低，且P型阱层和N型轻掺杂层的结深比例为2∶1，有利于衬底层的垂直方向耗尽区与水平方向耗尽区相互耦合，从而可以抵消沟道区得凹槽设计而带来的本征电容的增加，从而有利于器件的击穿电压和比导通电阻的参数设计。
5、本发明所述P型轻掺杂区两侧的第一N型轻掺杂区和第二N型轻掺杂区各自的掺杂浓度不同，且第一N型轻掺杂区和第二N型轻掺杂区之间的交界面位于P型轻掺杂区下方；有利于在P型轻掺杂区两侧形成垂直方向的耗尽层，可进一步提高器件的耐高压性能。
6、本发明保持高击穿电压的同时，进一步提高N型轻掺杂层的浓度从而降低了器件的整体比导通电阻和器件的开关损耗，且P型轻掺杂区对其N型轻掺杂层内调制的电场更趋于平坦化，有效降低了P型阱层与N型轻掺杂层之间的电场强度。
附图说明
附图1为本发明金属氧化物功率MOS半导体器件结构示意图；
附图2为附图1中A处局部放大图。
以上附图中：1、衬底层；2、P型阱层；3、N型轻掺杂层；4、源极区；5、漏极区；6、P型轻掺杂区；7、栅氧层；8、栅极区；9、第一N型轻掺杂区；10、第二N型轻掺杂区；11、凹槽；12、侧墙区；13、顶墙区；14、底部区。
具体实施方式
下面结合附图及实施例对本发明作进一步描述：
实施例：一种低导通电阻的横向扩散MOS半导体器件，包括：位于P型的衬底层1内的P型阱层2和N型轻掺杂层3，所述P型阱层2与N型轻掺杂层3在水平方向相邻从而构成一PN结，一源极区4位于所述P型阱层2，一漏极区5位于所述衬底层1内，位于所述源极区4和N型轻掺杂层3之间区域的P型阱层2上方设有栅氧层7，此栅氧层7上方设有一栅极区8；所述源极区4与N型轻掺杂层3之间且位于P型阱层2上部开有至少两个凹槽11，此凹槽11的刻蚀深度为源极区4结深的1/4～1/5之间；凹槽11的侧墙区12和顶墙区13的掺杂浓度相等，且为凹槽11的底部区14杂浓度的86～94％之间；
所述N型轻掺杂层3由第一N型轻掺杂区9、第二N型轻掺杂区10和P型轻掺杂区6组成；所述第一N型轻掺杂区9的掺杂浓度高于所述P型轻掺杂区6的掺杂浓度，所述P型轻掺杂区6的掺杂浓度高于所述第二N型轻掺杂区10的掺杂浓度；
所述第一N型轻掺杂区9与第二N型轻掺杂区10的掺杂浓度比例范围为：1.2∶1～1.3∶1；
所述第一N型轻掺杂区9位于所述第二N型轻掺杂区10上方；所述P型轻掺杂区6在水平方向上位于所述第一N型轻掺杂区9的中央区域且此P型轻掺杂区6在垂直方向上位于所述第一N型轻掺杂区9中央区域的中下部并与所述第二N型轻掺杂区10表面接触。
上述第一N型轻掺杂区9与P型轻掺杂区6的掺杂浓度比例为：1.08∶1。
上述P型阱层2和N型轻掺杂层3的结深比例为2∶1。
上述漏极区5位于所述N型轻掺杂层3内。
上述N型轻掺杂层3位于所述漏极区5与所述P型阱层2之间。
采用上述低导通电阻的横向扩散MOS半导体器件时，开有至少两个凹槽，增加了沟道密度加倍，提高了栅宽，提高了轻掺杂层掺杂浓度的设计空间，利于器件整体性能的优化及体积减小，从而降低产业成本；其次，本发明凹槽的侧墙区和顶墙区的掺杂浓度相等，可有效避免侧墙区、顶墙区掺杂离子的扩散，实现了器件性能长时间的参数稳定性；其次，侧墙区和顶墙区的掺杂浓度小于凹槽的底部区的掺杂浓度，克服了栅宽的影响，保证了器件的开启时间小，减小了高频时导通电阻和开关损耗；再次，本发明P型轻掺杂区在垂直方向上位于所述第一N型轻掺杂区中央区域的中下部并与所述第二N型轻掺杂区接触，经过仿真测试降低了栅漏电容Cgd，截止频率提高了8％左右，形成两条电流支路，进一步降低了比导通电阻；再次，本发明所述第一N型轻掺杂区、P型轻掺杂区和第二N型轻掺杂区的掺杂浓度依次降低，且P型阱层和N型轻掺杂层的结深比例为2∶1，有利于衬底层的垂直方向耗尽区与水平方向耗尽区相互耦合，从而可以抵消沟道区凹槽设计而带来的本征电容的增加，从而有利于器件的击穿电压和比导通电阻的参数设计。
上述实施例只为说明本发明的技术构思及特点，其目的在于让熟悉此项技术的人士能够了解本发明的内容并据以实施，并不能以此限制本发明的保护范围。凡根据本发明精神实质所作的等效变化或修饰，都应涵盖在本发明的保护范围之内。

Claims (4)

1.一种低导通电阻的横向扩散MOS半导体器件，包括：位于P型的衬底层(1)内的P型阱层(2)和N型轻掺杂层(3)，所述P型阱层(2)与N型轻掺杂层(3)在水平方向相邻从而构成一PN结，一源极区(4)位于所述P型阱层(2)，一漏极区(5)位于所述衬底层(1)内，位于所述源极区(4)和N型轻掺杂层(3)之间区域的P型阱层(2)上方设有栅氧层(7)，此栅氧层(7)上方设有一栅极区(8)；其特征在于：所述源极区(4)与N型轻掺杂层(3)之间且位于P型阱层(2)上部开有至少两个凹槽(11)，此凹槽(11)的刻蚀深度为源极区(4)结深的1/4～1/5之间；
所述N型轻掺杂层(3)由第一N型轻掺杂区(9)、第二N型轻掺杂区(10)和P型轻掺杂区(6)组成；所述第一N型轻掺杂区(9)的掺杂浓度高于所述P型轻掺杂区(6)的掺杂浓度，所述P型轻掺杂区(6)的掺杂浓度高于所述第二N型轻掺杂区(10)的掺杂浓度；
所述第一N型轻掺杂区(9)与第二N型轻掺杂区(10)的掺杂浓度比例范围为：1.2∶1～1.3∶1；
所述第一N型轻掺杂区(9)位于所述第二N型轻掺杂区(10)上方；所述P型轻掺杂区(6)在水平方向上位于所述第一N型轻掺杂区(9)的中央区域且此P型轻掺杂区(6)在垂直方向上位于所述第一N型轻掺杂区(9)中央区域的中下部并与所述第二N型轻掺杂区(10)表面接触；
所述凹槽(11)的侧墙区(12)和顶墙区(13)的掺杂浓度相等，且为凹槽(11)的底部区(14)掺杂浓度的86～94％之间；
所述第一N型轻掺杂区(9)与P型轻掺杂区(6)的掺杂浓度比例为：1.08∶1。
2.根据权利要求1所述的MOS半导体器件，其特征在于：所述P型阱层(2)和N型轻掺杂层(3)的结深比例为2∶1。
3.根据权利要求1或2所述的MOS半导体器件，其特征在于：所述漏极区(5)位于所述N型轻掺杂层(3)内。
4.根据权利要求1或2所述的MOS半导体器件，其特征在于：所述N型轻掺杂层(3)位于所述漏极区(5)与所述P型阱层(2)之间。
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