CN202695453U - 一种横向晶体管 - Google Patents

一种横向晶体管 Download PDF

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CN202695453U
CN202695453U CN201220245289XU CN201220245289U CN202695453U CN 202695453 U CN202695453 U CN 202695453U CN 201220245289X U CN201220245289X U CN 201220245289XU CN 201220245289 U CN201220245289 U CN 201220245289U CN 202695453 U CN202695453 U CN 202695453U
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transistor
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field plate
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唐纳德·迪斯尼
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Chengdu Monolithic Power Systems Co Ltd
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Abstract

公开了一种横向晶体管。该横向晶体管包括形成在栅区氧化物上的栅区和形成在厚栅区氧化物上的场板，所述场板电连接至源区，当横向晶体管处于关断状态时，该场板用于电容性耗尽漂移区。本实用新型可实现电容性耗尽和保护作用，同时不会增加栅漏之间的电容。

Description

一种横向晶体管
技术领域
本实用新型涉及分立半导体器件，更具体地说，本实用新型涉及但不仅限于金属氧化物半导体（Metal-Oxide Semiconductor, MOS）晶体管。
背景技术
横向晶体管，比如横向双扩散金属氧化物半导体（Double Diffused Metal-Oxide Semiconductor, DMOS）晶体管被广泛应用于各种电子场合，例如作为电压调节器的开关元件。横向DMOS晶体管包含位于栅区电介质层上的栅区，栅区电介质层具有薄、厚两个部分，在沟道区和部分漂移区上面具有一个较薄的部分，在漂移区的另一部分上具有较厚的部分。较薄的部分简单称作为“栅区氧化物”，而较厚的部分称作为“厚栅区氧化层”。一个延伸的栅区形成于整个栅区电介质的表面，包含至少部分厚栅区氧化物。厚栅区氧化物可减少栅区电场，有利于增加晶体管的击穿电压。但是，这个结构同样增加了漏栅区之间的电容，影响了晶体管的开关速度。
实用新型内容
根据现有技术中存在的一些问题，本实用新型提供了一种横向晶体管。
在本实用新型的第一方面，提供了一种横向晶体管，包括：外延层，形成于衬底上；源区和漏区；栅区氧化物和厚栅区氧化物，形成于源区和漏区之间的外延层上，其特征在于，所述厚栅区氧化物厚于所述栅区氧化物；栅区，形成于所述栅区氧化物上；场板，形成于所述厚栅区氧化物而非所述栅区氧化物上；层间电介质，具有第一通孔至所述源区，第二通孔至所述场板；以及源电极，通过穿过所述层间电介质的所述第一和第二通孔电连接至所述源区和所述场板。
本实用新型所述的晶体管，进一步包括：体区，环绕所述源区并位于所述栅区下；漂移区，环绕所述漏区并位于所述场板和部分所述栅区下。
本实用新型所述的晶体管，其特征在于，所述体区被所述漂移区环绕。
本实用新型所述的晶体管，其特征在于，侧墙隔板将所述漏区和所述场板横向隔开。
本实用新型所述的晶体管，其特征在于，所述衬底和所述体区掺杂P型掺杂物，所述源区、所述漂移区以及所述漏区掺杂N型掺杂物。
本实用新型所述的晶体管，其特征在于，所述晶体管包括横向双扩散金属氧化物半导体晶体管。
本实用新型所述的晶体管，其特征在于，所述栅区和所述场板被一个长度小于0.25um的沟隙隔开，所述沟隙被填充电介质材料。
本实用新型所述的晶体管，进一步包括：第一侧墙隔板和第二侧墙隔板，分别形成在所述栅区的两边侧墙上；以及第三侧墙隔板和第四侧墙隔板，分别形成在所述场板的两边侧墙上。
本实用新型所述的晶体管，其特征在于，所述栅区形成在所述栅区氧化物和部分所述厚栅区氧化物上。
在本实用新型的第二方面，还提供了一种横向晶体管，包括：P型半导体层；栅区，形成在栅区氧化物上；场板，形成在厚栅区氧化物而非栅区氧化物上，其特征在于所述厚栅区氧化物厚于所述栅区氧化物，所述场板和所述栅区被沟隙隔开；以及形成在P型体区里的N+源区和形成在漂移区里的N+漏区。
本实用新型所述的晶体管，进一步包括源电极，通过层间电介质上的通孔电连接所述N+源区和所述场板。
本实用新型所述的晶体管，其特征在于，所述场板和所述N+源区通过形成在所述N+源区上的硅化层电连接。
本实用新型所述的晶体管，其特征在于，所述N+源区和所述场板电连接。 
附图说明
附图作为说明书的一部分，对本实用新型实施例进行说明，并与实施例一起对本实用新型的原理进行解释。为了更好地理解本实用新型，将根据以下附图对本实用新型进行详细描述。
图1所示为根据本实用新型一实施例的横向晶体管截面图。
图2所示为图1中晶体管的栅区和场板放大示意图，并示出了各部分具体的尺寸。
图3所示为根据本实用新型另一实施例的横向晶体管示意图。
图4所示为根据本实用新型又一实施例的横向晶体管示意图。
在不同的附图中，相同的参数符号代表相同的器件，同时应了解，这些附图并不是完全按比例绘制的。
具体实施方式
为了更好的理解本实用新型，本实用新型在以下的内容中公开了大量的细节，比如具体实施例的结构，本领域的普通技术人员应理解，缺少部分细节，本实用新型仍可实施。在其他实施例中，为了避免模糊本实用新型的主旨，一些公知的细节未加描述，因此，本实用新型意在涵盖由权利要求书所界定的本实用新型精神和范围内所定义的各种可选方案、修改方案和等同方案。
图1所示为根据本实用新型一实施例的横向DMOS晶体管100的截面图。在图1所示实施例中，晶体管100包括形成在P型衬底101上的P-（即轻掺杂的P型掺杂物）外延层102。衬底101可包括硅片。外延层102的厚度约为3-6um，而衬底101的厚度约为200-600um。在本实用新型所示实施例中，图1以及其他附图并非是按比例刻度精确绘制，只做示意。同样地，外延层102和衬底101还可采用N型掺杂物，以适当地改变晶体管100的其他特性。
在图1所示实施例中，外延层102中将形成P型体区104和N型漂移区103。体区104和漂移区103被部分P型外延层102隔开，如图中所示。在其他实施例中，P型体区104和N型漂移区103可相互接触，甚至重叠在一起。在图1所示实施例中，不论是体区104还是漂移区103都不会延伸至衬底101，在其他实施例中，体区104和漂移区103均可垂直延伸至衬底101或与衬底101重叠。
外延层102中还将形成P+（即重掺杂的P型掺杂物）接触区117，N+（即重掺杂的N型掺杂物）源区106、轻掺杂的 N-源区166以及N+漏区107。接触区117增强了至体区104的电连接。在图1所示实施例中，源区106形成在体区104中，漏区107形成在漂移区103中。
在图1所示实施例中，晶体管100包括栅区电介质层，其特征在于栅区电介质层包括较薄的部分113和较厚的部分114。栅区电介质层可包括生长或淀积的二氧化硅。较薄的部分被简单称作“栅区氧化物113”，较厚部分被称作“厚栅区氧化物114”。栅区氧化物113形成在体区104和体区104与漂移区103之间的部分外延层102上，也就是导通状态（即晶体管100开关导通）下形成沟道的区域。另有一小部分栅区氧化物113还将延伸至漂移区103的上面，使得沟道和漂移区更好地电连接。厚栅区氧化物114形成在至少部分漂移区103上。
栅区108包括多晶硅，形成在栅区氧化物113上，在其他实施例中，还可延伸至厚栅区氧化物114上。场板109包括和栅区108一样的材料，形成在厚栅区氧化物114上，用于在关断状态（即晶体管100开关关断）时电容性耗尽漂移区103。在一些实施例中，栅区108和场板109上将各自形成硅化物层112和121。场板109和源区106通过源电极115电连接，源电极115可包括金属层。源电极115通过硅化层121与场板109连接，通过硅化层122与源区106连接。漏电极116可包括与源电极115相同的材料，通过硅化层123与漏区107电连接。
场板109不能与漏区107或栅区108电连接。场板109，漏区107以及栅区108被部分层间电介质（Interlevel Dielectric, ILD）105相互电气隔开。场板109，厚栅区氧化物114以及漂移区103形成金属氧化物半导体（Metal-Oxide Semiconductor, MOS）电容用于电容性耗尽来自漂移区103的电荷，当晶体管100处于关断状态时，场板109电容性耗尽来自漂移区109的自由载流子。这样有两点益处，第一，相比于没有电容性耗尽时，在不降低降低晶体管100的击穿电压的情况下，漂移区103可包括更多N型电荷；第二，通过与源区连接的场板109电容性耗尽漂移区103可以降低栅区108和漂移区103之间的电场（即场板109可保护栅区108免处于高电场中），因此可提高晶体管100的击穿电压。
传统的横向DMOS晶体管也具有相同的电容性耗尽以及通过在厚栅区氧化物上横向延伸栅区来避免高电场的作用，实质上是形成一个与栅区相连的场板。但是，这个与栅区相连的场板极大的增加了横向DMOS晶体管栅漏区之间的电容。本实用新型所示实施例可以实现电容性耗尽和保护作用，同时不会增加栅漏之间的电容。
栅电极（未示出）沿着垂直图1的方向电连接至栅区108。侧墙隔板110和111使得注入步骤中的自对准更容易。例如，轻掺杂的源区166可自对准至栅区108，同时源区106可自对准侧墙隔板110，漏区107可自对准侧墙隔板111。在其他实施例中，为了形成更长的漂移区，可通过光刻步骤使漏区107与侧墙隔板111横向隔开。
在图1所示实施例中，栅区108形成在栅区氧化物113和部分厚栅区氧化物114上。在一个特例中，当晶体管100的击穿电压为25V时，栅区在栅区氧化物113上的长度约为0.3um（参见图2中的LG），在厚栅区氧化物114上延伸的长度约为0.1um（参见图2中的LO）。沟隙161将栅区108和场板109在物理上以及电气上隔开。更好地是，由于沟隙161足够窄，当晶体管100关断时，在厚栅区氧化物114上的场板109与栅区108靠的很近，因此可减小栅区108边缘的电场，进而提高击穿电压。但是在栅区108和场板109之间存在的最大电势差下，为防止沟隙中部分层间电介质105大量退化，沟隙161又应足够宽。例如，在晶体管100击穿电压为25的实施例中，沟隙161约为0.1-0.2um。沟隙161可用电介质填充为侧墙隔板（即图2中所示隔板201、202）。
为了便于制作，可在同一个淀积步骤同时形成场板109和栅区108，再通过刻蚀将其分开。在这个实施例中，沟隙161的长度由工艺性能来决定（即局限于光刻和刻蚀的工艺）。
当晶体管100处于导通状态时，其工作原理与传统的LDMOS相同。更具体地说，通过在栅区108施加一个高于其阈值电压的正向电压，晶体管100导通，并在源区106和漂移区103之间形成一个反型层或沟道。电子流从源区106经沟道和漂移区103到达漏区107。由于沟隙161足够窄，栅区108和场板109的电场分布和连续栅区（即没有沟隙161）的电场分布相同。
当晶体管100处于关断状态时，栅区108上的电压减小，因此不能产生供电子流流动的沟道。源区、栅区和场板的电势完全相同，漏区施加一个相对于源区、栅区和场板电压为正的电压。P-外延层102和N-漂移区103之间的PN结反向偏压。场板109和厚栅区氧化物114的电容性行为进一步耗尽漂移区103，使得漂移区103的掺杂更高有利于减小晶体管的导通电阻。
图2所示为根据本实用新型一实施例的晶体管100中栅区108和场板109的放大示意图，并示出了各部分具体的尺寸。如图2所示，LG代表栅区位于栅区氧化物113的长度（如0.3um），LO代表栅区延伸至厚栅区氧化物114的长度（如0.1um），LGAP代表沟隙161的长度（如小于0.25um，或0.1-0.2um），LFP代表场板109的长度（0.3-0.6um）。这里公开的示例性的和其他具体的尺寸均是基于击穿电压为25的横向DMOS晶体管做出的。在图2中，还示出了侧墙隔板201和202，为了避免模糊图1，在图1中并未示出201和202。
如图2所示，在形成侧墙隔板110和111时，还将在沟隙161内形成侧墙隔板201和202。也就是说，栅区108的一边侧墙上具有侧墙隔板110，另一边侧墙上具有侧墙隔板201；场板109的一边侧墙上具有侧墙隔板111，另一边侧墙上具有侧墙隔板202。如果沟隙161很窄，沟隙161将可能被侧墙隔板的电介质材料完全填充。
根据前面所提及的，本技术领域一般技术人员应理解，在不减损本实用新型优势的情况下，可对晶体管100进行适当地修改。作为一个示例，图3所示为根据本实用新型一实施例的横向DMOS晶体管示意图300。晶体管300是晶体管100的一个特例，在这个实施例中，漏区107，P型体区104以及由其限定的其他特征均形成在N型阱130中，使N型阱130作为漂移区。图3中其他部分的说明参见先前图1、图2所述。
图4所示为根据本实用新型另一实施例的横向晶体管示意图。在图4所示示例中，横向晶体管为横向DMOS晶体管400。晶体管400是晶体管100的一个特例，其特征在于，场板109不再电连接至源电极401，而是电连接至独立的场板电极402。这样在晶体管关断状态下场板109接地，可通过其他电路或节点，而不是源区106来耗尽N-漂移区103。比如，场板109可电连接至外部或集成电路（未示出），这样可利用来自厚栅区氧化物114的有效电容。
虽然上面详细的描述了本实用新型具体的实施例，并指明了最优方案，但是不论先前描述的多详细，本实用新型仍有许多其他实施方式。在实际执行时可能有些变化，但仍然包含在本实用新型主旨范围内，因此，本实用新型旨在包括所有落入本实用新型和所述权利要求范围及主旨内的替代例、改进例和变化例等。

Claims (13)

1.一种横向晶体管，包括：
外延层，形成于衬底上；
源区和漏区；
栅区氧化物和厚栅区氧化物，形成于源区和漏区之间的外延层上，其特征在于，所述厚栅区氧化物厚于所述栅区氧化物；
栅区，形成于所述栅区氧化物上；
场板，形成于所述厚栅区氧化物而非所述栅区氧化物上；
层间电介质，具有第一通孔至所述源区，第二通孔至所述场板；以及
源电极，通过穿过所述层间电介质的所述第一和第二通孔电连接至所述源区和所述场板。
2.如权利要求1所述晶体管，进一步包括：
体区，环绕所述源区并位于所述栅区下；漂移区，环绕所述漏区并位于所述场板和部分所述栅区下。
3.如权利要求2所述晶体管，其特征在于，所述体区被所述漂移区环绕。
4.如权利要求2所述晶体管，其特征在于，侧墙隔板将所述漏区和所述场板横向隔开。
5.如权利要求1所述晶体管，其特征在于，所述衬底和所述体区掺杂P型掺杂物，所述源区、所述漂移区以及所述漏区掺杂N型掺杂物。
6.如权利要求1所述晶体管，其特征在于，所述晶体管包括横向双扩散金属氧化物半导体晶体管。
7.如权利要求6所述晶体管，其特征在于，所述栅区和所述场板被一个长度小于0.25um的沟隙隔开，所述沟隙被填充电介质材料。
8.如权利要求1所述晶体管，进一步包括：
第一侧墙隔板和第二侧墙隔板，分别形成在所述栅区的两边侧墙上；以及
第三侧墙隔板和第四侧墙隔板，分别形成在所述场板的两边侧墙上。
9.如权利要求1所述晶体管，其特征在于，所述栅区形成在所述栅区氧化物和部分所述厚栅区氧化物上。
10.一种横向晶体管，包括：
P型半导体层；
栅区，形成在栅区氧化物上；
场板，形成在厚栅区氧化物而非栅区氧化物上，其特征在于所述厚栅区氧化物厚于所述栅区氧化物，所述场板和所述栅区被沟隙隔开；以及
形成在P型体区里的N+源区和形成在漂移区里的N+漏区。
11.如权利要求10所述晶体管，进一步包括源电极，通过层间电介质上的通孔电连接所述N+源区和所述场板。
12.如权利要求10所述晶体管，其特征在于，所述场板和所述N+源区通过形成在所述N+源区上的硅化层电连接。
13.如权利要求10所述晶体管，其特征在于，所述N+源区和所述场板电连接。
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