TWI469347B - 帶有溝槽-氧化物-奈米管超級接面之元件結構及製備方法 - Google Patents

帶有溝槽-氧化物-奈米管超級接面之元件結構及製備方法 Download PDF

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TWI469347B
TWI469347B TW100106597A TW100106597A TWI469347B TW I469347 B TWI469347 B TW I469347B TW 100106597 A TW100106597 A TW 100106597A TW 100106597 A TW100106597 A TW 100106597A TW I469347 B TWI469347 B TW I469347B
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Taiwan
Prior art keywords
trench
epitaxial layer
dielectric
layer
region
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TW100106597A
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English (en)
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TW201131774A (en
Inventor
Hamza Yilmaz
Madhur Bobde
Yeeheng Lee
Lingpeng Guan
Xiaobin Wang
John Chen
Anup Bhalla
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Alpha & Omega Semiconductor
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Priority claimed from US12/661,004 external-priority patent/US8390058B2/en
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Publication of TW201131774A publication Critical patent/TW201131774A/zh
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Publication of TWI469347B publication Critical patent/TWI469347B/zh

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Description

帶有溝槽-氧化物-奈米管超級接面之元件結構及製備方法
本發明主要關於一種半導體功率元件，更確切地說，本發明關於帶有溝槽側壁之溝槽奈米管之結構和製備方法，其中用摻雜的外延層覆蓋溝槽側壁，然後用絕緣材料填充溝槽側壁，以便用簡化的製備技術靈活地製備可測量的電荷平衡的半導體功率元件，同時獲得高擊穿電壓以及很低的電阻。
儘管關於帶有垂直超級接面結構的半導體元件，為了改善其電學特性，已有許多專利資訊以及公開的技術檔案，但是在超級接面半導體元件的設計和製備的相關領域，仍然存在許多技術難題與製備侷限。更確切地說，最常見的超級接面元件包含金屬氧化物半導體場效電晶體(MOSFET)和絕緣閘雙極電晶體，關於這些元件，已有許多已公開的專利資訊，包含美國專利5,438,215、5,216,275、4,754,310、6,828,631。藤平(Fujihira)在《半導體超級接面元件理論》(日本應用物理快報，36卷，1997年10月，6254-6262頁)一書中，提出了垂直超級接面元件的結構。更確切地說，藤平發表的論文中的第2圖表示了一種垂直溝槽 MOSFET超級接面元件，在此引用為第1圖(1A)。藤平還在美國專利6,097,063中提出了一種具有漂流區的垂直半導體元件，當元件處於閉合模式時，漂流區中有漂流電流流過，當元件處於斷開模式時，漂流區中的漂流電流耗盡。所形成的漂流區結構是具有多個第一導電類型的分立的漂流區，以及多個第二導電類型的分隔區，其中每一分隔區都位於分別相鄰的漂流區中，並聯形成P-N接面。美國專利6,608,350提出了一種垂直超級接面元件，帶有介質材料層填充在溝槽中，美國專利5,981,996如第2圖(1B)所示，提出了一種垂直溝槽MISFET元件。
然而，在這些專利技術和公開內容中所述的超級接面元件的結構和工作性能中，仍然存在諸多技術侷限，從而限制了這些元件在實際應用中的有效性。傳統超級接面元件的難題與侷限包含深溝槽的填充、形成在溝槽中的奈米管的尺寸限制、保持終止區附近的臺面區域處電荷平衡、超級接面元件的非箝位元感應開關(UIS)能力不足、超級接面功率元件的振盪問題、由於外延生長速度緩慢造成超級接面元件的高製造成本、超級接面結構中的N和P雜質在高溫下相互擴散、在同一晶片上難以整合不同的元件、以及高壓應用時的終止區域很大等相關技術問題。
因此，在功率半導體元件的設計和製備領域中，有必要提出形成功率元件的新穎的元件結構和製備方法，從而解決上述困難與侷限。
因此，本發明的一個方面是提出一種新型的、改良的元件結構和製備方法，藉由在溝槽側壁和底部，生長一薄的N-型摻雜外延層 (例如砷外延層)，沒有完全填充或部分填充溝槽，然後在第一外延層上方生長第二外延層，並用非摻雜的介質材料填充剩餘的構成縫隙，從而解決用外延層填充深溝槽時，傳統的製備方法中經常遇到的問題。第二外延層可以充分填充其餘溝槽縫隙的底部，從而可以在縫隙中更加方便地沉積介質材料。
本發明的另一方面在於，提出了一種帶有超級接面結構的新型的、改良的元件結構和製備方法，利用電荷平衡原理，藉由奈米管結構，降低Rds，並且元件間距很小，以獲得6微米間距的600V MOSFET，其導通電阻率小於9毫歐/cm2。這就解決了用於高壓元件時對於高Rds的限制。
本發明的另一方面在於，提出了一種帶有超級接面結構的新型的、改良的元件結構和製備方法，該結構利用較大的間距以及狹窄的N-外延層，並利用在每個主動元件叉指末端具有較大半徑的單一元件，在主動區域臺面結構的末端保持電荷平衡。
本發明的另一方面在於，提出了一種帶有超級接面結構的新型的、改良的元件結構和製備方法，在一個帶有摻雜濃度分級的外延層中製備超級接面結構，例如在一個N+基體上用三個步驟形成P外延層，迫使擊穿發生在漂流區較低的部分中，從而改善超級接面MOSEFT元件的UIS性能。
本發明的另一方面在於，提出了一種帶有超級接面結構的新型的、改良的元件結構和製備方法，厚介質區位於閘電極以下，以降低閘-汲電容Crss，從而解決超級接面功率元件的振盪問題。
本發明的另一方面在於，提出了一種帶有超級接面結構的新型的 、改良的元件結構和製備方法，藉由生長一個薄的單一層N-外延層(0.1-1.0微米的厚度範圍)，部分填充溝槽，並用電介質/氧化物填充剩餘的深溝槽，從而解決由於深溝槽中外延生長緩慢，而造成的超級接面元件的高製造成本問題。此外，輕摻雜的N-型外延層可以在N-外延層之後生長，在用電介質/氧化物填充剩餘的深溝槽之前，充分填充溝槽，這有利於更加方便地用氧化物填充溝槽。
本發明的另一方面在於，提出了一種帶有超級接面結構的新型的、改良的元件結構和製備方法，在較寬的P-型區域附近形成一個非常薄的N-型奈米管層，並與較寬的P-型區域電荷平衡；作為示例，N-型奈米管層比較寬的P-型區域寬三倍，導致硼的摻雜濃度比N-型奈米管區域中的N-型摻雜濃度低三倍。因此，只能允許受限的硼擴散進入N-型奈米管區，從而補償多餘的砷電荷。N-型奈米管區域的重N-型摻雜(例如砷或銻)，不會過分移動，從而不會大量擴散到P-型區。這就解決了在高溫下，N-和P-雜質相互擴散所帶來的問題。
本發明的另一方面在於，提出了一種帶有超級接面結構的新型的、改良的元件結構和製備方法，增大第一元件分界線處的溝槽區域寬度，例如對於一個MOSFET元件以及一個第二元件(例如肖特基二極體)，是用介質材料充分填充大溝槽區域--與主動元件不同，主動元件是用矽充分填充，再用氧化矽(氧化物或SiO2)填充剩餘部分。因此，不同的元件可以更加方便地整合在同一個矽晶片上。
本發明的另一方面在於，提出了一種帶有超級接面結構的新型的 、改良的元件結構和製備方法，將一個肖特基二極體與一個受控的注入P-N二極體整合在一起，從而降低了二極體的恢復電荷，減少高壓元件的汲電流。
本發明的另一方面在於，提出了一種帶有超級接面結構的新型的、改良的元件結構和製備方法，將一個高壓(HV)肖特基二極體與一個受控的注入P-N二極體整合在同一個矽晶片上，作為一個絕緣閘雙極電晶體(IGBT)，其中IGBT的背面帶有發射極(對於N-通道元件而言為P-型)植入。從而解決了IGBT結構缺少嵌入式二極體的難題。
本發明的另一方面在於，提出了一種新型的、改良的終止結構，製備寬介質溝槽的方法是首先藉由形成一個SiO2網路，然後蝕刻掉SiO2網路內的矽臺面結構，並用自旋式玻璃、HDP或聚醯亞胺，填充剛蝕刻掉的區域，在金屬化之前還是之後進行，取決於所選的介質材料的類型。由於製備所受的限制，用傳統的蝕刻和填充方法很難製備又寬又深的介質溝槽，但是本發明的兩步方法可以利用標準的製備技術，形成一個高品質的又寬又深的介質填充溝槽。對於一個600V元件的每一側面而言，利用終止區的這種寬氧化物溝槽，一個普通的6-10密耳寬的HV終止區，可以減至2密耳。對於低電流產品，這種HV終止區增大了晶片尺寸，對大晶片增大15%左右(在一個TO-220填充的能力中)，對較小的晶片增大50%左右(對於HV終止，為53×53密耳^2晶片，8密耳/側)。因此，由於減小了適合高壓應用元件的終止區，從而解決了高壓MOSFET功率元件，需要大終止區的難題。
閱讀以下詳細說明並參照圖式之後，本發明的這些和其他的特點 和優勢，對於本領域的技術人員而言，無疑將顯而易見。
100、100-1、102、100-2、100-3‧‧‧MOSFET元件
101、101'‧‧‧IGBT元件
105‧‧‧N+基體
105-1‧‧‧P-基體層
105-1'、150-1"‧‧‧P-型層
108‧‧‧N-通道截止層
108'‧‧‧N-型層
108"‧‧‧N-型半導體基體
110'‧‧‧P-臺面結構
110‧‧‧外延層
110-1、110-2、110-3‧‧‧P-摻雜層
115‧‧‧溝槽側壁奈米管外延層
115-3‧‧‧N+外延層
115'‧‧‧溝槽側壁奈米管外延層
116、116-2、116-3、216‧‧‧P-外延層
116-1‧‧‧N--外延層
117、217‧‧‧N-型植入區
120、121、120-2、120-3‧‧‧氧化填充物
120'‧‧‧氧化溝槽
122‧‧‧不連續區
125‧‧‧閘極氧化層
130‧‧‧溝槽閘極
130'‧‧‧多晶矽塊
135‧‧‧本體區
135'、175‧‧‧P-區
135"、165‧‧‧N-區
140、240‧‧‧P+本體接觸區
140'、176‧‧‧P+區
140"‧‧‧N+區
145、245‧‧‧N+源極區
150‧‧‧阻擋金屬層
150-1、150-2、150-3、150-4、150-5、150-n‧‧‧金屬層
155‧‧‧源極電極
160‧‧‧閘極電極
161‧‧‧P-N接面二極體
162‧‧‧肖特基二極體
162'‧‧‧肖特基元件
163‧‧‧可調電阻器R1
170‧‧‧肖特基接觸金屬
189‧‧‧終止溝槽
190‧‧‧介質層
195‧‧‧鋸齒街區
195'‧‧‧鈍化層
198'‧‧‧主動單元
199'‧‧‧終止區
205‧‧‧N+半導體基體
215‧‧‧N-奈米管層
210‧‧‧P-型外延層
200‧‧‧超級結奈米管MOSFET
205-D‧‧‧汲極金屬
210-1、210-2、210-3‧‧‧外延層
211‧‧‧氧化層
212‧‧‧氮化矽(Si3N4)層
213‧‧‧溝槽
213a‧‧‧終止溝槽
213b‧‧‧主動溝槽
218‧‧‧溝槽閘極掩膜
220‧‧‧氧化層
222‧‧‧蝕刻溝槽
223‧‧‧氧化立柱
224‧‧‧半導體臺面結構
225‧‧‧閘極氧化層
230‧‧‧閘極多晶矽層
235‧‧‧本體區
249‧‧‧終止硬掩膜
250‧‧‧鈍化層
260-S‧‧‧源極金屬
289‧‧‧終止氧化溝槽
290‧‧‧介質材料
A-A'、B-B'‧‧‧線
第1圖表示現有一種垂直超級接面功率元件之傳統結構之剖面透視圖。
第2圖表示現有一種垂直超級接面功率元件之傳統結構之剖面圖。
第3圖表示本發明所述之帶有溝槽奈米管超級接面結構之MOSFET元件之剖面圖。
第4圖至第6圖表示本發明所述之帶有交替溝槽奈米管超級接面結構之MOSFET元件之剖面圖。
第7圖表示本發明所述之帶有溝槽奈米管超級接面結構之N-通道絕緣閘雙極電晶體(IGBT)元件之剖面圖。
第8圖和第9圖分別表示本發明所述之帶有溝槽奈米管超級接面結構之電荷注入控制電阻器之剖面圖以及等效電路圖。
第10圖為第8圖所示結構之俯視圖。
第11圖為第8圖所示結構之另一個剖面圖。
第12圖表示第3圖所示之MOSFET元件之另一個實施例之剖面圖，該MOSFET元件帶有溝槽奈米管超級接面結構以及三個不同摻雜濃度之外延層。
第13圖和第14圖表示兩種MOSFET元件之兩個局部透視圖，這兩種MOSFET元件都帶有本發明所述之溝槽奈米管超級接面結構。
第15圖表示類似於第14圖所示之MOSFET元件之俯視圖。
第16圖和第17圖表示本發明所述之功率元件之封閉元件結構之俯視圖。
第18圖表示本發明所述之MOSFET元件之剖面圖，該MOSFET元件帶有溝槽奈米管超級接面結構以及專門配置之終止區。
第19圖至第31圖為一系列表示第3圖所示之MOSFET元件之製備過程之剖面圖。
第32圖至第41圖為一系列表示配置本發明所述之終止區之製備過程之剖面圖。
第42圖為本發明所述之平面終止區之俯視圖；第43圖和第44圖為其剖面圖；第45圖表示整個終止區上夾斷步驟之電壓分佈。
第46圖和第47圖表示帶有肖特基元件之IGBT元件之剖面圖。
參閱第3圖表示本發明所述之溝槽奈米管金屬氧化物半導體場效電晶體(MOSFET)元件100之剖面圖。MOSFET元件形成在一個P-型外延層110中，P-型外延層110位於N+基體105上。多個溝槽側壁奈米管外延層115和多個溝槽形成在外延層110中。溝槽側壁帶有微小的傾斜角，以形成一個錐形溝槽。作為示例，側壁可以略微傾斜87-89度。每個溝槽側壁都被N+溝槽側壁奈米管外延層115覆蓋。另一個輕摻雜的P-外延層116生長在N+溝槽側壁奈米管外延層115上方。由於剩餘的溝槽寬度和溝槽的傾斜角，P-外延層116的側壁朝著底部會合，並充分填充溝槽的底部。用氧化矽120等電介質填充溝槽剩餘的中心部分。MOSFET元件100更包含形成在溝槽頂部的溝槽閘極130，溝槽閘極130被閘極氧化層125填充包圍著，並藉由氧化矽層120與下面的N+溝槽側壁奈米管外延層115絕緣。MOSFET元件100更包含包圍著溝槽閘極130的本體區。 每個本體區都含有一個P-本體區135和一個重摻雜的P+本體接觸區140。MOSFET元件100更包含N+源極區145，N+源極區145沉積在MOSFET元件100之頂面附近，被P-本體區140和135包圍著。MOSFET元件100更包含一個阻擋金屬層150，以接觸源極區145和P+本體接觸區140，MOSFET元件100也可以連接到源極電極155上。閘極電極160也用於在溝槽閘極130上載入閘極電壓。當打開MOSFET元件100時，會在本體區135中鄰近溝槽閘極130的地方形成一個通道(圖中沒有表示出)。
P-外延層110和帶有側壁、被N-溝槽側壁奈米管外延層115和輕摻雜的N-外延層116覆蓋的溝槽，構成奈米管結構，以使MOSFET元件獲得電荷平衡。本發明提出了一種電荷平衡的高壓元件，該元件可以高效地製備。N-溝槽側壁奈米管外延層115，即奈米管，同P-外延層110的鄰近部分達到電荷平衡，使得N-溝槽側壁奈米管外延層115構成MOSFET的漂流區，該漂流區在斷開模式下耗盡。P-外延層116更包含一個位於本體區135下面的N-型植入區117，以便將通道連接到N-溝槽側壁奈米管外延層115中的漂流區上。藉由從另一側耗盡N-外延層，以及允許更高的電荷儲存在N-溝槽側壁奈米管外延層115中，P-外延層116可以提供進一步的電荷平衡，並改善Rdson。例如，如果再增加25%的P-型電荷儲存在P-外延層116中，那麼就可以再增加25%的N-型電荷儲存在N-溝槽側壁奈米管外延層115中，從而使Rdson降低25%。P-側壁層116也充分填充深溝槽的底部。這會使溝槽中剩餘縫隙的縱橫比較小，可以輕鬆地用氧化填充物120填充這些縫隙，從而避免了形成空洞等製備問題。氧化填充物120使溝槽閘極130與汲極電位絕緣，並 降低了閘-汲電容。
N-溝槽側壁奈米管外延層115大約1微米寬，在相鄰的N-溝槽側壁奈米管外延層115之間的P-外延層110大約6微米寬，這僅作為示例，不作為侷限。可以認為P-外延層110具有兩半，每一半的寬度都為3微米，並與N-溝槽側壁奈米管外延層115保持電荷平衡。N-溝槽側壁奈米管外延層115和P-外延層110電荷平衡的那部分，具有的電荷濃度約為1E12cm-2，因此P-外延層110的摻雜濃度為3.33E15cm-3，N-溝槽側壁奈米管外延層115的摻雜濃度為1E16cm-3。此外，1微米寬的P-外延層116所具有的電荷濃度為0.25E12cm-2，摻雜濃度為2.5E15cm-3，N-溝槽側壁奈米管外延層115的摻雜濃度可以升高到1.25E16cm-3，從而降低Rdson。
參閱第4圖表示本發明所述之溝槽奈米管(MOSFET)元件100-1之一個可選實施例。MOSFET元件100-1除了輕摻雜的N--外延層116-1(而不是第3圖所示之P-外延層116)生長在N+溝槽側壁奈米管外延層115上以外，其他都與第3圖所示之MOSFET元件100類似。因此，MOSFET元件100-1中並不需要N-型植入區117。輕摻雜的N--外延層116-1也充分填充溝槽之底部，以便於接下來形成氧化填充物120。由於形成N-溝槽側壁奈米管外延層115之後，可以利用同一個外延生長室製備N--外延層116-1，而要生長P-外延層116的話，就需要將晶片移至另一個生長室，因此使用N--外延層116-1比P-外延層116更易於製備。這也提高了元件的產量。在一個可選實施例中，N-外延層116-1可以用一個本質或輕摻雜的P--層代替。
參閱第5圖表示本發明所述之溝槽奈米管(MOSFET)元件100-2的 一個可選實施例。MOSFET元件100-2與第3圖所示之MOSFET元件100基本類似，只是溝槽較寬，使得形成在N+溝槽側壁奈米管外延層115上方的P-外延層116-2僅僅襯在溝槽內，並不能充分填充溝槽底部。相反，氧化填充物120-2填充了溝槽底部的絕大部分。
參閱第6圖表示本發明所述之溝槽奈米管(MOSFET)元件100-3的一個可選實施例。MOSFET元件100-3與第3圖所示之MOSFET元件100基本類似，只是P-外延層116-3除了在氧化填充物120-3下方的底部較厚以外，在大多數區域中P-外延層116-3都很薄，以至於在這些區域中N+外延層115-3都與它反向摻雜。可以選擇的是，如果在生長P-外延層116-3之後實施各向同性的輕蝕刻，那麼就可以形成這種結構。各向同性的蝕刻可以除去P-外延層116-3的邊緣部分，留下P-外延層116-3的底部。
參閱第7圖表示本發明所述之帶有溝槽奈米管結構之N-通道絕緣閘雙極電晶體(IGBT)元件101之剖面圖。該IGBT元件101形成在P-型外延層110中，P-型外延層110位於P-基體層105-1上，作為IGBT的集電極，N-通道截止層108沉積在P-外延層110和P+IGBT發射層105-1之間。IGBT元件101與第3圖所示之MOSFET元件之結構類似，也包含形成在外延層110中的多個溝槽奈米管，溝槽奈米管中含有多個溝槽。所形成的溝槽帶有側壁，側壁具有微小的傾斜角，並且每個溝槽側壁都覆蓋有一個N-溝槽側壁奈米管外延層115、一個P-外延層116以及用氧化矽120填充的溝槽中心部分。IGBT元件101更包含溝槽閘極130，溝槽閘極130形成在溝槽頂部，被閘極氧化層125填充包圍著，並藉由氧化矽層120與N+溝槽側 壁奈米管外延層115絕緣。IGBT元件101更包含溝槽閘極周圍的本體區。每個本體區都含有一個沉積在重摻雜的P+本體接觸區140下面的P-本體區135。IGBT元件101更包含N+源極區145，N+源極區145沉積在頂面附近，並被P-本體區135和140包圍著。IGBT元件101更包含一個阻擋金屬層150，阻擋金屬層150將源極區145和本體區140連接到發射極電極155上。再形成一個閘極電極160，以便在溝槽閘極130上載入閘極電壓。
P-外延層110和所形成的帶有被N-溝槽側壁奈米管外延層115覆蓋的側壁的溝槽，構成奈米管結構，以形成IGBT元件中電荷平衡的漂流區。
參閱第8圖表示本發明所述之帶有溝槽奈米管結構的電荷注入控制二極體之剖面圖。第9圖用第8圖中的肖特基二極體162以及P-N接面二極體161，表示電荷注入可調電阻器R1 163的等效電路之電路圖。電荷注入可調電阻器R1 163與P-N接面二極體161串聯，P-N接面二極體161與肖特基二極體162並聯。電阻器163可以整合到元件中，例如作為一個金屬和多晶矽電阻器，或者也可以外接到元件中，使用戶可以選擇所需的電阻值。P-型外延層110位於N-/N+基體層105上，作為P-N接面二極體和肖特基二極體的陰極。到P-外延層110的歐姆接觸形成在第三維中，一直到P+區176。肖特基二極體和P-N接面二極體都位於P-外延層110上，所形成的P-外延層110帶有多個溝槽奈米管，溝槽奈米管含有多個溝槽。所形成的溝槽帶有側壁，側壁具有微小的傾斜角，並且每個溝槽側壁都覆蓋有N-溝槽側壁奈米管外延層115、P-外延層116以及用氧化矽120填充的溝槽中心部分。較寬的溝槽可以形成在比其他 的氧化填充物120更寬更深的氧化填充物121上。當它們形成在同一半導體晶片上時，這樣有助於分離不同的元件。肖特基二極體含有一個N-區165，肖特基接觸金屬170覆蓋著N-區165的頂面。N-區165沉積在溝槽側壁奈米管外延層115上方，靠近氧化層120，並與P-外延層110和N-溝槽側壁奈米管外延層115相接觸。P-N接面二極體含有一個P-/P+區175/176，歐姆接觸金屬層180作為一個調製閘極，覆蓋在P-/P+區175/176的頂面上。P-區175與P-外延層110和溝槽側壁奈米管外延層115相接觸。電阻器R1 163控制P-N接面二極體中的注入能階，是藉由降低整個P-N接面二極體上的電壓(藉由電壓VR1=I二極體*R1)，致使P-N接面二極體上儲存的電荷量減少，反向恢復得到增強。電阻器R1的值較大，會使反向恢復增強，並且傳導率調製降低帶來更少的正向傳導。電阻器R1的值較小會帶來相反的效果。將肖特基二極體與P-N接面二極體並聯，會進一步減少P-N接面二極體中儲存的電荷量。改變電阻器R1 163的大小，可以控制P-N接面二極體161中儲存的電荷量以及二極體的性能。P-N接面二極體降低了高壓(HV)肖特基二極體的汲電流，優化了複合元件的正向電壓降Vf。
參閱第10圖以及第11圖之剖面圖所示，肖特基二極體(用N-區165表示)以及P-N接面二極體(用P-/P+區175/176表示)位於外延層110的同一條紋上。
參閱第12圖表示類似於第3圖所示之MOSFET元件，帶有溝槽奈米管結構之MOSFET元件102之側面剖面圖。P-外延層110作為一個分級的外延層110'，更帶有藉由三種不同摻雜濃度的三步外延生長形成三個P-摻雜層110-1、110-2和110-3。外延摻雜濃度隨高度 的增加而增大，也就是說底部P-摻雜層110-1的摻雜濃度最低，頂部P-摻雜層110-3的摻雜濃度最高。分級的外延層110'藉由將擊穿區從外延層的頂部往下移，提高了元件的UIS。而且，藉由將擊穿場下移到P-外延層110中，使注入到P-外延區110的電荷多於N-溝槽側壁奈米管外延層115，也可以提高UIS。儘管，此例中用於製備分級外延層的是三步外延層，但是也可以使用更多步的外延層。還可選擇使用單一逐漸分級的外延層，其摻雜濃度從上到下逐漸降低。
參閱第13圖和第14圖表示作為條紋元件之兩種不同元件之側面透視圖。為了解釋說明，此處沒有表示出源極和本體區--僅表示出閘極和外延層。第13圖表示的元件類似於第4圖所示的元件100-1，第14圖表示的元件類似於第3圖所示的元件100。第15圖表示第14圖所示元件之俯視圖，不連續區122位於閘極130中，靠近部分P-外延層116。掩膜使氧化填充物120在製備過程中，不在區域122中被蝕刻。同一掩膜也使靠近不連續區122的P-外延層116中不被植入P-型植入物117，P-型植入物117在其他地方沿溝槽植入。在帶有裸露P-外延層116的地方，為了保持電荷平衡，可以建立從源極電壓到P-外延層116的連接。也可選擇，不在閘極130中形成不連續區122，形成P-型植入物117的植入過程並非表層植入，而是帶有掩膜的，從而允許P-外延層116的區域非反向摻雜，並連接到源極電壓上。也可以選擇的是，這種效果也可以藉由帶有掩膜的P-型植入步驟達到，從而形成P-型植入物117來創造P-外延層116被暴露的區域。
參閱第16圖和第17圖表示帶有封閉元件之MOSFET元件之俯視圖。 如第16圖和第17圖所示之封閉元件與條紋結構相比，在一個6×6的帶有3微米之矽臺面結構之封閉元件(即2.5微米的P-區、0.25微米的N-環以及3微米的溝槽開口)中，如第16圖和第17圖所示之封閉元件能夠降低約30%的Rds電阻。第16圖表示不帶主動極或本體區之奈米管結構之封閉元件佈局。P-外延層110位於每個封閉元件的中心，並被N-溝槽側壁奈米管外延層115和N--外延層116包圍著。溝槽閘極130和閘極氧化物125圍繞著封閉元件。第17圖中所表示的是源極和本體區，P+本體接觸140位於每個封閉元件的中心，被N+源極區145包圍著。為了簡化，圖中沒有表示出P-植入區117。也可選擇，在溝槽閘極和半導體的位置互換時，使用帶有不連續閘極的封閉元件，使半導體基體(包含源極和本體)包圍溝槽閘極，溝槽閘極位於封閉元件的中心。
參閱第18圖表示類似於第12圖所示之MOSFET元件102，帶有溝槽奈米管結構之MOSFET元件之側面剖面圖。P-外延層110作為三個P-摻雜層110-1、110-2和110-3，是藉由從上到下依次遞減的三種不同摻雜濃度的外延生長過程形成的。MOSFET元件更包含一個高壓終止區，帶有一個又寬又深的終止溝槽189(例如30微米)，並用介質材料190和氧化物120填充終止溝槽189。所形成的終止溝槽189帶有一個用氧化物120填充的溝槽的初始網路，它可以與主動溝槽的氧化物120同時形成。半導體臺面結構(圖中沒有表示出)位於氧化物120的網路之間；然後蝕刻掉半導體臺面結構，將介質材料190填充到所產生的縫隙中。終止區的終點為沉積在晶片週邊邊緣上的鋸齒街區195。
參閱第19圖至第31圖為一系列側面剖面圖，表示帶有類似於第3 圖所示奈米管之自對準的高壓(HV)半導體功率元件之製備過程。第19圖表示起始N+半導體基體205，即重摻雜的N+矽基體，承載著生長在基體205上方的P-型外延層210。P-型外延層210也可以看出是上層半導體基體，N+半導體基體205可看作是下層半導體基體。可以選擇生長P-型外延層210，具有三種或更多種不同的P-摻雜濃度，或者具有逐漸分級的摻雜濃度，其摻雜濃度從上到下逐漸降低。然後，形成氧化層211和氮化矽(Si3N4)層212，作為硬掩膜。在第20圖中，利用溝槽掩膜(圖中沒有表示出)首先蝕刻硬掩膜，包含氧化層211和氮化矽層212。然後進行矽蝕刻，在外延層210中打開溝槽213。打開溝槽213的溝槽寬度約為3.5微米，溝槽深度約為36至40微米，側壁角約為88度。N奈米管層215外延生長在N奈米管層215上方，厚度約為0.25至0.5微米，用砷摻雜物摻雜，如第21圖所示。P-外延層216可以生長在N奈米管層215上方。如第22圖所示，由於溝槽213的尺寸和傾斜的側壁，N--外延層216充分填充了溝槽的底部。然後，如第24圖所示，將很薄的高密度等離子(HDP)氧化層220沉積在溝槽內，並填充溝槽。
參閱第24圖中，利用背部蝕刻過程和/或化學機械平整化(CMP)技術，除去頂面上的氧化矽(SiO2)220，直到氮化矽層212裸露出來。使用溝槽閘極掩膜(圖中沒有表示出)，將氧化層220蝕刻到大約1.5至2.0微米的深度。如第25圖所示，利用N-型植入，在P-外延層216的裸露側壁上形成N-型植入物217。
參閱第26圖中，形成厚度約為350-1200埃的閘極氧化層225，沿P-外延層216覆蓋在側壁上。沉積閘極多晶矽層230，最好選用N+ 原位摻雜多晶矽層。背部蝕刻多晶矽230，利用CMP技術平整其頂面，並除去硬掩膜氧化層211和氮化矽(Si3N4)層212。進一步蝕刻多晶矽層230，形成一個輕微凹陷的閘極230，閘極多晶矽230的頂面比臺面結構表面大約低0.3微米。然後在頂面上方生長一個襯墊氧化層232。
參閱第27圖中，利用高能量硼或P-本體摻雜植入，形成本體區235。進行高能本體摻雜植入時，要帶有一定的傾斜角，以阻止由於溝槽側壁的負臺面結構角，而在溝槽側壁附近的區域中產生遮蔽。升高溫度後，進行本體摻雜驅動，將本體區235擴散到P-外延層210、N-奈米管層215和N--外延層216中。然後，在接近零度時，進行重硼植入，以便在本體區235上方的頂面附近形成P+本體接觸區240。在第28圖中，利用源極掩膜(圖中沒有表示出)進行低能含磷的N+植入，以形成包圍在P-本體區235和P+區240中的N+源極區245。在900攝氏度下，利用退火技術進行植入啟動30分鐘。在一個可選實施例中，在一個更高的溫度下進行N-型植入，以便在P-本體區235下方產生埋入的N-型區，同樣用於將MOSFET通道區連接到作為N-型植入物217的N外延層215。
然後，在頂面上形成一個氮化矽(Si3N4)硬掩膜層(圖中沒有表示出)。利用終止掩膜(圖中沒有表示出)在終止區中進行各向同性的矽蝕刻，以便在氧化矽層之間的終止區中的臺面結構區域中打開溝槽(圖中沒有表示出)，然後用電介質或SiO2填充蝕刻後的臺面結構溝槽(例如第18圖所示的介質層190)。背部蝕刻介質層190，直到硬掩膜層裸露出來，然後蝕刻並除去硬掩膜(圖中沒有表示出)。在終止區中的這些技術如第11圖所示。如第 29圖所示的那樣，沉積含有硼酸的矽玻璃(BPSG)鈍化層250。在第30圖中，利用接觸掩膜(圖中沒有表示出)，打開穿過BPSG層250的接觸開口。在第31圖中，在頂面上沉積一個金屬層，然後利用金屬掩膜(圖中沒有表示出)，在金屬層上形成源極金屬260-S和閘極墊(圖中沒有表示出)的圖案。在基體205的底部也形成一個金屬層，以製備汲極金屬205-D，從而完成了整個超級結奈米管MOSFET 200。
參見第32圖至第41圖為一系列側面剖面圖，表示一種帶有如第3圖所示之奈米管的自對準高壓(HV)半導體功率元件的終止區之製備過程。第32圖表示初始N+半導體基體205(例如重N+摻雜矽基體)，承載著P-型外延層210，P-型外延層210作為層210-1、210-2和210-3，用三種不同的摻雜濃度，在基體205的上方生長。所生長的P-型外延層210也可以具有逐漸分級的摻雜濃度，其摻雜濃度從上到下逐漸降低。然後，形成氧化層和氮化矽(Si3N4)層212，作為硬掩膜。在第33圖中，利用溝槽掩膜(圖中沒有表示出)，首先蝕刻硬掩膜212，包含一個氧化層和一個氮化矽層。然後，利用矽蝕刻打開主動溝槽213b和終止溝槽213a，進入外延層210中。打開的溝槽深度約為36至40微米，側壁角約為88度。終止溝槽213a的寬度可能大於主動區溝槽213b，以保證如圖所示的那樣，填充在這些溝槽中的氧化物到達溝槽底部。然後，在溝槽213a和213b的側壁上外延生長一個N-外延奈米管層215，其厚度約為0.25至0.5微米，並用砷摻雜物摻雜，隨後在N-奈米管215上方外延生長一個P-外延層216。如第34圖所示，在溝槽中沉積並填充有薄HDP氧化層220。要注意的是，由於終止溝槽213a 的寬度較大，雖然P-外延層216充分了填充主動區域溝槽213b的底部，卻僅能填充終止溝槽213a的一薄層襯裏。因此，氧化層220在終止溝槽213a中填充的深度遠小於在主動溝槽213b中的深度。可在邊界區域使用又深又寬的氧化物填充較寬溝槽，以便在同一半導體晶片上製備不同元件時，區分這些不同的元件。
然後，利用背部蝕刻技術和/或化學機械平整化(CMP)技術，除去頂面上的氧化層220，直到氮化矽層212裸露出來。這時，會在終止區中形成一個氧化立柱223的網路，在該網路中含有半導體臺面結構224。終止區覆蓋著寬溝槽213a，利用覆蓋著終止區的溝槽閘極掩膜218，蝕刻主動區溝槽213b中的氧化層220。然後，如第35圖所示，沿P-外延層216的裸露側壁進行N-型植入，製備N-型植入區217。如第36圖所示，藉由閘極氧化層225的襯墊，製備多晶矽閘極230。此時，可以除去主動區上的硬掩膜212。然後，如上所述，形成P-本體基極區235和重P+區240。利用源極掩膜(圖中沒有表示出)，如上所述，在主動單元區中，植入並形成N+源極區245，如第37圖所示。在第38圖中，利用終止硬掩膜249，將溝槽閘極掩膜218和剩餘的硬掩膜212一起除去。在第39圖中，利用矽蝕刻，蝕刻半導體臺面結構224，即外延層210-1、210-2和210-3，在終止區的氧化層220之間，留下臨時蝕刻溝槽222。在第40圖中，用介質材料290填充在終止區中的氧化層220之間的蝕刻溝槽222，以便填充終止區中的蝕刻臺面結構，形成又深又寬的終止氧化溝槽289。在第41圖中，除去終止硬掩膜249，進行如第29圖至第31圖所示的後續處理技術，完成帶有如第18圖所示之特製終止區之MOSFET元件的製備。
參閱第42圖為俯視圖，第43圖和第44圖分別為帶有平面終止結構的如第42圖所示之MOSFET元件之沿A-A'線和B-B'線之剖面圖。為了清晰起見，雖然大體表示出了由金屬層形成的電連接，但是俯視圖並沒有表示出金屬、氧化物和鈍化層之頂部，如第18圖和第41圖所示，平面終止是寬氧化溝槽的一個可選實施例。在平面終止結構中，終止區199'包含類似於主動區之臺面結構110'，臺面結構110'位於氧化層120'之間，用側壁填充在溝槽中，並由N溝槽側壁奈米管外延層115'覆蓋著。終止單元不具有主動單元198'的源極/本體區135、140和145。相反，如第42圖至第44圖所示，P-臺面結構和N-外延層由金屬層150-1至150-5連接，以使每個終止單元閉鎖一個特定的夾斷電壓VPT。鈍化層195'可以覆蓋金屬層150-1至150-5。
最後一個主動單元(如圖中左側所示)，在源極電壓為0伏時，藉由金屬層150-1，短接至第一終止單元的P-臺面結構(以及在中間的多晶矽塊130')。更確切地說，金屬層150-1連接了P-區135'內的P+區140'。P-臺面結構110'和周圍的N-溝槽側壁奈米管外延層115'耗盡，將N-外延層的電壓升高至夾斷電壓VPT1，即N-外延層和P-臺面結構耗盡時的電壓。N-溝槽側壁奈米管外延層115'連接到包圍著第一終止單元的N+區140"的N-區135"上，第一終止單元的N+區140"藉由金屬層150-2短接至下一個終止單元(右側的下一個單元)的P-臺面結構上，由於在該單元中發生耗盡，使電壓又升高了一個VPT1，從而使此時的總電壓為VPT2 2*VPT1。直到達到元件的工作電壓(汲極電壓)時，這種情況才會停止。參見第45圖，首先將源極電位作為參考電壓，例如金屬 層150-1的V=0，電壓以夾斷步階155的漸進式的方式逐漸增加，使得金屬層150-2處的電壓為VPT1。電壓遞增至VPT1，然後達到金屬層150-3處的VPT2，最終升高到元件電壓，即在最後一個金屬層150-n處的600伏預設電壓，如第45圖中最靠近半導體晶片邊緣處的劃線所示。
在氧化溝槽120'內形成多晶矽塊130'，以防止電荷和汙物進入氧化溝槽中的氧化物，從而提高了元件的可靠性。由於平面終止結構與寬氧化溝槽相比，需要更大的橫向距離，以阻隔工作電壓，因此該平面終止結構不如第18圖所示之寬氧化溝槽終止結構緊湊。更應注意的是，與上述主動單元區中的溝槽類似，在終止區中打開用氧化矽填充的溝槽，也帶有稍稍傾斜的側壁。
參閱第46圖表示一種類似於第7圖所示之IGBT元件101'之剖面圖，該IGBT元件101'與類似於第4圖所示之肖特基元件162'相整合。帶有又深又寬氧化填充物121的寬溝槽，將元件分開。在這種情況下，將半導體基體背部研磨到又深又寬的氧化填充物121的底部。在半導體材料的底部，植入N-型層108'和P-型層105-1'。由於IGBT不像MOSFET那樣具有嵌入式二極體，因此該實施例十分有用。應明確的是，如同美國專利申請號為12/484,166中所述的那樣，對不帶有初始外延層的單一P-基體進行背部研磨和植入後，可以用這種單一P-基體構成元件。如第47圖所示，製備該結構也可以無需背部研磨，以便將P-型層150-1"植入到一部分N-型半導體基體108"中。
儘管本發明已經詳細說明了現有的較佳實施例，但不應作為本發明的侷限。例如，儘管以上說明所述的是n-通道元件，但是本發 明藉由將摻雜區域的導電類型反轉，也可用於P-通道元件。可以製備各種不同的元件，包含那些帶有平面閘極的元件。本領域的技術人員閱讀上述詳細說明後，各種變化和修正無疑將顯而易見。因此，所附的申請專利範圍應涵蓋本發明的真實意圖和範圍內的全部變化和修正。
儘管本發明的內容已經藉由上述較佳實施例作了詳細介紹，但應當認識到上述的描述不應被認為是對本發明的限制。在本領域技術人員閱讀了上述內容後，對於本發明的多種修改和替代都將是顯而易見的。因此，本發明的保護範圍應由所附的申請專利範圍來限定。
100‧‧‧MOSFET元件
105‧‧‧N+基體
110‧‧‧外延層
115‧‧‧溝槽奈米管
116‧‧‧P-外延層
117‧‧‧N-型植入區
120‧‧‧氧化填充物
125‧‧‧閘極氧化層
130‧‧‧溝槽閘極
135‧‧‧本體區
140‧‧‧P+本體接觸區
145‧‧‧N+源極區
150‧‧‧阻擋金屬層
155‧‧‧源極電極
160‧‧‧閘極電極

Claims (28)

  1. 一種帶有溝槽-氧化物-奈米管超級接面之元件結構，其包含：第一導電類型之一第一半導體層以及第二導電類型之一第二半導體層，該第二半導體層沉積在該第一半導體層之上方；在該第二半導體層中打開之複數個溝槽，垂直延伸到該第一半導體層；形成在該複數個溝槽之側壁上的第一導電類型之一第一外延層；以及形成在該第一外延層上之一第二外延層；其中該第一外延層與相鄰的第二半導體層之間達到充分的電荷平衡。
  2. 如申請專利範圍第1項所述之元件結構，其中在至少某些該溝槽中，該第二外延層充分填充了未被該第一外延層佔據的縫隙之底部。
  3. 如申請專利範圍第2項所述之元件結構，其中該第二外延層之側壁朝著該溝槽之底部合併在一起。
  4. 如申請專利範圍第1項所述之元件結構，其中該溝槽之側壁具有一定的角度，以形成錐形溝槽，並朝著該溝槽之底面匯聚。
  5. 如申請專利範圍第1項所述之元件結構，其中該第二外延層為第一導電類型。
  6. 如申請專利範圍第1項所述之元件結構，其中該第二外延層為第二導電類型或本質半導體材料。
  7. 如申請專利範圍第1項所述之元件結構，其更包含：在一中心縫隙中之一第一電介質填充物，該中心縫隙在該溝槽的中心，未被該第二外延層佔據。
  8. 如申請專利範圍第1項所述之元件結構，其更包含：一閘極電極，其沉積在至少某些該溝槽頂部中。
  9. 如申請專利範圍第8項所述之元件結構，其更包含：位於該閘極電極下方之一介質層。
  10. 如申請專利範圍第1項所述之元件結構，其更包含：形成在相鄰該溝槽之間之一肖特基二極體和一P-N接面二極體。
  11. 如申請專利範圍第10項所述之元件結構，其中該P-N接面二極體是一電荷注入可控二極體，其與一電荷注入可控電阻器串聯，並與該肖特基二極體並聯。
  12. 如申請專利範圍第1項所述之元件結構，其中該第二半導體層在兩個相鄰該溝槽之間的寬度，遠大於該第一外延層的寬度。
  13. 如申請專利範圍第1項所述之元件結構，其中該第二半導體層在兩個相鄰該溝槽之間的寬度，至少是該第一外延層的寬度的三倍。
  14. 如申請專利範圍第1項所述之元件結構，其中該元件結構更包含一金屬氧化物半導體場效電晶體(MOSFET)。
  15. 如申請專利範圍第1項所述之元件結構，其中該元件結構更包含一絕緣閘雙極電晶體(IGBT)。
  16. 如申請專利範圍第1項所述之元件結構，其中該元件結構更包含與一二極體整合的一絕緣閘雙極電晶體(IGBT)。
  17. 如申請專利範圍第1項所述之元件結構，其中該第二半導體層具有分級之摻雜結構，其摻雜濃度從上到下逐漸降低。
  18. 如申請專利範圍第7項所述之元件結構，其更包含：具有介質溝槽之一終止結構，其包含由該第一電介質填充物和一第二電介質填充物形成之一介質立柱之一網路，該第一電介質填充物和該第二電介質填充物形成在該網路內該介質立柱之間。
  19. 如申請專利範圍第7項所述之元件結構，其中至少一第二元件沉積在半導體基體上，其中沉積在相鄰元件之間之該溝槽具有較大的溝槽寬度。
  20. 如申請專利範圍第1項所述之元件結構，其中該元件結構更包含具有條紋結構之電晶體單元。
  21. 如申請專利範圍第1項所述之元件結構，其中該元件結構更包含具有封閉式單元佈局之電晶體單元。
  22. 如申請專利範圍第1項所述之元件結構，其更包含：由包含複數個終止單元之一陣列構成之一終止區，在主動單元之介面處帶有一第一終止單元，其中每一終止單元更包含：該第二半導體層之一臺面結構，並且該第一外延層形成在其側壁上，該第二外延層形成在該第一外延層上，該臺面結構靠近帶有介質填充物之該溝槽；第一導電類型之一第一區域，形成在該臺面結構之頂面中；以及第二導電類型之一第二區域，形成在該臺面結構之頂面中，與該臺面結構中之該第一區域分開，其中大多數該終止單元之該第一區域都電連接到相鄰該終止單元之該第二區域上。
  23. 一種帶有溝槽-氧化物-奈米管超級接面之元件結構之製備方法，其包含：在第二導電類型之一第二半導體層中蝕刻複數個溝槽； 在該複數個溝槽中，生長第一導電類型之一第一外延層；以及在該第一外延層之上方，生長一第二外延層；其中第一導電類型之一第一半導體層位於該第二半導體層之下方，以及其中該第一外延層觸及該第一半導體層，且該第一外延層與周圍之第二半導體層達到電荷平衡。
  24. 如申請專利範圍第23項所述之製備方法，其中生長該第二外延層，使該第二外延層充分填充該溝槽之底部。
  25. 如申請專利範圍第23項所述之製備方法，其更包含：生長該第二外延層後，用一電介質填充該溝槽中剩餘之一縫隙。
  26. 如申請專利範圍第25項所述之製備方法，其更包含：用該電介質填充該溝槽中剩餘之該縫隙後，背部蝕刻該電介質，並在至少某些該溝槽之頂部中形成一溝槽閘極電極。
  27. 如申請專利範圍第25項所述之製備方法，其更包含：在蝕刻該溝槽時，同時蝕刻一終止區中之該溝槽，以便用留在介質填充溝槽之間之一半導體臺面結構，在該終止區中形成介質填充溝槽之網路；以及蝕刻掉該終止區中之該半導體臺面結構，並用一第二介質填充物填充空間，以便在該終止區中形成又寬又深之一電介質溝槽。
  28. 一種製備電介質溝槽之方法，其包含：在一半導體層中製備一溝槽之一網路，並用一第一電介質填充該溝槽，以便形成含有一半導體臺面結構之一電介質立柱之網路；蝕刻掉該電介質立柱之網路內之該半導體臺面結構，並用一第二電介質填充縫隙，從而構成又寬又深之一電介質溝槽。
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US9685511B2 (en) * 2012-05-21 2017-06-20 Infineon Technologies Austria Ag Semiconductor device and method for manufacturing a semiconductor device
CN103681778B (zh) * 2012-09-09 2017-04-26 朱江 一种沟槽电荷补偿肖特基半导体装置及其制备方法
CN103413763B (zh) * 2013-08-22 2016-09-28 上海华虹宏力半导体制造有限公司 超级结晶体管及其形成方法
CN104681438B (zh) * 2013-11-27 2017-10-20 上海华虹宏力半导体制造有限公司 一种半导体器件的形成方法
TWI567974B (zh) * 2014-07-28 2017-01-21 萬國半導體股份有限公司 用於納米管ｍｏｓｆｅｔ的端接設計
JP2017050423A (ja) * 2015-09-02 2017-03-09 株式会社東芝 半導体装置の製造方法
CN105405889B (zh) * 2015-11-04 2019-01-08 中国科学院微电子研究所 一种具有全方位电流扩展路径的沟槽mosfet
CN105655385B (zh) * 2016-01-15 2018-08-21 上海华虹宏力半导体制造有限公司 沟槽型超级结器件的制造方法
CN106229335A (zh) * 2016-08-01 2016-12-14 上海华虹宏力半导体制造有限公司 深沟槽填充方法
WO2018107429A1 (zh) * 2016-12-15 2018-06-21 深圳尚阳通科技有限公司 超结器件及其制造方法
CN106847923B (zh) * 2017-02-08 2019-10-11 上海华虹宏力半导体制造有限公司 超结器件及其制造方法
CN107068735A (zh) * 2017-03-16 2017-08-18 上海华虹宏力半导体制造有限公司 沟槽型超级结的制造方法
CN107180865B (zh) * 2017-06-30 2020-01-07 东南大学 一种低噪声低损耗绝缘栅双极型晶体管
CN107910374A (zh) * 2017-12-13 2018-04-13 深圳市晶特智造科技有限公司 超结器件及其制造方法
CN109273439A (zh) * 2018-09-14 2019-01-25 深圳市心版图科技有限公司 一种功率器件保护芯片及其制作方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040185665A1 (en) * 2003-03-07 2004-09-23 Fuji Electric Holdings Co., Ltd. Fabrication method of semiconductor wafer
US20060180947A1 (en) * 2005-02-15 2006-08-17 Semiconductor Components Industries, Llc. Semiconductor device having deep trench charge compensation regions and method
US20060214221A1 (en) * 2003-05-20 2006-09-28 Ashok Challa Power semiconductor devices and methods of manufacture

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4088033B2 (ja) * 2000-11-27 2008-05-21 株式会社東芝 半導体装置
EP1261036A3 (en) * 2001-05-25 2004-07-28 Kabushiki Kaisha Toshiba Power MOSFET semiconductor device and method of manufacturing the same
CN103199017B (zh) * 2003-12-30 2016-08-03 飞兆半导体公司 形成掩埋导电层方法、材料厚度控制法、形成晶体管方法
TWI401749B (zh) * 2004-12-27 2013-07-11 Third Dimension 3D Sc Inc 用於高電壓超接面終止之方法
US7679146B2 (en) * 2006-05-30 2010-03-16 Semiconductor Components Industries, Llc Semiconductor device having sub-surface trench charge compensation regions
US7750398B2 (en) * 2006-09-26 2010-07-06 Force-Mos Technology Corporation Trench MOSFET with trench termination and manufacture thereof
US8148275B2 (en) * 2007-12-27 2012-04-03 Canon Kabushiki Kaisha Method for forming dielectric films
JP5365016B2 (ja) * 2008-02-06 2013-12-11 富士電機株式会社 半導体素子およびその製造方法
CN100589253C (zh) * 2008-04-29 2010-02-10 西安理工大学 氧化物填充扩展沟槽栅超结mosfet及其制造方法
US20090315104A1 (en) * 2008-06-20 2009-12-24 Force Mos Technology Co. Ltd. Trench MOSFET with shallow trench structures

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040185665A1 (en) * 2003-03-07 2004-09-23 Fuji Electric Holdings Co., Ltd. Fabrication method of semiconductor wafer
US20060214221A1 (en) * 2003-05-20 2006-09-28 Ashok Challa Power semiconductor devices and methods of manufacture
US20060180947A1 (en) * 2005-02-15 2006-08-17 Semiconductor Components Industries, Llc. Semiconductor device having deep trench charge compensation regions and method

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