WO2018107429A1 - 超结器件及其制造方法 - Google Patents

超结器件及其制造方法 Download PDF

Info

Publication number
WO2018107429A1
WO2018107429A1 PCT/CN2016/110085 CN2016110085W WO2018107429A1 WO 2018107429 A1 WO2018107429 A1 WO 2018107429A1 CN 2016110085 W CN2016110085 W CN 2016110085W WO 2018107429 A1 WO2018107429 A1 WO 2018107429A1
Authority
WO
WIPO (PCT)
Prior art keywords
filling layer
type
trench
layer
filling
Prior art date
Application number
PCT/CN2016/110085
Other languages
English (en)
French (fr)
Inventor
曾大杰
肖胜安
Original Assignee
深圳尚阳通科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳尚阳通科技有限公司 filed Critical 深圳尚阳通科技有限公司
Priority to PCT/CN2016/110085 priority Critical patent/WO2018107429A1/zh
Publication of WO2018107429A1 publication Critical patent/WO2018107429A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present invention relates to the field of semiconductor integrated circuit fabrication, and more particularly to a super junction device; and to a method of fabricating a superjunction device.
  • the super junction structure is an N-type column and a P-type column structure which are alternately arranged. If a super-junction structure is used to replace the N-type drift region in a Vertical Double-diffused Metal-Oxide-Semiconductor (VDMOS) device, a conduction path is provided through the N-type pillar in an on state, and when conducting The P-type column does not provide a conduction path; in the off state, the PN column is subjected to a reverse bias voltage to form a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET).
  • MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor
  • FIG. 1 it is a structural diagram of a conventional super junction device.
  • the super junction device is a super junction power device.
  • an N-type super junction device is taken as an example, and the doping type of the device can be replaced accordingly.
  • a P-type super junction device is obtained, and the P-type super junction device will not be described in detail herein.
  • the N-type super junction device includes:
  • the gate 1 is usually composed of polysilicon, that is, the gate 1 is a polysilicon gate, and the thickness is usually between.
  • the gate oxide layer 2 is used to achieve the isolation of the gate 1 and the channel.
  • the thickness of the gate oxide layer 2 determines the withstand voltage of the gate 1, and in order to ensure a certain withstand voltage of the gate 1, the gate oxide layer 2 Thickness is generally greater than
  • the source region 3 is composed of an N-type heavily doped region, that is, an N+ region, and the doping amount of the source region 3, that is, the implantation dose of the ion implantation doping is usually 1 e15/cm 2 or more.
  • the doping amount of the P-type channel region 5 and the P-type channel region 5 is usually between 3e13/cm 2 and 1e14/cm 2 , and the doping of the P-type channel region 5 determines the threshold voltage of the device, doping. The higher the dose, the higher the threshold voltage of the device.
  • the surface of the P-type channel region 5 covered by the gate 1 is used to form a channel.
  • the hole collecting region 4 is composed of a P-type heavily doped region formed on the surface of the P-type channel region 5, that is, a P+ region.
  • the N-type epitaxial layer 7 has a doped body concentration of usually between 1e15/cm 3 and 5e16/cm 3 , and the N-type epitaxial layer 7 serves as a drift region of the device, and the thickness of the N-type epitaxial layer 7 determines the device's impact. Wear voltage.
  • the P-type column 6, the P-type column 6 and the N-type column composed of the N-type epitaxial layer 7 between the P-type columns 6 are alternately arranged to form a super-junction structure, and in the super-junction structure, each P-type column 6 and the corresponding N-type
  • the pillars are complementarily doped and realize the lateral depletion of the N-type pillars, and the N-type drift region consumption in the entire super-junction structure can be easily realized by mutual lateral depletion between the P-type pillars 6 and the adjacent N-type pillars. As a result, high doping concentration and high breakdown voltage can be achieved at the same time.
  • the P-type column 6 is usually implemented in two ways, one is formed by multiple epitaxy, and the other is formed by trenching and P-type silicon filling.
  • the N-type epitaxial layer 7 is formed on the semiconductor substrate 9.
  • the semiconductor substrate 9 is N-doped with a bulk concentration of 1e19/cm 3 or more, and its high doping concentration is to reduce the resistance of the semiconductor substrate 9.
  • the super junction power device is a MOSFET device
  • a drain region is formed of an N-type highly doped semiconductor substrate 9, and a drain composed of a back metal layer is formed on the back surface of the semiconductor substrate 9.
  • the method of trenching and P-type silicon filling is simple and efficient.
  • the P-type column 6 is formed by the method of trenching and P-type silicon filling, and is introduced as follows:
  • a trench is formed in the N-type epitaxial layer by a photolithography etching process.
  • the trench is filled with P-type silicon.
  • the method of trenching and P-type silicon filling is simple and efficient.
  • the P-type column 6 is formed by the method of trenching and P-type silicon filling, and is described as follows:
  • a trench is formed in the N-type epitaxial layer by a photolithography etching process.
  • FIG. 2 it is a schematic view of an ideal condition of a trench of a conventional superjunction device; it can be seen that a plurality of trenches 102a are formed in the N-type epitaxial layer 101a.
  • the N-type epitaxial layer 101a corresponds to the N-type epitaxial layer 7 in FIG. 1, and the trench 102a is the formation region of the P-type pillar 6 in FIG.
  • the side surface of the groove 102a is a vertical structure, and the side inclination angle thereof, that is, the angle corresponding to the mark 130a is 90 degrees.
  • FIG. 3 it is a schematic diagram of the actual condition of the trench of the existing super junction device; in the actual process, a plurality of trenches 102b are formed in the N-type epitaxial layer 101b; wherein, the N-type epitaxial layer 101b and FIG.
  • the N-type epitaxial layer 7 corresponds to the groove 102b which is the formation region of the P-type pillar 6 in FIG. It can be seen that the side surface of the groove 102b is an inclined structure, and the side inclination angle thereof, that is, the angle corresponding to the mark 130b is 88.5 degrees.
  • the trench is subjected to P-type silicon filling to form a super-junction structure in which the N-type pillar and the P-type pillar are alternately arranged.
  • FIG. 5 it is a schematic diagram of a super junction structure when the trench of the existing super junction device is in an ideal state; and FIG. 2
  • the P-type pillar 403a is composed of P-type silicon filled in the trench 102a
  • the N-type pillar 402a is composed of the N-type epitaxial layer 101a between the trenches 102a
  • the P-type pillar 403a and the N-type pillar 402a are alternately arranged.
  • Super junction structure At the bottom of the super junction structure is a buffer layer 401a, which is also composed of an N-type epitaxial layer 101a, that is, the buffer layer 401a is composed of an N-type epitaxial layer 101a at the bottom of the trench 102a.
  • the buffer layer 401a there is a semiconductor substrate 9 shown in FIG.
  • FIG. 6 it is a schematic diagram of a super junction structure when the trench of the conventional super junction device is in an actual state; and as compared with FIG. 3, the P-type pillar 403b is composed of P-type silicon filled in the trench 102b, and the N-type is shown.
  • the pillars 402b are composed of an N-type epitaxial layer 101b between the trenches 102b, and the P-type pillars 403b and the N-type pillars 402b are alternately arranged to constitute a superjunction structure.
  • a buffer layer 401b which is also composed of an N-type epitaxial layer 101b, that is, the buffer layer 401b is composed of an N-type epitaxial layer 101b at the bottom of the trench 102b.
  • the buffer layer 401b is composed of an N-type epitaxial layer 101b at the bottom of the trench 102b.
  • a semiconductor substrate 9 shown in FIG.
  • the vertical structure on the side is difficult to produce stably. If the trench becomes wider than the top trench due to the change of the process, the trench will fill after filling. Defects cause increased leakage of the device, and the groove has a certain degree of tilt angle to improve the stability and uniformity of the etching process, which improves the leakage and breakdown voltage uniformity of the device.
  • the angle of the trench etch corresponds to the side angle of the etched trench.
  • the angle of the trench etching is usually 88.4. Between 89 degrees.
  • the side-tilted trenches are advantageous for both etching and filling, the side-tilted trenches themselves can reduce the breakdown voltage of the device, as explained below:
  • the comparison of the breakdown voltage of the device when the groove etching angle is different is given in Table 1.
  • the process conditions of the other structures are the same, such as using the same substrate structure.
  • the grooves forming the super-junction structure in the present invention are deep in depth, and are also generally referred to as deep grooves by those skilled in the art. It is assumed here that the deep groove of the device has a depth of 41 ⁇ m.
  • the breakdown voltage differs by more than 150V due to the different etching angles of the trenches.
  • the specific reasons are as follows:
  • FIG. 4 is an electric field intensity distribution curve of the device having the grooves shown in FIGS. 2 and 3 along the AA' position of FIG. 1; wherein the curve 201 corresponds to the groove having the side perpendicular as shown in FIG.
  • the corresponding groove has a side inclination of 88.45 degrees.
  • the X axis in Fig. 4 represents the longitudinal depth along the AA' position in Fig. 1, 0 ⁇ m represents the interface of silicon and silicon dioxide, and the unit is micron; the Y axis represents electric field strength in units of V/cm.
  • the electric field strength is substantially flat over the depth of the entire trench.
  • the electric field strength has a lower value at the top and bottom of the trench, wherein the location area indicated by the dashed box 203 is the top area of the trench, and the location area indicated by the dashed box 204 corresponds to the bottom area of the trench. . Comparing the curves 201 and 202, since the electric field intensity of the curve 202 is lowered at the top and bottom of the groove, the area covered by the curve 202 is small, that is, the breakdown voltage of the device corresponding to the curve 202 is lowered. This is consistent with the data in Table 1.
  • the width of the bottom of the trench is relatively small, that is, the bottom of the P-pillar 403b has a small width and a large top width;
  • the structure of the N-type pillar 402b is reversed, and the width of the top portion is small and the width of the bottom portion is large. Since the P-type pillar 403b is filled with a uniform doping structure, the width of the P-type pillar 403b is such that the P-type doping at different longitudinal positions is total.
  • the dose has an effect such that the final dose of P-type impurities at the bottom of the P-type column 403b is less, and the total dose of P-type impurities at the top of the P-type column 403b is larger; the corresponding N-type column 402b is the opposite, N-type
  • the total dose of N-type impurities at the bottom of column 402b is greater, while the total dose of N-type impurities at the top of N-type column 402b is less; for two adjacent P-type columns 403b and N-type columns 402b, at the top of the trench It is a small P and a small N, that is, a large amount of P-type impurities, and a small amount of N-type impurities.
  • At the bottom of the trench is P less than N. It can be seen that P-type impurities and N-type impurities are unbalanced at the top and bottom of the trench, respectively.
  • the doping concentration of the device can be increased at the same breakdown voltage because the P impurity and the N impurity can be completely depleted laterally, and it is desirable to be able to P and N at each position of the trench. That is, the total dose of P impurity and N impurity is just balanced. And if the angle is inclined, then naturally the top N is less, P is more, and the bottom is less P, N more. Thus the balance of P and N can only be at a certain position, and the balance of P-N cannot be achieved at all positions.
  • the P and N balances cannot be achieved at the top and bottom of the trench, which corresponds to the decrease in the electric field strength at the position corresponding to the broken lines 203 and 204 of the curve 202 in Fig. 4;
  • the problem of imbalance between P and N at the top and bottom of the trench occurs, so the electric field distribution of curve 201 is flat over the entire depth of the trench. It is because of the decrease in the electric field strength at the top and bottom of the trenches in the curve 202 that the breakdown voltage of the superjunction device having the laterally inclined trenches is drastically reduced by more than 150V.
  • the technical problem to be solved by the present invention is to provide a super junction device which can improve the balance of P and N type impurities at the top and bottom of the side inclined trenches, thereby increasing the breakdown voltage.
  • the present invention also provides a method of fabricating a superjunction device.
  • a plurality of trenches are formed on the first conductive type epitaxial layer, and the trench is filled with a second conductive type pillar, and is filled in the trench
  • the second conductive type pillar and the first conductive type pillar composed of the first conductive type epitaxial layer between the trenches are alternately arranged to form a superjunction structure
  • the side surface of the trench is an inclined structure such that the bottom width of the trench is smaller than the top width, thereby facilitating etching of the trench and filling of the second conductive type pillar to reduce filling defects;
  • the second conductive type pillar includes a first filling layer covering a side surface and a bottom surface of the trench, and a second filling layer superposed on the first filling layer
  • the first filling layer and the second filling layer are both doped with a second conductivity type and the doping concentration of the first filling layer is more than twice the doping concentration of the second filling layer
  • the second conductive type doping total amount of the second conductive type pillar at different depths of the trench is mainly determined by the first filling layer, thereby suppressing a bottom width of the trench.
  • the effect of the side slope structure less than the top width on the total amount of doping of the second conductivity type at different depths of the trench, thereby increasing the total amount of doping and adjacent of the second conductivity type at different depths of the trench A balance of the total amount of doping of the first conductivity type of the first conductivity type column.
  • a further improvement is that the first conductive type epitaxial layer is a first conductive type silicon epitaxial layer, the first filled layer is a second conductive type silicon epitaxial layer, and the second filled layer is a second conductive type silicon epitaxial layer a layer, a second conductivity type polysilicon layer or a dielectric film.
  • a further improvement is that the sides of the grooves have an inclination of 88.4 degrees to 89 degrees.
  • the doping concentration of the first filling layer is: the total amount of impurities of the second conductive type of the first filling layer is a first value, and the total amount of impurities of the first conductive type column is a second a value, a difference between the first value and the second value is a third value, the third value is less than 10% of the first value, and the third value is less than 10% of the second value .
  • the second conductive type pillar further includes a third filling layer, the third filling layer is doped with a second conductivity type, and a doping concentration of the third filling layer is the first filling layer 1/2 or less of the doping concentration; the thickness of the third filling layer on the side of the trench is less than 1/5 of the width of the bottom of the trench, and the third filling layer is isolated from the second The filling layer and the side surface and the bottom surface of the trench are used to reduce diffusion of P-type impurities and N-type impurities between adjacent P-type pillars and N-type pillars to reduce on-resistance.
  • the second conductive type pillar further includes a fourth filling layer, the fourth filling layer is doped with a second conductivity type, and a doping concentration of the fourth filling layer is the second filling layer The doping concentration is more than twice the doping concentration, and the fourth filling layer is superposed on the surface of the second filling layer.
  • a further improvement is that the doping concentration of the first filling layer is more than 10 times the doping concentration of the second filling layer.
  • a further improvement is that the volume of the first filling layer is greater than or equal to half of the volume of the entire second conductivity type column; or the thickness of the first filling layer covering the bottom surface of the groove is greater than or equal to 1/3 of the depth of the trench.
  • a further improvement is that the first conductivity type epitaxial layer is a uniform doped structure.
  • the first conductive type epitaxial layer is a superposed structure of a first epitaxial sublayer and a second epitaxial sublayer, wherein the first epitaxial sublayer is a uniform doped structure, and the second epitaxial sublayer is uniformly doped
  • the doping concentration of the first epitaxial sublayer and the second epitaxial sublayer are different.
  • the doping concentration of the first conductivity type epitaxial layer is in a direction from the bottom surface to the top surface An incremental gradient distribution or a decreasing gradient distribution.
  • a further improvement is that the first conductivity type is N-type and the second conductivity type is P-type; or, the first conductivity type is P-type, and the second conductivity type is N-type.
  • the method for manufacturing a super junction device includes the following steps:
  • Step 1 providing a first conductive type epitaxial layer, wherein a plurality of trenches are formed on the first conductive type epitaxial layer, and a side surface of the trench is an inclined structure such that a bottom width of the trench is smaller than a top width, thereby facilitating The etching of the trenches and the subsequent filling of the second conductivity type pillars reduces fill defects.
  • Step 2 filling the trench with a second conductivity type pillar, the second conductivity type pillar filled in the trench, and the first conductivity type epitaxial layer between the trenches
  • the first conductivity type columns are alternately arranged to form a super junction structure.
  • the filling process of the second conductive type column includes the following sub-steps:
  • Step 21 Perform a first filling to form a first filling layer, the first filling layer covering a side surface and a bottom surface of the trench.
  • Step 22 Perform a second filling to form a second filling layer, and the second filling layer is superposed on a surface of the first filling layer.
  • the first filling layer and the second filling layer are both doped with a second conductivity type and the doping concentration of the first filling layer is more than twice the doping concentration of the second filling layer.
  • the second conductive type doping total amount of the second conductive type pillar at different depths of the trench is mainly determined by the first filling layer, thereby suppressing a side inclined structure in which a bottom width of the trench is smaller than a top width Effect of the total amount of doping of the second conductivity type at different depths of the trench, thereby increasing the total amount of doping of the second conductivity type at different depths of the trench and the adjacent first conductivity type The balance of the total amount of doping of the first conductivity type of the column.
  • a further improvement is that the first conductive type epitaxial layer is a first conductive type silicon epitaxial layer, the first filled layer is a second conductive type silicon epitaxial layer, and the second filled layer is a second conductive type silicon epitaxial layer a layer, a second conductivity type polysilicon layer or a dielectric film.
  • the doping concentration of the first filling layer is: the total amount of impurities of the second conductive type of the first filling layer is a first value, and the total amount of impurities of the first conductive type column is a second a value, a difference between the first value and the second value is a third value, the third value is less than 10% of the first value, and the third value is less than 10% of the second value .
  • step 21 include:
  • Step 20 forming a third filling layer on a side surface and a bottom surface of the trench, the third filling layer is doped with a second conductivity type, and a doping concentration of the third filling layer is the first filling layer 1/2 or less of the doping concentration; the thickness of the third filling layer on the side of the trench is less than 1/5 of the width of the bottom of the trench, and the third filling layer is isolated from the second
  • the filling layer and the side surface and the bottom surface of the trench are used to reduce diffusion of P-type impurities and N-type impurities between adjacent P-type pillars and N-type pillars to reduce on-resistance.
  • a further improvement is that after the step 22 of the filling process of the second conductive type column of the second step, the method further comprises:
  • Step 23 forming a fourth filling layer on the surface of the second filling layer, the fourth filling layer is doped with a second conductivity type and the doping concentration of the fourth filling layer is the second filling layer More than twice the doping concentration.
  • the use of the inclined trench structure in the super junction structure of the present invention which utilizes the advantages of the inclined trench in the trench etching and the trench filling, can improve the stability and uniformity of the trench etching process, respectively, and improve the trench filling.
  • the present invention can also solve the problem of the breakdown voltage due to the tilt of the trench and can greatly improve the breakdown voltage of the device: the present invention is directed to the narrow width of the top of the inclined trench, in order to avoid the longitudinal direction of the trench
  • the present invention specifically designs a column of the second conductivity type filled in the trench, the pillar of the second conductivity type comprising a first filling layer and a second filling layer, the first filling layer covering a second filling layer is superposed on a surface of the first filling layer at a side surface and a bottom surface of the trench;
  • the second conductivity type pillar is at a different depth of the trench by setting the first filling layer to a high concentration doping
  • the total amount of doping of the two conductivity types is mainly determined by the first filling layer, thereby suppressing the influence of the side inclined structure whose bottom width of the trench is smaller than the top width on the total doping amount of the second conductive type at different depths of the trench
  • FIG. 1 is a structural view of a conventional super junction device
  • FIG. 2 is a schematic view of an ideal condition of a trench of a conventional super junction device
  • FIG. 3 is a schematic view showing the actual condition of a trench of a conventional super junction device
  • Figure 4 is an electric field intensity distribution curve of the device having the grooves shown in Figures 2 and 3 along the AA' position of Figure 1;
  • FIG. 5 is a schematic diagram of a super junction structure when a trench of a conventional super junction device is in an ideal condition
  • FIG. 6 is a schematic diagram of a super junction structure when a trench of a conventional super junction device is in an actual state
  • FIG. 7 is a schematic diagram of a super junction structure of a super junction device according to a first embodiment of the present invention.
  • FIG. 8 is an electric field intensity distribution curve at a position along the AA' of FIG. 1 of the super junction structure of the first embodiment of the present invention shown in FIG. 7 and the conventional super junction structure shown in FIG.
  • FIG. 9 is a structural diagram of a super junction device according to a second embodiment of the present invention.
  • 10A-10D are schematic views showing a super junction structure in each step of a method for fabricating a superjunction device according to a third embodiment of the present invention.
  • FIGS. 11A to 11D are schematic views showing a super junction structure in each step of a method of fabricating a superjunction device according to a fourth embodiment of the present invention.
  • the super-junction device of the first embodiment of the present invention is described by taking an N-type device as an example.
  • the super-junction device of the first embodiment of the present invention is a super-junction power device, and its structure is the same as that of FIG.
  • the first conductivity type is N-type
  • the second conductivity type is P-type
  • the P-type device can be obtained by changing the first conductivity type to the P-type and the second conductivity type to the N-type.
  • the P-type device will not be described in detail.
  • the super junction device of the first embodiment of the present invention is mainly designed for the super junction structure of the device, as shown in FIG. 7 , which is a schematic diagram of a super junction structure of the super junction device according to the first embodiment of the present invention;
  • a plurality of trenches 503 are formed in the layer, and the trenches 503 are filled with P-type pillars, and the P-type pillars filled in the trenches 503 and the N between the trenches 503
  • the N-type pillars 502 composed of the epitaxial layers are alternately arranged to form a super-junction structure.
  • the N-type epitaxial layer in FIG. 7 is the N-type epitaxial layer 7 in FIG.
  • the N-type epitaxial layer 7 is a uniform doped structure, and a semiconductor substrate such as a silicon substrate 9 is formed at the bottom of the N-type epitaxial layer 7.
  • the trench 503 does not pass through the N-type epitaxial layer 7, and finally a buffer layer 501 composed of the N-type epitaxial layer 7 is formed at the bottom of the super-junction structure, buffering Layer 501 is used to buffer the effect of heavily doped semiconductor substrate 9 on the superjunction structure.
  • the side surface of the trench 503 is an inclined structure such that the bottom width of the trench 503 is smaller than the top width, thereby facilitating etching of the trench 503 and filling of the P-type pillar to reduce filling defects.
  • the inclination angle of the side surface of the groove 503 is 88.4 to 89 degrees.
  • the P-type pillar includes a first filling layer 504 and a second filling layer 505, the first filling layer 504 being covered a side surface and a bottom surface of the trench 503, the second filling layer 505 is superposed on a surface of the first filling layer 504; the first filling layer 504 and the second filling layer 505 are both P-type doped And the doping concentration of the first filling layer 504 is more than twice the doping concentration of the second filling layer 505, so that the P-type doping of the P-type pillar at different depths of the trench 503
  • the total amount of impurities is mainly determined by the first filling layer 504, thereby suppressing the influence of the side inclined structure of the bottom width of the trench 503 being smaller than the top width on the total amount of P-type doping at different depths of the trench 503. Thereby, the balance of the total amount of P-type doping at different depths of the trench 503 and the total amount of N-type doping of the adjacent N-type pillars
  • the doping concentration of the first filling layer 5 is very high, and the doping concentration of the second filling layer 505 is very low, and the doping concentration of the second filling layer 505 can be as close as possible to the intrinsic Doping is the intrinsic doping.
  • the doping concentration of the first filling layer 504 is 10 times or more of the doping concentration of the second filling layer 505.
  • the N-type epitaxial layer is an N-type silicon epitaxial layer
  • the first filling layer 504 is a P-type silicon epitaxial layer
  • the second filling layer 505 is a P-type silicon epitaxial layer, a P-type polysilicon layer or a dielectric film.
  • the doping concentration of the first filling layer 504 is satisfied: the total amount of the P-type impurities of the first filling layer 504 is a first value, and the total amount of impurities of the N-type column 502 is a second value, the first The difference between the value and the second value is a third value, the third value being less than 10% of the first value, and the third value being less than 10% of the second value.
  • the doping concentration of the first filling layer 504 is set such that the total amount of P-type doping at different depths of the trench 503 and the total amount of N-type doping of the adjacent N-type pillars 502 are reached. Very good balance. In other embodiments, the increase or decrease of 10% described above may be made according to the level of the balance of the N-type and P-type impurities.
  • the volume of the first filling layer 504 is greater than or equal to half of the volume of the entire P-type pillar; or the first filling layer 504 covers the bottom surface of the trench 503.
  • the thickness is greater than or equal to 1/3 of the depth of the trench 503.
  • FIG. 1 which includes:
  • the gate 1 is usually composed of polysilicon, that is, the gate 1 is a polysilicon gate, and the thickness is usually between.
  • the gate oxide layer 2 is used to achieve the isolation of the gate 1 and the channel.
  • the thickness of the gate oxide layer 2 determines the withstand voltage of the gate 1, and in order to ensure a certain withstand voltage of the gate 1, the gate oxide layer 2 Thickness is generally greater than In other embodiments, the gate oxide layer 2 can also be replaced with other dielectric layers.
  • the source region 3 is composed of an N-type heavily doped region, that is, an N+ region, and the doping amount of the source region 3, that is, the implantation dose of the ion implantation doping is usually 1 e15/cm 2 or more.
  • the doping amount of the P-type channel region 5 and the P-type channel region 5 is usually between 3e13/cm 2 and 1e14/cm 2 , and the doping of the P-type channel region 5 determines the threshold voltage of the device, doping. The higher the dose, the higher the threshold voltage of the device.
  • the surface of the P-type channel region 5 covered by the gate 1 is used to form a channel.
  • the hole collecting region 4 is composed of a P-type heavily doped region formed on the surface of the P-type channel region 5, that is, a P+ region.
  • the N-type epitaxial layer 7 has a doped body concentration of usually between 1e15/cm 3 and 5e16/cm 3 , and the N-type epitaxial layer 7 serves as a drift region of the device, and the thickness of the N-type epitaxial layer 7 determines the device's impact. Wear voltage.
  • the P-type pillar 6 in FIG. 1 corresponds to the P-type pillar formed by superposition of the first filling layer 504 and the second filling layer 505 in FIG.
  • the N-type pillar 502 in FIG. 7 corresponds to the N-type pillar composed of the N-type epitaxial layer 7 between the P-type pillars 6 in FIG.
  • the N-type epitaxial layer 7 is formed on the semiconductor substrate 9.
  • the semiconductor substrate 9 is N-doped with a bulk concentration of 1e19/cm 3 or more, and its high doping concentration is to reduce the resistance of the semiconductor substrate 9.
  • the super junction power device is a MOSFET device
  • a drain region is formed of an N-type highly doped semiconductor substrate 9, and a drain composed of a back metal layer is formed on the back surface of the semiconductor substrate 9.
  • a P-type pillar is formed in the trench 503 by using two P-type fillings.
  • the prior art only discloses the use of the first lightening to reduce the P and N types between the N-type column and the P-type column.
  • the lateral expansion between the impurities reduces the specific on-resistance.
  • the multiple P-type filling of the P-type pillar in the first embodiment of the present invention is designed according to the technical problem to be solved by the present invention, that is, the angle of the deep trench etching is mainly different, resulting in the bottom of the trench 503.
  • the P is small, that is, the total amount of P-type impurities is small, and the P at the top is more than the total amount of P-type impurities.
  • This problem is compensated by multiple fillings, and the PN between the N-type column and the P-type column is obtained as much as possible.
  • the type of impurity and the N-type impurity achieve a better balance, so that the breakdown voltage can be better improved to obtain better performance.
  • the doping concentration of the first filling layer 504 formed by the first filling in the two fillings of the first embodiment of the present invention is very rich and the doping concentration of the second filling layer 505 formed by the second filling is very Light, the difference between the two is 2 times or even more.
  • the thickness of the two can be adjusted by adjusting the filling time of the first filling and the second filling, so that the volume of the first filling layer 504 is greater than or equal to half of the volume of the entire P-type column;
  • First The filling layer 504 covers a thickness of a bottom surface of the trench 503 that is greater than or equal to 1/3 of a depth of the trench 503. Specifically, if it is assumed that the time corresponding to the complete filling of the deep groove 503 is 1, the first filling layer 504 can be filled with a high concentration for 30% of the time, and the concentration of the first filling layer 504 can be filled for 70% of the time.
  • a second filling layer 505 it is also possible to fill the first filling layer 504 with a high concentration for 25% of the time, or fill the second filling layer 505 with a low concentration for 75% of the time; or fill in 40% of the time
  • the first fill layer 504 is at a high concentration, or the second fill layer 505 is filled in a low concentration for 60% of the time.
  • This can be chosen according to the designer's requirements. It can be seen that the first filling layer 504 of the first embodiment of the present invention is very rich, the second filling layer 505 is very light, and the bottom P of the trench 503 is small, and the phenomenon of the top P is alleviated. The PN balance of the device is better. Finally, the breakdown voltage can be increased.
  • Table 2 compares the breakdown voltages of the super-junction devices of the P-type columns composed of the single-filled composition and the two-filled layers of the first embodiment of the present invention.
  • the P-type column is an existing single-fill structure. Please refer to FIG. 6.
  • the P-type column 403b in FIG. 6 is a single-fill structure, and the doping concentration is the same from the bottom of the trench to the top P-type pillar 403b. There are many P-type impurities at the top of the groove, and there are few P-type impurities at the bottom, that is, there are many top P and less bottom P.
  • the doping concentration of the P-type pillar is normalized, and the doping concentration of the P-type pillar 403b of the prior structure shown in FIG. 6 is assumed to be 1.0, that is, 1 unit doping concentration;
  • the doping concentration of the first filling layer 504 of the P-type pillar in the first embodiment of the present invention for comparison is set to 1.5
  • the doping concentration of the second filling layer 505 is set to 0.1
  • Layer 505 is close to the intrinsic fill.
  • the side angles of the trenches filled by the P-type pillars of the two are both 88.45 degrees.
  • the breakdown voltage of the device of the first embodiment of the present invention can reach 932.54 V, which is higher than the 782.54 V of the existing device. 150V.
  • the breakdown voltage of the device of the first embodiment of the present invention is only 6 V lower than the breakdown voltage of 938.75 V of the prior art device which is perpendicular to the side of the trench, and the two are substantially close.
  • the groove side of the first embodiment of the present invention is inclined as compared with the prior art device which is perpendicular to the side of the groove, which enables the first embodiment of the present invention to be advantageous for etching and filling the groove, that is, capable of The production capacity of the etching machine equipment is separately increased, the cost is reduced, and the defects of the trench filling are reduced, thereby reducing leakage of the device due to defects and increasing the breakdown voltage of the device.
  • the first embodiment of the present invention can greatly increase the breakdown voltage after using the two-layer filling structure.
  • V Breakdown voltage
  • the device of the first embodiment of the present invention can improve the breakdown voltage of the device. It can also be seen from the image of FIG. 8.
  • the curve 301 in FIG. 8 is a super junction device having the super junction structure of the first embodiment of the present invention shown in FIG.
  • the electric field intensity distribution curve along the AA' position of FIG. 1 the curve 302 is the electric field intensity distribution curve of the super junction device having the conventional super junction structure shown in FIG. 6 along the AA' position of FIG. 1; the curves 301 and 302
  • the corresponding groove has a side inclination of 88.45 degrees.
  • the X axis in Fig. 8 represents the longitudinal depth along the AA' position in Fig. 1, 0 ⁇ m represents the interface of silicon and silicon dioxide, and the unit is micron; the Y axis represents electric field strength in units of V/cm.
  • the dashed box 303 corresponds to the top region of the trench
  • the dashed box 304 corresponds to the bottom region of the trench. It can be seen that the electric field intensity of the first embodiment of the present invention is improved in the top region and the bottom region of the trench, which is due to The first embodiment of the present invention achieves a balance of N-type impurities and P-type impurities at the top and bottom of the trench, and finally makes the curve 301 relatively flat over the depth range of the entire trench; and the curve 302 and FIG. 4
  • the curve 202 is the same, and the top and bottom of the trench are due to the imbalance of the N-type impurity and the P-type impurity. At the top of the trench, P is more than N, and the bottom of the trench is N and P less, by the N-type impurity and The imbalance of the P-type impurities eventually causes the corresponding electric field strength to decrease.
  • FIG. 9 is a structural diagram of a super junction device according to a second embodiment of the present invention; the difference between the super junction device of the second embodiment of the present invention and the super junction device of the first embodiment of the present invention is:
  • the N-type epitaxial layer in the second embodiment is a superposed structure of the first epitaxial sub-layer 7b and the second epitaxial sub-layer 7a, the first epitaxial sub-layer 7b is a uniform doped structure, and the second epitaxial sub-layer 7a is The doping concentration of the first epitaxial sub-layer 7b and the second epitaxial sub-layer 7a is different.
  • the other structures are the same, that is, the P-type column in the second embodiment of the present invention also employs the P-type column structure of the first embodiment of the present invention as shown in FIG.
  • the doping concentration of the N-type epitaxial layer may be in an increasing gradient distribution or a decreasing gradient distribution from the bottom surface to the top surface, that is, the N-type epitaxial layer is a Graded Epi.
  • the P-type pillar of the super junction structure of the three embodiment super-junction device further includes a third filling layer 506, the third filling layer 506 is P-doped and the doping concentration of the third filling layer 506 is 1 ⁇ 2 or less of the doping concentration of the first filling layer 504;
  • the thickness of the third filling layer 506 on the side of the trench 503 is less than 1/5 of the width of the bottom of the trench 503, and the third filling layer 506 is isolated from the second filling layer 505 and the trench.
  • the side surface and the bottom surface of 503 for reducing the diffusion of P-type impurities and N-type impurities between adjacent P-type pillars and N-type pillars 502 to reduce on-resistance. That is, with respect to the case where the first filling layer 504 is directly formed on the side and bottom surfaces of the trench so as to be in direct contact with the N-type epitaxial layer in the structure of the first embodiment of the present invention, doping is employed in the third embodiment of the present invention.
  • the third filling layer 506 having a lower concentration is brought into contact with the N-type epitaxial layer, which can reduce the lateral diffusion of the high-concentration P-type impurity into the N-type pillar 502 to lower the on-resistance.
  • FIG. 11D is a schematic diagram of a super junction structure of a super junction device according to a fourth embodiment of the present invention; the difference between the super junction device of the third embodiment of the present invention and the super junction device of the first embodiment of the present invention is:
  • the P-type pillar of the super junction structure of the three embodiment super-junction device further includes a fourth filling layer 507, the fourth filling layer 507 is P-type doped and the doping concentration of the fourth filling layer 507 is The doping concentration of the second filling layer 505 is more than twice, and the fourth filling layer 507 is superposed on the surface of the second filling layer 505.
  • the fourth filling layer 507 at the top of the trench in the fourth embodiment of the present invention is capable of adjusting the doping of the top of the trench 503 to improve the balance of the P-type and N-type impurities at the top of the trench.
  • Adding the third filling layer 506 in the third embodiment of the present invention and the fourth filling layer 507 in the fourth embodiment of the present invention to the present invention can be obtained by adding the super junction structure of the super junction device of the first embodiment of the present invention.
  • the fifth embodiment super device that is, the P-type pillar of the super junction structure of the super junction device of the fifth embodiment of the present invention is superposed by the third filling layer 506, the first filling layer 504, the second filling layer 505 and the fourth filling layer 507 form.
  • the manufacturing method of the super junction device of the first embodiment of the present invention is for a super junction device having the super junction structure shown in FIG. 7.
  • the schematic diagram of the entire super junction device is as shown in FIG. 1 and includes the following steps:
  • Step 1 providing an N-type epitaxial layer, wherein a plurality of trenches 503 are formed on the N-type epitaxial layer, and a side surface of the trench 503 has an inclined structure such that a bottom width of the trench 503 is smaller than a top width, thereby facilitating The etching of the trench 503 and the filling of the subsequent P-type pillars reduce the filling defects.
  • the N-type epitaxial layer is the N-type epitaxial layer 7 in FIG. 1 , the N-type epitaxial layer 7 is a uniform doped structure, and the bottom of the N-type epitaxial layer 7 is a semiconductor substrate such as a silicon substrate 9;
  • the trench 503 does not pass through the N-type epitaxial layer 7, and finally a buffer layer 501 composed of the N-type epitaxial layer 7 is formed at the bottom of the super-junction structure, and the buffer layer 501 is used. The effect of the heavily doped semiconductor substrate 9 on the super junction structure is buffered.
  • the inclination angle of the side surface of the groove 503 is 88.4 to 89 degrees.
  • Step 2 filling the trench 503 with a P-type pillar, filling the P-type pillar and the P-type pillar in the trench 503 N-type pillars 502 composed of the N-type epitaxial layers between the trenches 503 are alternately arranged to form a super-junction structure;
  • the filling process of the P-type column includes the following sub-steps:
  • Step 21 performing a first filling to form a first filling layer 504, the first filling layer 504 covering the side and bottom surfaces of the trench 503.
  • Step 22 performing a second filling to form a second filling layer 505, the second filling layer 505 being superposed on the surface of the first filling layer 504.
  • the first filling layer 504 and the second filling layer 505 are both P-type doped and the doping concentration of the first filling layer 504 is more than twice the doping concentration of the second filling layer 505.
  • the total amount of P-type doping of the P-type pillars at different depths of the trench 503 is primarily determined by the first fill layer 504, thereby inhibiting the side slope of the trench 503 having a bottom width that is less than the top width.
  • the effect of the structure on the total amount of P-type doping at different depths of the trenches 503, thereby increasing the total amount of P-type doping at different depths of the trenches 503 and the adjacent N-type pillars 502 The balance of the total amount of N-doping.
  • the doping concentration of the first filling layer 5 is very high, and the doping concentration of the second filling layer 505 is very low, and the doping concentration of the second filling layer 505 can be as close as possible to the present The doping and intrinsic doping.
  • the doping concentration of the first filling layer 504 is 10 times or more of the doping concentration of the second filling layer 505.
  • the N-type epitaxial layer is an N-type silicon epitaxial layer
  • the first filling layer 504 is a P-type silicon epitaxial layer
  • the second filling layer 505 is a P-type silicon epitaxial layer, a P-type polysilicon layer or a dielectric film.
  • the doping concentration of the first filling layer 504 is satisfied: the total amount of the P-type impurities of the first filling layer 504 is a first value, and the total amount of impurities of the N-type column 502 is a second value, the first The difference between the value and the second value is a third value, the third value being less than 10% of the first value, and the third value being less than 10% of the second value.
  • the doping concentration of the first filling layer 504 is set such that the total amount of P-type doping at different depths of the trench 503 and the total amount of N-type doping of the adjacent N-type pillars 502 are reached. Very good balance. In other embodiments, the increase or decrease of 10% described above may be made according to the level of the balance of the N-type and P-type impurities.
  • the volume of the first filling layer 504 is greater than or equal to half of the volume of the entire P-type pillar; or the first filling layer 504 covers the bottom surface of the trench 503.
  • the thickness is greater than or equal to 1/3 of the depth of the trench 503.
  • the thicknesses of the first filling layer 504 and the second filling layer 505 can be adjusted by the filling time filled in the step 21 and the step 22, which may be:
  • the time corresponding to the deep groove 503 is 1, so that the first filling layer 504 can be filled with a high concentration for 30% of the time, and the second filling layer 505 can be filled with a low concentration for 70% of the time; % of the time is filled with the first filling layer 504, or 75% of the time is filled with the second filling layer 505; it is also possible to fill the first filling layer with a high concentration for 40% of the time. 504, or 60% of the time to fill the second fill layer 505. This can be chosen according to the designer's requirements.
  • the filling process of the P-type column of the second step further includes: before the step 21:
  • a third filling layer 506 is formed on the side and bottom surfaces of the trench 503, the third filling layer 506 is P-doped and the third filling layer 506 is doped.
  • the concentration is less than 1/2 of the doping concentration of the first filling layer 504; the thickness of the third filling layer 506 on the side of the trench 503 is less than 1/5 of the bottom width of the trench 503,
  • the third filling layer 506 is isolated between the second filling layer 505 and the side surface and the bottom surface of the trench 503 for reducing P-type impurities between adjacent P-type pillars and N-type pillars 502 And N-type impurities diffuse to reduce on-resistance.
  • Figure 10A corresponds to the schematic diagram after the completion of the first step. At this time, the groove 503 has been formed, and the first step of the method of the third embodiment of the present invention is the same as the first step of the method of the first embodiment of the present invention.
  • FIG. 10C corresponds to the structural diagram after the completion of step 21, that is, the first filling layer 504 is formed in step 21.
  • FIG. 10D corresponds to the structural diagram after the completion of step 22, that is, the second filling layer 505 is formed in step 22.
  • each filling layer can be adjusted by adjusting the filling time in steps 20 to 22.
  • the doping concentration of each filling layer is also represented by normalization, so that the doping concentration of the first filling layer 504 having a higher concentration is 1 That is, 1 unit; in addition, the entire filling time is 1 again, in a specific embodiment, the following method can be used to implement the method of the third embodiment of the present invention: the filling time of step 20 is 5%, the concentration is 0.3; the filling of step 21 The time is 25% and the concentration is 1; the filling time of step 22 is 75% and the concentration is 0.05.
  • the parameters of these specific embodiments are only for the purpose of illustrating the present invention more clearly, and other variations are possible, and the settings may be made according to actual needs.
  • FIG. 11A to FIG. 11D a schematic diagram of a super junction structure in each step of the manufacturing method of the super junction device according to the fourth embodiment of the present invention, a difference between the method of the fourth embodiment of the present invention and the method of the first embodiment of the present invention
  • the method further includes:
  • Step 23 as shown in FIG. 11D, forming a fourth filling layer 507 on the surface of the second filling layer 505, the fourth filling layer 507 being P-doped and the doping concentration of the fourth filling layer 507 It is twice or more the doping concentration of the second filling layer 505.
  • Figure 11A corresponds to the schematic diagram after the completion of the first step. At this time, the groove 503 has been formed, and the first step of the method of the fourth embodiment of the present invention is the same as the first step of the method of the first embodiment of the present invention.
  • FIG. 11B corresponds to the structural diagram after the completion of step 21, that is, the first filling layer 504 is formed in step 21.
  • FIG. 11C corresponds to the structural diagram after the completion of step 22, that is, the second filling layer 505 is formed in step 22.
  • each filling layer can be adjusted by adjusting the filling time in steps 21 to 23.
  • the doping concentration of each filling layer is also represented by normalization, so that the doping concentration of the first filling layer 504 having a higher concentration is 1 That is, 1 unit; in addition, the entire filling time is 1 again, in a specific embodiment, the following method can be used to implement the method of the fourth embodiment of the present invention: the filling time of step 21 is 30%, the concentration is 1; The filling time was 50% and the concentration was 0.05; the filling time of step 23 was 20% and the concentration was 1. For step 23, in other embodiments, the filling time of step 23 can be 20% and the concentration is 2.
  • the parameters of these specific embodiments are only for the purpose of illustrating the present invention more clearly, and other variations are possible, and the settings may be made according to actual needs.
  • the method of the fifth embodiment of the method of the third embodiment of the present invention and the step 23 of the method of the fourth embodiment of the present invention can also be used to form the fifth embodiment of the present invention, that is, the fifth aspect of the present invention.
  • Step two of the embodiment method consists of steps 20, 21, 22 and 23.
  • the thickness of each filling layer can be adjusted by adjusting the filling time in steps 21 to 23, and the doping concentration of each filling layer is also represented by normalization, so that the first concentration is higher.
  • the filling layer 504 has a doping concentration of 1 or 1 unit. In addition, the entire filling time is 1 .
  • the filling time of step 20 is 5. %, the concentration is 0.4; the filling time of step 21 is 25%, the concentration is 1; the filling time of step 22 is 50%, the concentration is 0.05; the filling time of step 23 is 20%, and the concentration is 1.
  • the parameters of these specific embodiments are only for the purpose of illustrating the present invention more clearly, and other variations are possible, and the settings may be made according to actual needs.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thyristors (AREA)

Abstract

一种超结器件，超结结构由填充于沟槽中的第二导电类型柱和由沟槽之间的第一导电类型外延层组成的第一导电类型柱交替排列组成超结结构；沟槽(503)的侧面倾斜；第二导电类型柱包括第一和第二填充层，第一填充层(504)覆盖在沟槽(503)的侧面和底部表面，第二填充层(505)叠加在所述第一填充层(504)的表面；两填充层都为第二导电类型掺杂且第一填充层的掺杂浓度高并使第二导电类型柱在沟槽的不同深度处的掺杂总量主要由第一填充层(504)确定，抑制沟槽侧面倾斜结构对沟槽的不同深度处的掺杂总量的影响，提高沟槽的不同深度处的P和N型掺杂总量的平衡。还公开了一种超结器件的制造方法。能提高侧面倾斜沟槽的顶部和底部的P和N型杂质的平衡，提高击穿电压。

Description

超结器件及其制造方法 技术领域
本发明涉及半导体集成电路制造领域，特别是涉及一种超结(super junction)器件；本发明还涉及一种超结器件的制造方法。
背景技术
超结结构就是交替排列的N型柱和P型柱组成结构。如果用超结结构来取代垂直双扩散MOS晶体管(Vertical Double-diffused Metal-Oxide-Semiconductor，VDMOS)器件中的N型漂移区，在导通状态下通过N型柱提供导通通路，导通时P型柱不提供导通通路；在截止状态下由PN立柱共同承受反偏电压，就形成了超结金属-氧化物半导体场效应晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor，MOSFET)。超结MOSFET能在反向击穿电压与传统的VDMOS器件一致的情况下，通过使用低电阻率的外延层，而使器件的导通电阻大幅降低。
如图1所示，是现有超结器件的结构图，该超结器件为超结功率器件，这里是以N型超结器件为例进行介绍，对器件的掺杂类型进行相应的替换可以得到P型超结器件，这里对P型超结器件不做详细介绍。由图1可知，N型超结器件包括：
栅极1，通常是由多晶硅组成即栅极1为多晶硅栅，厚度通常在
Figure PCTCN2016110085-appb-000001
之间。
栅氧化层2，用来是实现栅极1和沟道的隔离，栅氧化层2的厚度决定了栅极1的耐压，通常为了保证一定的栅极1的耐压，栅氧化层2的厚度一般大于
Figure PCTCN2016110085-appb-000002
源区3，由N型重掺杂区即N+区组成，源区3的掺杂剂量即离子注入掺杂的注入剂量通常是在1e15/cm2以上。
P型沟道区5，P型沟道区5的掺杂剂量通常是在3e13/cm2～1e14/cm2之间，P型沟道区5的掺杂决定了器件的阈值电压，掺杂剂量越高，器件的阈值电压越高。被栅极1覆盖的P型沟道区5的表面用于形成沟道。
空穴收集区4，由形成于所述P型沟道区5表面的P型重掺杂区即P+区组成。
N型外延层7，其掺杂的体浓度通常是在1e15/cm3～5e16/cm3之间，N型外延层7作为器件的漂移区，N型外延层7的厚度决定了器件的击穿电压。
P型柱6，P型柱6和由P型柱6之间的N型外延层7组成的N型柱交替排列形成超结结构，超结结构中，各P型柱6和对应的N型柱互补掺杂并实现对N型柱的横向耗尽，通过各P型柱6和相邻的N型柱之间的互相横向耗尽能够轻易实现对整个超结结构中的N型漂移区耗尽，从而能同时实现高的掺杂浓度和高的击穿电压。
P型柱6在工艺上通常有两种实现方式，一种是通过多次外延形成，另外一种是通过挖槽和P型硅填入形成的。
N型外延层7形成于半导体衬底9上，半导体衬底9为N型高掺杂，其体浓度1e19/cm3以上，其高的掺杂浓度是为了减小半导体衬底9的电阻。超结功率器件为MOSFET器件时，由N型高掺杂的半导体衬底9组成漏区，并在半导体衬底9的背面形成由背面金属层组成的漏极。
在P型柱6的两种形成工艺中，次外延工艺具有较高的成本以及工艺时间长。而通过挖槽和P型硅填入的方法，工艺简单且效率高。通过挖槽和P型硅填入的方法来形成P型柱6采用比较多，现介绍如下：
首先、需要采用光刻刻蚀工艺在N型外延层中形成沟槽。
之后、对沟槽进行P型硅填充。
在P型柱6的两种形成工艺中，多次外延工艺具有较高的成本以及工艺时间长。而通过挖槽和P型硅填入的方法，工艺简单且效率高。通过挖槽和P型硅填入的方法来形成P型柱6采用的比较多，现介绍如下：
首先、需要采用光刻刻蚀工艺在N型外延层中形成沟槽。
如图2所示，是现有超结器件的沟槽的理想状况的示意图；可以看出在N型外延层101a形成了多个沟槽102a。其中，N型外延层101a和图1中的N型外延层7相对应，沟槽102a即为图1中的P型柱6的形成区域。可以看出，沟槽102a的侧面为垂直结构，其侧面倾角即标记130a所对应的角度为90度。
如图3所示，是现有超结器件的沟槽的实际状况的示意图；实际工艺中，在N型外延层101b中形成了多个沟槽102b；其中，N型外延层101b和图1中的N型外延层7相对应，沟槽102b即为图1中的P型柱6的形成区域。可以看出，沟槽102b的侧面为倾斜结构，其侧面倾角即标记130b所对应的角度为88.5度。
之后、对沟槽进行P型硅填充形成N型柱和P型柱交替排列的超结结构。
如图5所示，是现有超结器件的沟槽为理想状况时的超结结构示意图；和图2对 比可知，P型柱403a由填充于沟槽102a中的P型硅组成，N型柱402a由沟槽102a之间的N型外延层101a组成，P型柱403a和N型柱402a交替排列组成超结结构。在超结结构底部为缓冲层401a，缓冲层401a也是由N型外延层101a组成，也即缓冲层401a由沟槽102a底部的N型外延层101a组成。在缓冲层401a的底部具有图1中所示的半导体衬底9。
如图6所示，是现有超结器件的沟槽为实际状况时的超结结构示意图；和图3对比可知，P型柱403b由填充于沟槽102b中的P型硅组成，N型柱402b由沟槽102b之间的N型外延层101b组成，P型柱403b和N型柱402b交替排列组成超结结构。在超结结构底部为缓冲层401b，缓冲层401b也是由N型外延层101b组成，也即缓冲层401b由沟槽102b底部的N型外延层101b组成。在缓冲层401b的底部具有图1中所示的半导体衬底9。
之所以在实际工艺中采用图3和图6所示的沟槽侧面倾斜的结构，而不采用图2和图5所示的沟槽侧面垂直的结构，是因为：
1、在沟槽刻蚀过程中，侧面垂直的结构很难稳定的生产，如果沟槽由于工艺的变化变成了底部沟槽宽度大于顶部沟槽的形貌，沟槽填充后就会出现填充缺陷，造成器件漏电增大，而沟槽具有一定程度的倾斜角后能够提高刻蚀工艺的稳定性和一致性，这会改善器件的漏电和击穿电压的一致性。其中沟槽刻蚀的角度对应于刻蚀后的沟槽的侧面倾角。
2、在沟槽填充硅的工艺过程中，有一定的倾斜角度，能够保证硅填入的缺陷尽可能的少，并提高沟槽填充设备的生产能力，降低制造成本，从而可以减少器件的漏电。
由上可知，正是因为沟槽侧面倾斜结构能够在沟槽刻蚀过程中和沟槽填充过程中都带来很好的效果，故在实际情况下，沟槽刻蚀的角度通常是在88.4到89度之间。
虽然侧面倾斜的沟槽能够对刻蚀和填充都有利，但是侧面倾斜的沟槽本身会降低器件的击穿电压，现说明如下：
表一
沟槽刻蚀的角度 击穿电压
88.45度 782.54V
90度 938.75V
如表一所示，表一中给出了沟槽刻蚀角度不同时器件的击穿电压的比较。这里超结器件中除了沟槽刻蚀的角度不同之外，其它结构的工艺条件都相同，如采用相同的衬底结构。本发明中形成超结结构的沟槽的深度都比较深，本领技术人员一般也称之为深槽。在这里假定，器件的深槽的深度为41μm。
从表一可以看到，因为沟槽刻蚀角度的不同，击穿电压相差超过150V。具体原因如下：
如图4所示，是具有图2和图3所示沟槽的器件沿图1的AA’位置处的电场强度分布曲线；其中曲线201对应于具有图2所示的侧面垂直的沟槽的器件沿图1的AA’位置处的电场强度分布曲线，曲线202对应于具有图3所示的侧面倾斜的沟槽的器件沿图1的AA’位置处的电场强度分布曲线，这里曲线202所对应的沟槽的侧面倾角为88.45度。图4中的X轴代表沿着图1中AA’位置的纵向深度，0微米代表硅和二氧化硅的界面，单位是微米；Y轴代表电场强度，单位是V/cm。
可以看到，对应曲线201，在整个沟槽的深度范围内，电场强度基本上是平的。而曲线202中，电场强度在沟槽的顶部和底部都具有较低的值，其中虚线框203所示位置区域为沟槽的顶部区域，虚线框204所示位置区域对应于沟槽的底部区域。比较曲线201和202可知，由于曲线202的电场强度在沟槽的顶部和底部会降低，故曲线202覆盖的面积会较小，也即曲线202所对应的器件的击穿电压会降低。这和表一的数据是一致。
曲线202中之所以会出现电场强度在沟槽的顶部和底部降低的现象，是因为在具有侧面倾斜的沟槽的顶部和底部的N型柱和P型柱的掺杂平衡性变差造成的。具体分析如下：
如图6所示，如果沟槽(Trench)挖的角度是倾斜的即沟槽侧面倾斜时，那么沟槽的底部宽度比较小，也即P型柱403b的底部宽度小、顶部宽度大；而N型柱402b的结构正好相反，为顶部宽度小、底部宽度大，由于P型柱403b填充时采用均匀掺杂结构，这样P型柱403b的宽度会对不同纵向位置处的P型掺杂总剂量产生影响，这样最后会使得P型柱403b的底部的P型杂质总剂量较少，而P型柱403b的顶部的P型杂质总剂量较多；对应N型柱402b则正好相反，N型柱402b的底部的N型杂质总剂量较多，而N型柱402b的顶部的N型杂质总剂量较少；对于两个相邻的P型柱403b和N型柱402b，在沟槽的顶部是P多N少即P型杂质总量多、N型杂质总量少， 在沟槽的底部是P少N多。从而可以看出在沟槽的顶部和底部分别出现了P型杂质和N型杂质不平衡的现象。
而图5所示的沟槽侧面垂直结构中，由于沟槽的侧面是垂直的，故从沟槽的顶部到底部宽度一致，这使得沟槽的宽度对不同纵向位置的掺杂不会产生影响，故在整个沟槽的深度范围类，P型杂质和N型杂质都相平衡。
对于超结器件，之所以能够在相同击穿电压下，提高器件的掺杂浓度，就是因为P杂质和N杂质能够正好被横向完全耗尽，希望在沟槽的每一个位置都能够P和N即P杂质和N杂质的总剂量正好平衡。而如果角度是倾斜的，那么自然会造成顶部N少，P多，而底部是P少，N多。这样P和N的平衡只能够在某一位置，而不能在所有位置实现P-N的平衡。也即在沟槽的顶部和底部无法实现P和N平衡，这正好对应于图4中曲线202在虚线框203和204所对应位置处的电场强度会降低；而垂直沟槽由于没有倾斜沟槽所出现的在沟槽顶部和底部P和N不平衡的问题，故曲线201在整个沟槽深度范围内电场分布是平的。正是因为曲线202中在沟槽顶部和底部的电场强度的降低，使得具有侧面倾斜的沟槽的超结器件的击穿电压会急剧降低，降低超过150V。
发明内容
本发明所要解决的技术问题是提供一种超结器件，能提高侧面倾斜沟槽的顶部和底部的P和N型杂质的平衡，从而提高击穿电压。为此，本发明还提供一种超结器件的制造方法。
为解决上述技术问题，本发明提供的超结器件中，在第一导电类型外延层上形成有多个沟槽，在所述沟槽中填充有第二导电类型柱，填充于所述沟槽中的所述第二导电类型柱和由所述沟槽之间的所述第一导电类型外延层组成的第一导电类型柱交替排列组成超结结构；
所述沟槽的侧面为倾斜结构使所述沟槽的底部宽度小于顶部宽度，从而有利于所述沟槽的刻蚀和所述第二导电类型柱的填充从而减少填充缺陷；
所述第二导电类型柱包括第一填充层和第二填充层，所述第一填充层覆盖在所述沟槽的侧面和底部表面，所述第二填充层叠加在所述第一填充层的表面；所述第一填充层和所述第二填充层都为第二导电类型掺杂且所述第一填充层的掺杂浓度为所述第二填充层的掺杂浓度的2倍以上，使所述第二导电类型柱在所述沟槽的不同深度处的第二导电类型掺杂总量主要由所述第一填充层确定，从而抑制所述沟槽的底部宽度 小于顶部宽度的侧面倾斜结构对所述沟槽的不同深度处的第二导电类型掺杂总量的影响，从而提高所述沟槽的不同深度处的第二导电类型掺杂总量和相邻的所述第一导电类型柱的第一导电类型掺杂总量的平衡。
进一步的改进是，所述第一导电类型外延层为第一导电类型硅外延层，所述第一填充层为第二导电类型硅外延层，所述第二填充层为第二导电类型硅外延层、第二导电类型多晶硅层或介质膜。
进一步的改进是，所述沟槽的侧面的倾角为88.4度～89度。
进一步的改进是，所述第一填充层的掺杂浓度满足：所述第一填充层的第二导电类型杂质总量为第一值，所述第一导电类型柱的杂质总量为第二值，所述第一值和所述第二值的差值为第三值，所述第三值小于所述第一值的10％，所述第三值小于所述第二值的10％。
进一步的改进是，所述第二导电类型柱还包括第三填充层，所述第三填充层为第二导电类型掺杂且所述第三填充层的掺杂浓度为所述第一填充层的掺杂浓度的1/2以下；所述第三填充层位于所述沟槽的侧面的厚度小于所述沟槽的底部宽度的1/5，所述第三填充层隔离于所述第二填充层和所述沟槽的侧面和底部表面之间，用于减少相邻的P型柱和N型柱之间的P型杂质和N型杂质扩散从而降低导通电阻。
进一步的改进是，所述第二导电类型柱还包括第四填充层，所述第四填充层为第二导电类型掺杂且所述第四填充层的掺杂浓度为所述第二填充层的掺杂浓度的2倍以上，所述第四填充层叠加在所述第二填充层的表面。
进一步的改进是，所述第一填充层的掺杂浓度为所述第二填充层的掺杂浓度的10倍以上。
进一步的改进是，所述第一填充层的体积大于等于整个所述第二导电类型柱的体积的一半；或者，所述第一填充层覆盖在所述沟槽的底部表面的厚度大于等于所述沟槽的深度的1/3。
进一步的改进是，所述第一导电类型外延层为均匀掺杂结构。
或者，所述第一导电类型外延层为第一外延子层和第二外延子层的叠加结构，所述第一外延子层为均匀掺杂结构，所述第二外延子层为均匀掺杂结构，所述第一外延子层和所述第二外延子层的掺杂浓度不同。
或者，所述第一导电类型外延层的掺杂浓度在从底部表面到顶部表面的方向上呈 递增的梯度分布或递减的梯度分布。
进一步的改进是，第一导电类型为N型，第二导电类型为P型；或者，第一导电类型为P型，第二导电类型为N型。
为解决上述技术问题，本发明提供的超结器件的制造方法包括如下步骤：
步骤一、提供第一导电类型外延层，在第一导电类型外延层上形成有多个沟槽，所述沟槽的侧面为倾斜结构使所述沟槽的底部宽度小于顶部宽度，从而有利于所述沟槽的刻蚀和后续第二导电类型柱的填充从而减少填充缺陷。
步骤二、在所述沟槽中填充第二导电类型柱，填充于所述沟槽中的所述第二导电类型柱和由所述沟槽之间的所述第一导电类型外延层组成的第一导电类型柱交替排列组成超结结构。
所述第二导电类型柱的填充工艺包括如下分步骤：
步骤21、进行第一次填充形成第一填充层，所述第一填充层覆盖在所述沟槽的侧面和底部表面。
步骤22、进行第二次填充形成第二填充层，所述第二填充层叠加在所述第一填充层的表面。
所述第一填充层和所述第二填充层都为第二导电类型掺杂且所述第一填充层的掺杂浓度为所述第二填充层的掺杂浓度的2倍以上，使所述第二导电类型柱在所述沟槽的不同深度处的第二导电类型掺杂总量主要由所述第一填充层确定，从而抑制所述沟槽的底部宽度小于顶部宽度的侧面倾斜结构对所述沟槽的不同深度处的第二导电类型掺杂总量的影响，从而提高所述沟槽的不同深度处的第二导电类型掺杂总量和相邻的所述第一导电类型柱的第一导电类型掺杂总量的平衡。
进一步的改进是，所述第一导电类型外延层为第一导电类型硅外延层，所述第一填充层为第二导电类型硅外延层，所述第二填充层为第二导电类型硅外延层、第二导电类型多晶硅层或介质膜。
进一步的改进是，所述第一填充层的掺杂浓度满足：所述第一填充层的第二导电类型杂质总量为第一值，所述第一导电类型柱的杂质总量为第二值，所述第一值和所述第二值的差值为第三值，所述第三值小于所述第一值的10％，所述第三值小于所述第二值的10％。
进一步的改进是，步骤二的所述第二导电类型柱的填充工艺中在步骤21之前还 包括：
步骤20、在所述沟槽的侧面和底部表面形成第三填充层，所述第三填充层为第二导电类型掺杂且所述第三填充层的掺杂浓度为所述第一填充层的掺杂浓度的1/2以下；所述第三填充层位于所述沟槽的侧面的厚度小于所述沟槽的底部宽度的1/5，所述第三填充层隔离于所述第二填充层和所述沟槽的侧面和底部表面之间，用于减少相邻的P型柱和N型柱之间的P型杂质和N型杂质扩散从而降低导通电阻。
进一步的改进是，步骤二的所述第二导电类型柱的填充工艺中在步骤22之后还包括：
步骤23、在所述第二填充层的表面形成第四填充层，所述第四填充层为第二导电类型掺杂且所述第四填充层的掺杂浓度为所述第二填充层的掺杂浓度的2倍以上。
有益效果
本发明的超结结构中采用倾斜沟槽结构，利用倾斜沟槽在沟槽刻蚀中和沟槽填充中的优点，能够分别提高沟槽刻蚀工艺的稳定性和一致性，提高沟槽填充设备的生产能力并降低成本以及能减少沟槽填充的缺陷，从而减少由于缺陷所造成的器件的漏电。
另外，本发明还能解决由于沟槽倾斜带来的击穿电压降低的问题并能大大提高器件的击穿电压：本发明针对倾斜沟槽的顶部宽底部窄的特性，为了避免沟槽的纵向宽度不同对PN杂质平衡性的影响，本发明对在沟槽中填充的第二导电类型柱进行了特别设计，第二导电类型柱包括第一填充层和第二填充层，第一填充层覆盖在沟槽的侧面和底部表面，第二填充层叠加在第一填充层的表面；通过将第一填充层设置为高浓度掺杂，使第二导电类型柱在沟槽的不同深度处的第二导电类型掺杂总量主要由第一填充层确定，从而抑制沟槽的底部宽度小于顶部宽度的侧面倾斜结构对沟槽的不同深度处的第二导电类型掺杂总量的影响，从而提高沟槽的不同深度处的第二导电类型掺杂总量和相邻的第一导电类型柱的第一导电类型掺杂总量的平衡，这样能大大提高器件的击穿电压。
附图说明
下面结合附图和具体实施方式对本发明作进一步详细的说明：
图1是现有超结器件的结构图；
图2是现有超结器件的沟槽的理想状况的示意图；
图3是现有超结器件的沟槽的实际状况的示意图；
图4是具有图2和图3所示沟槽的器件沿图1的AA’位置处的电场强度分布曲线；
图5是现有超结器件的沟槽为理想状况时的超结结构示意图；
图6是现有超结器件的沟槽为实际状况时的超结结构示意图；
图7是本发明实施例第一实施例超结器件的超结结构示意图；
图8是具有图7所示的本发明第一实施例的超结结构和图6所示的现有超结结构沿图1的AA’位置处的电场强度分布曲线；
图9是本发明实施例第二实施例超结器件的结构图；
图10A-图10D本发明第三实施例超结器件的制造方法各步骤中的超结结构的示意图；
图11A-图11D本发明第四实施例超结器件的制造方法各步骤中的超结结构的示意图。
具体实施方式
本发明第一实施例超结器件以N型器件为例进行说明，本发明第一实施例超结器件为一超结功率器件，其结构示意图和图1相同。对于N型器件，第一导电类型为N型，第二导电类型为P型，将第一导电类型换为P型以及将第二导电类型换为N型则能得到P型器件，本发明说明书中不对P型器件做详细说明。
本发明第一实施例超结器件主要是对器件的超结结构做了特别设计，如图7所示，是本发明实施例第一实施例超结器件的超结结构示意图；在N型外延层上形成有多个沟槽503，在所述沟槽503中填充有P型柱，填充于所述沟槽503中的所述P型柱和由所述沟槽503之间的所述N型外延层组成的N型柱502交替排列组成超结结构。图7中的N型外延层即为图1中的N型外延层7，所述N型外延层7为均匀掺杂结构，在N型外延层7的底部为半导体衬底如硅衬底9；本发明第一实施例中，所述沟槽503并未穿过所述N型外延层7，最后在超结结构的底部形成有由所述N型外延层7组成的缓冲层501，缓冲层501用于缓冲重掺杂的半导体衬底9对超结结构的影响。
所述沟槽503的侧面为倾斜结构使所述沟槽503的底部宽度小于顶部宽度，从而有利于所述沟槽503的刻蚀和所述P型柱的填充从而减少填充缺陷。较佳为，所述沟槽503的侧面的倾角为88.4度～89度。
所述P型柱包括第一填充层504和第二填充层505，所述第一填充层504覆盖在 所述沟槽503的侧面和底部表面，所述第二填充层505叠加在所述第一填充层504的表面；所述第一填充层504和所述第二填充层505都为P型掺杂且所述第一填充层504的掺杂浓度为所述第二填充层505的掺杂浓度的2倍以上，使所述P型柱在所述沟槽503的不同深度处的P型掺杂总量主要由所述第一填充层504确定，从而抑制所述沟槽503的底部宽度小于顶部宽度的侧面倾斜结构对所述沟槽503的不同深度处的P型掺杂总量的影响，从而提高所述沟槽503的不同深度处的P型掺杂总量和相邻的所述N型柱502的N型掺杂总量的平衡。
本发明第一实施例中，所述第一填充层5掺杂浓度非常高，而第二填充层505的掺杂浓度非常低，第二填充层505的掺杂浓度能够淡到接近于本征掺杂和就是本征掺杂。较佳为，所述第一填充层504的掺杂浓度为所述第二填充层505的掺杂浓度的10倍以上。
所述N型外延层为N型硅外延层，所述第一填充层504为P型硅外延层，所述第二填充层505为P型硅外延层、P型多晶硅层或介质膜。
所述第一填充层504的掺杂浓度满足：所述第一填充层504的P型杂质总量为第一值，所述N型柱502的杂质总量为第二值，所述第一值和所述第二值的差值为第三值，所述第三值小于所述第一值的10％，所述第三值小于所述第二值的10％。上述所述第一填充层504的掺杂浓度的设置能够使得所述沟槽503的不同深度处的P型掺杂总量和相邻的所述N型柱502的N型掺杂总量达到很好的平衡。在其它实施例中，根据N型和P型杂质的平衡的要求的高低可以对上面描述的10％进行增加或减少。
对于厚度设置，较佳为：所述第一填充层504的体积大于等于整个所述P型柱的体积的一半；或者，所述第一填充层504覆盖在所述沟槽503的底部表面的厚度大于等于所述沟槽503的深度的1/3。
上面是对本发明第一实施例中的超结器件的超结结构的描述，对于超结结构的其它结构，请参考图1所示，包括：
栅极1，通常是由多晶硅组成即栅极1为多晶硅栅，厚度通常在
Figure PCTCN2016110085-appb-000003
之间。
栅氧化层2，用来是实现栅极1和沟道的隔离，栅氧化层2的厚度决定了栅极1的耐压，通常为了保证一定的栅极1的耐压，栅氧化层2的厚度一般大于
Figure PCTCN2016110085-appb-000004
在其它实施例中，所述栅氧化层2也能采用其它介质层替换。
源区3，由N型重掺杂区即N+区组成，源区3的掺杂剂量即离子注入掺杂的注入剂量通常是在1e15/cm2以上。
P型沟道区5，P型沟道区5的掺杂剂量通常是在3e13/cm2～1e14/cm2之间，P型沟道区5的掺杂决定了器件的阈值电压，掺杂剂量越高，器件的阈值电压越高。被栅极1覆盖的P型沟道区5的表面用于形成沟道。
空穴收集区4，由形成于所述P型沟道区5表面的P型重掺杂区即P+区组成。
N型外延层7，其掺杂的体浓度通常是在1e15/cm3～5e16/cm3之间，N型外延层7作为器件的漂移区，N型外延层7的厚度决定了器件的击穿电压。
图1中的P型柱6即对应于图7中由第一填充层504和第二填充层505叠加形成的P型柱。图7中的N型柱502对应于图1中由P型柱6之间的N型外延层7组成的N型柱。
N型外延层7形成于半导体衬底9上，半导体衬底9为N型高掺杂，其体浓度1e19/cm3以上，其高的掺杂浓度是为了减小半导体衬底9的电阻。超结功率器件为MOSFET器件时，由N型高掺杂的半导体衬底9组成漏区，并在半导体衬底9的背面形成由背面金属层组成的漏极。
本发明第一实施例器件中，通过采用两次P型填充来在沟槽503中形成P型柱。注意，在现有技术中，也有提到过多次P填充的方法，但是现有技术仅公开了采用第一次做淡，来减小N型柱和P型柱之间的P和N型杂质之间的横扩，从而降低比导通电阻。而本发明第一实施例中的P型柱的多次P型填充是根据本发明所要解决的技术问题出发进行设计的，即主要是针对深槽刻蚀的角度不同，造成了沟槽503底部的P少即P型杂质总量少而顶部的P多即P型杂质总量多，通过多次填充去弥补这个问题，尽可能的做到N型柱和P型柱之间的P-N即P型杂质和N型杂质实现更好的平衡，从而可以更好的提高击穿电压，从而获得更好的性能。
本发明第一实施例的两次填充中的第一次填充形成的所述第一填充层504的掺杂浓度非常浓和第二次填充形成的所述第二填充层505的掺杂浓度非常淡，两者的浓度差在2倍甚至是更多。
两者的厚度能够通过调节第一次填充和第二次填充的填充时间来调节，能使得：所述第一填充层504的体积大于等于整个所述P型柱的体积的一半；或者，所述第一 填充层504覆盖在所述沟槽503的底部表面的厚度大于等于所述沟槽503的深度的1/3。具体可以为：如果假定完整填完整个深槽503所对应的时间为1，则能够让30％的时间填高浓度的所述第一填充层504，70％的时间填低浓度的所述第二填充层505；也可以让25％的时间填高浓度的所述第一填充层504，或者是75％的时间填低浓度的所述第二填充层505；也可以让40％的时间填高浓度的所述第一填充层504，或者是60％的时间填低浓度的所述第二填充层505。这个可以根据设计者的要求自行选择。可以看到，本发明第一实施例的所述第一填充层504非常的浓，所述第二填充层505非常的淡，其沟槽503底部P少，顶部P多的现象得到了缓解，器件的PN平衡更好。最后能够提高击穿电压。
如表二所示，表二对现有采用单次填充组成的P型柱和本发明第一实施例中的两次填充层组成的P型柱的超结器件的击穿电压进行了比较。其中P型柱为现有单次填充结构请参考图6所示，图6中的P型柱403b为单次填充结构，从沟槽底部到顶部P型柱403b的掺杂浓度相同最后使得沟槽顶部的P型杂质多、底部的P型杂质少即顶部P多、底部P少。为了便于比较，对P型柱的掺杂浓度进行归一化处理，假定以图6所示的现有结构的P型柱403b的掺杂浓度为1.0即1个单位掺杂浓度；则表二中用于进行比较的本发明第一实施例中的P型柱的第一填充层504的掺杂浓度设置为1.5，第二填充层505的掺杂浓度设置为0.1，可以看到第二填充层505接近于本征填充。两者的P型柱所填充的沟槽的侧面倾角都采用88.45度，可以看出，本发明第一实施例的器件的击穿电压能达到932.54V，相对于现有器件的782.54V提高了150V。和表一相比可知，本发明第一实施例的器件的击穿电压仅比采用沟槽侧面垂直的现有器件的938.75V的击穿电压低6V，两者基本接近。
由此可知，和沟槽侧面垂直的现有器件相比，本发明第一实施例的沟槽侧面为倾斜，这能使得本发明第一实施例对沟槽的刻蚀和填充有利，即能够分别提高刻蚀机台设备的生产能力并降低成本以及能减少沟槽填充的缺陷，从而减少由于缺陷所造成的器件的漏电和提高器件的击穿电压。
而和沟槽倾斜的现有器件相比，本发明第一实施例采用两层填充结构后，能够大大提高击穿电压。
表二
P型柱结构 击穿电压(V)
现有单次填充结构 782.54
本发明第一实施例的两次填充结构 932.54
本发明第一实施例器件能够提高器件的击穿电压也能从图8形象的看出，图8中曲线301是具有图7所示的本发明第一实施例的超结结构的超结器件沿图1的AA’位置处的电场强度分布曲线，曲线302是具有图6所示的现有超结结构的超结器件沿图1的AA’位置处的电场强度分布曲线；曲线301和302所对应的沟槽的侧面倾角都为88.45度。图8中的X轴代表沿着图1中AA’位置的纵向深度，0微米代表硅和二氧化硅的界面，单位是微米；Y轴代表电场强度，单位是V/cm。
虚线框303对应于沟槽的顶部区域，虚线框304对应于沟槽的底部区域，可知，在沟槽的顶部区域和底部区域，本发明第一实施例的电场强度都得到提高，这是由于本发明第一实施例在沟槽的顶部和底部都实现了N型杂质和P型杂质的平衡，最后使得在整个沟槽的深度范围内曲线301都比较平；而曲线302和图4中的曲线202相同，在沟槽的顶部和底部都是由于N型杂质和P型杂质的不平衡在沟槽的顶部是P多N少、沟槽的底部为N多P少，由N型杂质和P型杂质的不平衡而最后使对应的电场强度降低。
如图9所示，是本发明实施例第二实施例超结器件的结构图；本发明第二实施例超结器件和本发明第一实施例超结器件的区别之处为：本发明第二实施例中的N型外延层为第一外延子层7b和第二外延子层7a的叠加结构，所述第一外延子层7b为均匀掺杂结构，所述第二外延子层7a为均匀掺杂结构，所述第一外延子层7b和所述第二外延子层7a的掺杂浓度不同。其它结构都相同，也即本发明第二实施例中的P型柱也采用如图7所示的本发明第一实施例的P型柱结构。
在其它实施例中，也能为：所述N型外延层的掺杂浓度在从底部表面到顶部表面的方向上呈递增的梯度分布或递减的梯度分布，即N型外延层为Graded Epi。
如图10D所示，是本发明第三实施例超结器件的超结结构示意图；本发明第三实施例超结器件和本发明第一实施例超结器件的区别之处为：本发明第三实施例超结器件的超结结构的P型柱中还包括第三填充层506，所述第三填充层506为P型掺杂且所述第三填充层506的掺杂浓度为所述第一填充层504的掺杂浓度的1/2以下；所述 第三填充层506位于所述沟槽503的侧面的厚度小于所述沟槽503的底部宽度的1/5，所述第三填充层506隔离于所述第二填充层505和所述沟槽503的侧面和底部表面之间，用于减少相邻的P型柱和N型柱502之间的P型杂质和N型杂质扩散从而降低导通电阻。也即，相对于本发明第一实施例的结构中第一填充层504直接形成于沟槽的侧面和底部表面从而和N型外延层直接接触的情形，本发明第三实施例中采用掺杂浓度较低的所述第三填充层506来和N型外延层相接触，这能够减少高浓度的P型杂质横向扩散到N型柱502中从而降低导通电阻。
如图11D所示，是本发明第四实施例超结器件的超结结构示意图；本发明第三实施例超结器件和本发明第一实施例超结器件的区别之处为：本发明第三实施例超结器件的超结结构的P型柱中还包括第四填充层507，所述第四填充层507为P型掺杂且所述第四填充层507的掺杂浓度为所述第二填充层505的掺杂浓度的2倍以上，所述第四填充层507叠加在所述第二填充层505的表面。本发明第四实施例中位于沟槽顶部的所述第四填充层507能够对沟槽503顶部的掺杂进行调节，提高沟槽顶部的P型和N型杂质的平衡性。
在本发明第一实施例超结器件的超结结构的基础上增加本发明第三实施例中的第三填充层506和本发明第四实施例中的第四填充层507能够得到本发明第五实施例超级器件，也即本发明第五实施例超结器件的超结结构的P型柱由第三填充层506，第一填充层504，第二填充层505和第四填充层507叠加形成。
本发明第一实施例超结器件的制造方法是用于具有图7所示的超结结构的超结器件，整个超结器件的示意图如图1所示，包括如下步骤：
步骤一、提供N型外延层，在N型外延层上形成有多个沟槽503，所述沟槽503的侧面为倾斜结构使所述沟槽503的底部宽度小于顶部宽度，从而有利于所述沟槽503的刻蚀和后续P型柱的填充从而减少填充缺陷。
N型外延层即为图1中的N型外延层7，所述N型外延层7为均匀掺杂结构，在N型外延层7的底部为半导体衬底如硅衬底9；本发明第一实施例中，所述沟槽503并未穿过所述N型外延层7，最后在超结结构的底部形成有由所述N型外延层7组成的缓冲层501，缓冲层501用于缓冲重掺杂的半导体衬底9对超结结构的影响。
较佳为，所述沟槽503的侧面的倾角为88.4度～89度。
步骤二、在所述沟槽503中填充P型柱，填充于所述沟槽503中的所述P型柱和 由所述沟槽503之间的所述N型外延层组成的N型柱502交替排列组成超结结构；
所述P型柱的填充工艺包括如下分步骤：
步骤21、进行第一次填充形成第一填充层504，所述第一填充层504覆盖在所述沟槽503的侧面和底部表面。
步骤22、进行第二次填充形成第二填充层505，所述第二填充层505叠加在所述第一填充层504的表面。
所述第一填充层504和所述第二填充层505都为P型掺杂且所述第一填充层504的掺杂浓度为所述第二填充层505的掺杂浓度的2倍以上，使所述P型柱在所述沟槽503的不同深度处的P型掺杂总量主要由所述第一填充层504确定，从而抑制所述沟槽503的底部宽度小于顶部宽度的侧面倾斜结构对所述沟槽503的不同深度处的P型掺杂总量的影响，从而提高所述沟槽503的不同深度处的P型掺杂总量和相邻的所述N型柱502的N型掺杂总量的平衡。
本发明第一实施例方法中，所述第一填充层5掺杂浓度非常高，而第二填充层505的掺杂浓度非常低，第二填充层505的掺杂浓度能够淡到接近于本征掺杂和就是本征掺杂。较佳为，所述第一填充层504的掺杂浓度为所述第二填充层505的掺杂浓度的10倍以上。
所述N型外延层为N型硅外延层，所述第一填充层504为P型硅外延层，所述第二填充层505为P型硅外延层、P型多晶硅层或介质膜。
所述第一填充层504的掺杂浓度满足：所述第一填充层504的P型杂质总量为第一值，所述N型柱502的杂质总量为第二值，所述第一值和所述第二值的差值为第三值，所述第三值小于所述第一值的10％，所述第三值小于所述第二值的10％。上述所述第一填充层504的掺杂浓度的设置能够使得所述沟槽503的不同深度处的P型掺杂总量和相邻的所述N型柱502的N型掺杂总量达到很好的平衡。在其它实施例中，根据N型和P型杂质的平衡的要求的高低可以对上面描述的10％进行增加或减少。
对于厚度设置，较佳为：所述第一填充层504的体积大于等于整个所述P型柱的体积的一半；或者，所述第一填充层504覆盖在所述沟槽503的底部表面的厚度大于等于所述沟槽503的深度的1/3。
本发明第一实施例方法中，能够通过步骤21和步骤22填充的填充时间来调节所述第一填充层504和所述第二填充层505的厚度，具体可以为：如果假定完整填完整 个深槽503所对应的时间为1，则能够让30％的时间填高浓度的所述第一填充层504，70％的时间填低浓度的所述第二填充层505；也可以让25％的时间填高浓度的所述第一填充层504，或者是75％的时间填低浓度的所述第二填充层505；也可以让40％的时间填高浓度的所述第一填充层504，或者是60％的时间填低浓度的所述第二填充层505。这个可以根据设计者的要求自行选择。
如图10A至图10D所示，本发明第三实施例超结器件的制造方法各步骤中的超结结构的示意图，本发明第三实施例方法和本发明第一实施例方法的区别之处为，在本发明第三实施例方法中，步骤二的所述P型柱的填充工艺中在步骤21之前还包括：
步骤20、如图10B所示，在所述沟槽503的侧面和底部表面形成第三填充层506，所述第三填充层506为P型掺杂且所述第三填充层506的掺杂浓度为所述第一填充层504的掺杂浓度的1/2以下；所述第三填充层506位于所述沟槽503的侧面的厚度小于所述沟槽503的底部宽度的1/5，所述第三填充层506隔离于所述第二填充层505和所述沟槽503的侧面和底部表面之间，用于减少相邻的P型柱和N型柱502之间的P型杂质和N型杂质扩散从而降低导通电阻。
图10A对应于步骤一完成后的示意图，这时沟槽503已经形成，本发明第三实施例方法的步骤一和本发明第一实施例方法的步骤一相同。
在步骤20之后，进行步骤21和22，这也都和本发明第一实施例方法的步骤21和22相同。其中图10C对应于步骤21完成后的结构示意图，即步骤21中形成了第一填充层504。图10D对应于步骤22完成后的结构示意图，即步骤22中形成了第二填充层505。
能通过调节步骤20至22中的填充时间来调节各填充层的厚度，各填充层的掺杂浓度也采用归一化表示，令浓度较高的的第一填充层504的掺杂浓度为1即1个单位；另外，再令整个填充时间为1，则在一个具体实施方式能够采用如下参数实现本发明第三实施例方法：步骤20填充时间为5％，浓度为0.3；步骤21的填充时间为25％，浓度为1；步骤22的填充时间为75％，浓度为0.05。这些具体实施方式的参数仅是为了更清楚的说明本发明，还能有其它变化，根据实际需要进行设置即可。
如图11A至图11D所示，本发明第四实施例超结器件的制造方法各步骤中的超结结构的示意图，本发明第四实施例方法和本发明第一实施例方法的区别之处为，在本发明第四实施例方法中，步骤二的所述P型柱的填充工艺中在步骤22之后还包括：
步骤23、如图11D所示，在所述第二填充层505的表面形成第四填充层507，所述第四填充层507为P型掺杂且所述第四填充层507的掺杂浓度为所述第二填充层505的掺杂浓度的2倍以上。
图11A对应于步骤一完成后的示意图，这时沟槽503已经形成，本发明第四实施例方法的步骤一和本发明第一实施例方法的步骤一相同。
步骤21和22都和本发明第一实施例方法的步骤21和22相同。其中图11B对应于步骤21完成后的结构示意图，即步骤21中形成了第一填充层504。图11C对应于步骤22完成后的结构示意图，即步骤22中形成了第二填充层505。
能通过调节步骤21至23中的填充时间来调节各填充层的厚度，各填充层的掺杂浓度也采用归一化表示，令浓度较高的的第一填充层504的掺杂浓度为1即1个单位；另外，再令整个填充时间为1，则在一个具体实施方式能够采用如下参数实现本发明第四实施例方法：步骤21的填充时间为30％，浓度为1；步骤22的填充时间为50％，浓度为0.05；步骤23的填充时间为20％，浓度为1。对于步骤23，在其它实施方式中，也能为：步骤23的填充时间为20％，浓度为2。这些具体实施方式的参数仅是为了更清楚的说明本发明，还能有其它变化，根据实际需要进行设置即可。
也能在本发明第一实施例方法的基础上增加本发明第三实施例方法的步骤20和本发明第四实施例方法的步骤23形成本发明第五实施例方法，也即本发明第五实施例方法的步骤二由步骤20、21、22和23组成。同样，本发明第五实施例中能通过调节步骤21至23中的填充时间来调节各填充层的厚度，各填充层的掺杂浓度也采用归一化表示，令浓度较高的的第一填充层504的掺杂浓度为1即1个单位；另外，再令整个填充时间为1，则在一个具体实施方式能够采用如下参数实现本发明第五实施例方法：步骤20的填充时间为5％，浓度为0.4；步骤21的填充时间为25％，浓度为1；步骤22的填充时间为50％，浓度为0.05；步骤23的填充时间为20％，浓度为1。这些具体实施方式的参数仅是为了更清楚的说明本发明，还能有其它变化，根据实际需要进行设置即可。
以上通过具体实施例对本发明进行了详细的说明，但这些并非构成对本发明的限制。在不脱离本发明原理的情况下，本领域的技术人员还可做出许多变形和改进，这些也应视为本发明的保护范围。

Claims (15)

  1. 一种超结器件，其特征在于：在第一导电类型外延层上形成有多个沟槽，在所述沟槽中填充有第二导电类型柱，填充于所述沟槽中的所述第二导电类型柱和由所述沟槽之间的所述第一导电类型外延层组成的第一导电类型柱交替排列组成超结结构；
    所述沟槽的侧面为倾斜结构使所述沟槽的底部宽度小于顶部宽度，从而有利于所述沟槽的刻蚀和所述第二导电类型柱的填充从而减少填充缺陷；
    所述第二导电类型柱包括第一填充层和第二填充层，所述第一填充层覆盖在所述沟槽的侧面和底部表面，所述第二填充层叠加在所述第一填充层的表面；所述第一填充层和所述第二填充层都为第二导电类型掺杂且所述第一填充层的掺杂浓度为所述第二填充层的掺杂浓度的2倍以上，使所述第二导电类型柱在所述沟槽的不同深度处的第二导电类型掺杂总量主要由所述第一填充层确定，从而抑制所述沟槽的底部宽度小于顶部宽度的侧面倾斜结构对所述沟槽的不同深度处的第二导电类型掺杂总量的影响，从而提高所述沟槽的不同深度处的第二导电类型掺杂总量和相邻的所述第一导电类型柱的第一导电类型掺杂总量的平衡。
  2. 如权利要求1所述超结器件，其特征在于：所述第一导电类型外延层为第一导电类型硅外延层，所述第一填充层为第二导电类型硅外延层，所述第二填充层为第二导电类型硅外延层、第二导电类型多晶硅层或介质膜。
  3. 如权利要求1所述超结器件，其特征在于：所述沟槽的侧面的倾角为88.4度～89度。
  4. 如权利要求1所述超结器件，其特征在于，所述第一填充层的掺杂浓度满足：所述第一填充层的第二导电类型杂质总量为第一值，所述第一导电类型柱的杂质总量为第二值，所述第一值和所述第二值的差值为第三值，所述第三值小于所述第一值的10％，所述第三值小于所述第二值的10％。
  5. 如权利要求1所述超结器件，其特征在于：所述第二导电类型柱还包括第三填充层，所述第三填充层为第二导电类型掺杂且所述第三填充层的掺杂浓度为所述第一填充层的掺杂浓度的1/2以下；所述第三填充层位于所述沟槽的侧面的厚度小于所述沟槽的底部宽度的1/5，所述第三填充层隔离于所述第二填充层和所述沟槽的侧面和底部表面之间，用于减少相邻的P型柱和N型柱之间的P型杂质和N型杂质扩散从而降低导通电阻。
  6. 如权利要求1或5所述超结器件，其特征在于：所述第二导电类型柱还包括第四填充层，所述第四填充层为第二导电类型掺杂且所述第四填充层的掺杂浓度为所述第二填充层的掺杂浓度的2倍以上，所述第四填充层叠加在所述第二填充层的表面。
  7. 如权利要求1或4或5所述超结器件，其特征在于：所述第一填充层的掺杂浓度为所述第二填充层的掺杂浓度的10倍以上。
  8. 如权利要求1或4或5所述超结器件，其特征在于：所述第一填充层的体积大于等于整个所述第二导电类型柱的体积的一半；或者，所述第一填充层覆盖在所述沟槽的底部表面的厚度大于等于所述沟槽的深度的1/3。
  9. 如权利要求1所述超结器件，其特征在于：所述第一导电类型外延层为均匀掺杂结构；
    或者，所述第一导电类型外延层为第一外延子层和第二外延子层的叠加结构，所述第一外延子层为均匀掺杂结构，所述第二外延子层为均匀掺杂结构，所述第一外延子层和所述第二外延子层的掺杂浓度不同；
    或者，所述第一导电类型外延层的掺杂浓度在从底部表面到顶部表面的方向上呈递增的梯度分布或递减的梯度分布。
  10. 如权利要求1所述超结器件，其特征在于：第一导电类型为N型，第二导电类型为P型；或者，第一导电类型为P型，第二导电类型为N型。
  11. 一种超结器件的制造方法，其特征在于，包括如下步骤：
    步骤一、提供第一导电类型外延层，在第一导电类型外延层上形成有多个沟槽，所述沟槽的侧面为倾斜结构使所述沟槽的底部宽度小于顶部宽度，从而有利于所述沟槽的刻蚀和后续第二导电类型柱的填充从而减少填充缺陷；
    步骤二、在所述沟槽中填充第二导电类型柱，填充于所述沟槽中的所述第二导电类型柱和由所述沟槽之间的所述第一导电类型外延层组成的第一导电类型柱交替排列组成超结结构；
    所述第二导电类型柱的填充工艺包括如下分步骤：
    步骤21、进行第一次填充形成第一填充层，所述第一填充层覆盖在所述沟槽的侧面和底部表面；
    步骤22、进行第二次填充形成第二填充层，所述第二填充层叠加在所述第一填充层的表面；
    所述第一填充层和所述第二填充层都为第二导电类型掺杂且所述第一填充层的掺杂浓度为所述第二填充层的掺杂浓度的2倍以上，使所述第二导电类型柱在所述沟槽的不同深度处的第二导电类型掺杂总量主要由所述第一填充层确定，从而抑制所述沟槽的底部宽度小于顶部宽度的侧面倾斜结构对所述沟槽的不同深度处的第二导电类型掺杂总量的影响，从而提高所述沟槽的不同深度处的第二导电类型掺杂总量和相邻的所述第一导电类型柱的第一导电类型掺杂总量的平衡。
  12. 如权利要求11所述超结器件的制造方法，其特征在于：所述第一电类型外延层为第一导电类型硅外延层，所述第一填充层为第二导电类型硅外延层，所述第二填充层为第二导电类型硅外延层、第二导电类型多晶硅层或介质膜。
  13. 如权利要求11所述超结器件的制造方法，其特征在于，所述第一充层的掺杂浓度满足：所述第一填充层的第二导电类型杂质总量为第一值，所述第一导电类型柱的杂质总量为第二值，所述第一值和所述第二值的差值为第三值，所述第三值小于所述第一值的10％，所述第三值小于所述第二值的10％。
  14. 如权利要求11所述超结器件的制造方法，其特征在于，步骤二的所述第二导电类型柱的填充工艺中在步骤21之前还包括：
    步骤20、在所述沟槽的侧面和底部表面形成第三填充层，所述第三填充层为第二导电类型掺杂且所述第三填充层的掺杂浓度为所述第一填充层的掺杂浓度的1/2以下；所述第三填充层位于所述沟槽的侧面的厚度小于所述沟槽的底部宽度的1/5，所述第三填充层隔离于所述第二填充层和所述沟槽的侧面和底部表面之间，用于减少相邻的P型柱和N型柱之间的P型杂质和N型杂质扩散从而降低导通电阻。
  15. 如权利要求11所述超结器件的制造方法，其特征在于，步骤二的所述第二导电类型柱的填充工艺中在步骤22之后还包括：
    步骤23、在所述第二填充层的表面形成第四填充层，所述第四填充层为第二导电类型掺杂且所述第四填充层的掺杂浓度为所述第二填充层的掺杂浓度的2倍以上。
PCT/CN2016/110085 2016-12-15 2016-12-15 超结器件及其制造方法 WO2018107429A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/CN2016/110085 WO2018107429A1 (zh) 2016-12-15 2016-12-15 超结器件及其制造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2016/110085 WO2018107429A1 (zh) 2016-12-15 2016-12-15 超结器件及其制造方法

Publications (1)

Publication Number Publication Date
WO2018107429A1 true WO2018107429A1 (zh) 2018-06-21

Family

ID=62557677

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2016/110085 WO2018107429A1 (zh) 2016-12-15 2016-12-15 超结器件及其制造方法

Country Status (1)

Country Link
WO (1) WO2018107429A1 (zh)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109360854A (zh) * 2018-10-29 2019-02-19 深圳市富裕泰贸易有限公司 一种功率器件终端结构及其制作方法
CN111341830A (zh) * 2018-12-18 2020-06-26 深圳尚阳通科技有限公司 超结结构及其制造方法
CN111403267A (zh) * 2020-04-23 2020-07-10 上海华虹宏力半导体制造有限公司 沟槽外延填充方法
CN112786677A (zh) * 2019-11-01 2021-05-11 南通尚阳通集成电路有限公司 超结器件及其制造方法
CN112864219A (zh) * 2019-11-12 2021-05-28 南通尚阳通集成电路有限公司 超结器件及其制造方法
CN112864246A (zh) * 2019-11-12 2021-05-28 南通尚阳通集成电路有限公司 超结器件及其制造方法
CN115064446A (zh) * 2022-08-18 2022-09-16 北京智芯微电子科技有限公司 超结半导体器件及其制备方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11307627A (ja) * 1997-08-01 1999-11-05 Nippon Steel Corp 半導体装置及びその製造方法
CN101471264A (zh) * 2007-12-28 2009-07-01 万国半导体股份有限公司 具有优化的可制造性的垂直功率器件的高压结构及方法
CN103026461A (zh) * 2010-07-26 2013-04-03 意法半导体股份有限公司 用于填充半导体材料本体中深沟槽的工艺以及根据相同工艺所得的半导体器件
CN104377238A (zh) * 2010-03-05 2015-02-25 万国半导体股份有限公司 带有沟槽-氧化物-纳米管超级结的器件结构及制备方法
CN105428397A (zh) * 2015-11-17 2016-03-23 深圳尚阳通科技有限公司 超结器件及其制造方法
CN105957896A (zh) * 2016-06-24 2016-09-21 上海华虹宏力半导体制造有限公司 超结功率器件及其制造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11307627A (ja) * 1997-08-01 1999-11-05 Nippon Steel Corp 半導体装置及びその製造方法
CN101471264A (zh) * 2007-12-28 2009-07-01 万国半导体股份有限公司 具有优化的可制造性的垂直功率器件的高压结构及方法
CN104377238A (zh) * 2010-03-05 2015-02-25 万国半导体股份有限公司 带有沟槽-氧化物-纳米管超级结的器件结构及制备方法
CN103026461A (zh) * 2010-07-26 2013-04-03 意法半导体股份有限公司 用于填充半导体材料本体中深沟槽的工艺以及根据相同工艺所得的半导体器件
CN105428397A (zh) * 2015-11-17 2016-03-23 深圳尚阳通科技有限公司 超结器件及其制造方法
CN105957896A (zh) * 2016-06-24 2016-09-21 上海华虹宏力半导体制造有限公司 超结功率器件及其制造方法

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109360854A (zh) * 2018-10-29 2019-02-19 深圳市富裕泰贸易有限公司 一种功率器件终端结构及其制作方法
CN111341830A (zh) * 2018-12-18 2020-06-26 深圳尚阳通科技有限公司 超结结构及其制造方法
CN111341830B (zh) * 2018-12-18 2022-08-30 深圳尚阳通科技有限公司 超结结构及其制造方法
CN112786677A (zh) * 2019-11-01 2021-05-11 南通尚阳通集成电路有限公司 超结器件及其制造方法
CN112786677B (zh) * 2019-11-01 2024-04-02 南通尚阳通集成电路有限公司 超结器件及其制造方法
CN112864219A (zh) * 2019-11-12 2021-05-28 南通尚阳通集成电路有限公司 超结器件及其制造方法
CN112864246A (zh) * 2019-11-12 2021-05-28 南通尚阳通集成电路有限公司 超结器件及其制造方法
CN112864246B (zh) * 2019-11-12 2024-04-02 南通尚阳通集成电路有限公司 超结器件及其制造方法
CN111403267A (zh) * 2020-04-23 2020-07-10 上海华虹宏力半导体制造有限公司 沟槽外延填充方法
CN115064446A (zh) * 2022-08-18 2022-09-16 北京智芯微电子科技有限公司 超结半导体器件及其制备方法
CN115064446B (zh) * 2022-08-18 2022-12-16 北京智芯微电子科技有限公司 超结半导体器件及其制备方法
WO2024036792A1 (zh) * 2022-08-18 2024-02-22 北京智芯微电子科技有限公司 超结半导体器件及其制备方法

Similar Documents

Publication Publication Date Title
WO2018107429A1 (zh) 超结器件及其制造方法
US8362550B2 (en) Trench power MOSFET with reduced on-resistance
US8106447B2 (en) Semiconductor device and method of manufacturing the same
US7859052B2 (en) Semiconductor apparatus
KR100675219B1 (ko) 반도체 장치 및 그 제조 방법
CN107482061B (zh) 超结器件及其制造方法
US20150179764A1 (en) Semiconductor device and method for manufacturing same
US20090140327A1 (en) Semiconductor device and manufacturing method of the same
US8704300B1 (en) Semiconductor device and fabricating method thereof
CN112786677B (zh) 超结器件及其制造方法
US9837532B2 (en) Laterally diffused metal oxide semiconductor device and manufacturing method therefor
CN112864246B (zh) 超结器件及其制造方法
JP2008227441A (ja) 半導体装置およびその製造方法
US8354712B2 (en) Semiconductor device and method of manufacturing the same
CN103137661B (zh) 横向双扩散金属氧化物半导体器件及其制造方法
TW201931598A (zh) 新型sgt超級結mosfet結構
US8642427B1 (en) Semiconductor device and method for fabricating the same
US20200335580A1 (en) Methods Of Manufacturing A Deep Trench Super Junction MOSFET
CN112864219B (zh) 超结器件及其制造方法
CN108074963B (zh) 超结器件及其制造方法
US20170222022A1 (en) Semiconductor device with composite trench and implant columns
CN108091683B (zh) 半导体功率器件的超结结构及其制作方法
US20140124858A1 (en) Semiconductor device and fabricating method thereof
CN111341830B (zh) 超结结构及其制造方法
JP2009004493A (ja) 半導体装置及びその製造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16923826

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 16923826

Country of ref document: EP

Kind code of ref document: A1