WO2024036792A1 - 超结半导体器件及其制备方法 - Google Patents

超结半导体器件及其制备方法 Download PDF

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Publication number
WO2024036792A1
WO2024036792A1 PCT/CN2022/132497 CN2022132497W WO2024036792A1 WO 2024036792 A1 WO2024036792 A1 WO 2024036792A1 CN 2022132497 W CN2022132497 W CN 2022132497W WO 2024036792 A1 WO2024036792 A1 WO 2024036792A1
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Prior art keywords
epitaxial
pillar
layer
conductivity type
semiconductor device
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PCT/CN2022/132497
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English (en)
French (fr)
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赵东艳
肖超
陈燕宁
邵瑾
付振
刘芳
田俊
张泉
尹强
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北京智芯微电子科技有限公司
北京芯可鉴科技有限公司
国家电网有限公司
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Publication of WO2024036792A1 publication Critical patent/WO2024036792A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present disclosure relates to the field of power semiconductors, and in particular to a superjunction semiconductor device and a preparation method thereof.
  • Power semiconductor devices are the "heart" of power electronic systems, and their performance determines the efficiency of the entire system.
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor, metal oxide semi-field effect transistor
  • SJ-MOSFET Superjunction MOSFET, super junction metal oxide semi-field effect transistor
  • the laminate structure breaks the so-called “silicon limit” and can significantly reduce the device on-resistance (under the same voltage level, the resistance can be reduced by 5 to 10 times) and improve system efficiency.
  • the multiple epitaxial process has the disadvantages of high epitaxy times and high cost. Therefore, the commonly used manufacturing process is the deep trench single epitaxial filling process.
  • the flow of the deep trench single epitaxial filling process requires one deep trench etching to form a deep trench in the N-type epitaxial layer, and then filling the deep trench with P-type epitaxial material to form alternately arranged P pillars and N pillars; In the process flow, deep trench etching and epitaxial layer filling only need to be done once, and the process is relatively simple.
  • embodiments of the present disclosure provide a superjunction semiconductor device and a preparation method thereof.
  • embodiments of the present disclosure provide a method for manufacturing a superjunction semiconductor device.
  • the preparation method of the superjunction semiconductor device includes:
  • At least one Ai deep trench is etched in a first predetermined area of the wafer through a deep trench etching process, and the Ai deep trench is filled with a first epitaxial layer with a doping concentration of N Ai to form the i-th layer.
  • a conductive type epitaxial pillar ;
  • At least one Di deep trench is etched in the second predetermined area of the wafer through a deep trench etching process.
  • the Di deep trench is filled with a second epitaxial layer with a doping concentration of N Di to form the i-th layer.
  • Two conductivity type epitaxial pillars; the Di deep trench is located between the first conductivity type epitaxial pillars of the i-th layer;
  • the first epitaxial column includes M segments of first epitaxial layers
  • the second epitaxial column includes M segments of second epitaxial layers; i ranges from 1 to M, and M is an integer greater than or equal to 2. As i increases, the depth of the Ai deep trench gradually decreases, and the depth of the Di deep trench also gradually decreases.
  • the method further includes:
  • a thin silicon oxide layer is formed on the surface of the epitaxial pillar of the first conductivity type in the i-th layer by thermal oxidation;
  • a thin silicon oxide layer is formed on the surface of the i-th epitaxial pillar of the second conductivity type by thermal oxidation.
  • At least one Ai deep trench is etched on the wafer through a deep trench etching process, including:
  • At least one Ai deep trench is etched on the wafer through a deep trench etching process.
  • the method further includes:
  • An annealing process is used to bring the first epitaxial pillar and the second epitaxial pillar into contact.
  • the method when the wafer includes a semiconductor substrate and an epitaxial layer, the method includes:
  • An epitaxial layer of the second conductivity type is grown on an upper surface of the semiconductor substrate of the second conductivity type.
  • the wafer is a low-doping high-resistance wafer including ions of the second conductivity type
  • the method further includes:
  • the A1 deep trench is etched to obtain the A1 deep trench, trench implantation of second conductivity type ions is performed, and the A1 deep trench is filled with a first epitaxial layer with a doping concentration of N A1 to form a first layer of the first conductivity type.
  • Epitaxial pillar after etching the D1 deep trench, perform trench implantation of second conductivity type ions, and fill the D1 deep trench with a second epitaxial layer with a doping concentration of N D1 to form the first layer of the second conductivity type
  • the epitaxial pillar; the second conductivity type trench injection in the A1 and D1 deep trenches forms a superjunction field stop layer;
  • the Ai deep trench After etching the Ai deep trench, fill the Ai deep trench with a first epitaxial layer with a doping concentration of N Ai to form an epitaxial pillar of the i-th layer of the first conductivity type; after etching the Di deep trench, fill the Di The second epitaxial layer with a doping concentration of N Di is filled in the deep trench to form an epitaxial column of the i-th layer of the second conductivity type; the value of i is 2 to M, and the M is an integer greater than or equal to 2, forming a super Knot structure;
  • First conductive type ions are implanted simultaneously on the surface of the wafer and the superjunction structure, a first conductive type body region is formed at the first epitaxial pillar, and a field limiting ring is formed in the terminal region.
  • the method further includes:
  • Second conductive type ions are implanted and laser annealed on the back side of the low-doped high-resistance wafer to form a second conductive type substrate.
  • the method further includes:
  • First conductive type ions are implanted and laser annealed on the back side of the low-doped high-resistance wafer to form a first conductive type substrate.
  • the method further includes:
  • a first conductive type body region is formed on the first epitaxial pillar, and a gate oxide layer and a polysilicon gate layer are formed on the surface of the second epitaxial pillar.
  • the method further includes:
  • Trench etching and thermal oxidation are performed on the upper end of the second epitaxial pillar to form a trench-shaped trench gate oxide layer, and then polysilicon is deposited to form a trench polysilicon gate layer.
  • the value range of the gap between adjacent Ai deep trenches and Di deep trenches includes greater than 0 and less than or equal to 0.05um.
  • the electric field intensity at the central axis of any first epitaxial column forms an inflection point at the interface of any two adjacent first epitaxial layers, and the central axis passes through the first epitaxial column transversely.
  • the geometric center of the cross section extends along the longitudinal direction, the transverse direction is a direction parallel to the wafer surface, and the longitudinal direction is a direction perpendicular to the wafer surface.
  • the first epitaxial pillar includes M segments of first epitaxial layers with different doping concentrations
  • the second epitaxial pillar includes M segments of second epitaxial layers with different doping concentrations
  • the M The doping concentration N Ai of the i-th first epitaxial layer in the first epitaxial layer of the segment and the doping concentration N Di of the second epitaxial layer of the i-th segment in the M-segment second epitaxial layer satisfy the preset conditions so that the super The junction structure achieves charge balance.
  • the first epitaxial pillar and the second epitaxial pillar have the same width.
  • the width of the first epitaxial pillar or the second epitaxial pillar ranges from 1 to 6 ⁇ m.
  • each section of the first epitaxial layer and each section of the second epitaxial layer have the same thickness.
  • N Ai is not equal to N Di
  • each section of the first epitaxial layer and each section of the second epitaxial layer ranges from 5 to 10 um.
  • the value of M ranges from 2 to 10.
  • the first conductivity type is N-type
  • the second conductivity type is P-type
  • the first conductivity type is P type
  • the second conductivity type is N type
  • the doping concentration N Ai and the doping concentration N Di range from 1e15 to 1e17cm -3 .
  • embodiments of the present disclosure provide a superjunction semiconductor device.
  • the superjunction semiconductor device includes a superjunction semiconductor device manufactured by applying the method described in the first aspect.
  • the superjunction semiconductor device includes:
  • a superjunction structure formed in the wafer including at least one first epitaxial pillar of a first conductivity type and at least one second epitaxial pillar of a second conductivity type, the first epitaxial pillar and the second epitaxial pillar
  • the pillars are alternately arranged laterally, the first epitaxial pillars include M segments of first epitaxial layers, the second epitaxial pillars include M segments of second epitaxial layers, the first conductivity type is opposite to the second conductivity type, so M is an integer greater than or equal to 2, and the lateral direction is a direction parallel to the wafer surface.
  • embodiments of the present disclosure provide a superjunction semiconductor device.
  • the superjunction semiconductor device includes:
  • a superjunction structure formed in the wafer including at least one first epitaxial pillar of a first conductivity type and at least one second epitaxial pillar of a second conductivity type, the first epitaxial pillar and the second epitaxial pillar
  • the pillars are alternately arranged laterally.
  • the first epitaxial pillars include M segments of first epitaxial layers with different doping concentrations.
  • the second epitaxial pillars include M segments of second epitaxial layers with different doping concentrations.
  • the first conductive type Contrary to the second conductivity type, the M is an integer greater than or equal to 2, and the lateral direction is a direction parallel to the wafer surface;
  • the doping concentration N Ai of the i-th first epitaxial layer in the M-section first epitaxial layer and the doping concentration N Di of the i-th second epitaxial layer in the M-section second epitaxial layer satisfy the preset The conditions are such that the superjunction structure reaches charge balance; when M is an even number, if i is an odd number, then N Ai > N Di , and if i is an even number, then N Ai ⁇ N Di .
  • the first epitaxial pillar and the second epitaxial pillar have the same width.
  • each section of the first epitaxial layer and each section of the second epitaxial layer have the same thickness.
  • N Ai is not equal to N Di
  • the width of the first epitaxial pillar or the second epitaxial pillar ranges from 1 to 6 ⁇ m.
  • each section of the first epitaxial layer and each section of the second epitaxial layer ranges from 5 to 10 um.
  • the value of M ranges from 2 to 10.
  • the wafer includes:
  • An epitaxial layer of a second conductivity type is deposited on the semiconductor substrate, wherein the superjunction structure is formed in the epitaxial layer of the second conductivity type.
  • the wafer includes a low-doped high-resistance wafer of the second conductivity type; the superjunction semiconductor device further includes:
  • a superjunction terminal structure is located at the edge of the superjunction semiconductor device.
  • the superjunction terminal structure includes a field-limited ring.
  • it also includes:
  • a substrate of a second conductivity type is located under the low-doping high-resistance wafer of the second conductivity type.
  • it also includes:
  • a first conductivity type substrate is located under the second conductivity type low doping high resistance wafer.
  • it also includes:
  • a first conductive type body region is formed on the surface of the superjunction structure
  • a polysilicon gate layer is located on the upper surface of the gate oxide layer.
  • it also includes:
  • a first conductive type body region is formed on the surface of the superjunction structure
  • the trench gate oxide layer is in the shape of a groove and is located in the groove at the upper end of the second epitaxial pillar;
  • the trench polysilicon gate layer is located in the groove of the trench gate oxide layer.
  • the first conductivity type is N-type
  • the second conductivity type is P-type
  • the first conductivity type is P type
  • the second conductivity type is N type
  • the doping concentration N Ai and the doping concentration N Di range from 1e15 to 1e17cm -3 .
  • embodiments of the present disclosure provide a superjunction semiconductor device.
  • the superjunction semiconductor device includes:
  • a superjunction structure formed in the wafer including at least one first epitaxial pillar of a first conductivity type and at least one second epitaxial pillar of a second conductivity type, the first epitaxial pillar and the second epitaxial pillar Arranged alternately laterally, the first epitaxial pillars include M segments of first epitaxial layers, the second epitaxial pillars include M segments of second epitaxial layers corresponding to the first epitaxial layers, and the first conductivity type is different from the first epitaxial layer.
  • the second conductivity type is opposite, and the M is an integer greater than or equal to 2;
  • the electric field intensity at the central axis of any first epitaxial column forms an inflection point at the junction of any two adjacent first epitaxial layers, and the central axis passes through the geometric center of the transverse section of the first epitaxial column and extends along the longitudinal direction.
  • the transverse direction is a direction parallel to the wafer surface
  • the longitudinal direction is a direction perpendicular to the wafer surface.
  • the first epitaxial pillar includes M segments of first epitaxial layers with different doping concentrations
  • the second epitaxial pillar includes M segments of second epitaxial layers with different doping concentrations
  • the M The doping concentration N Ai of the i-th first epitaxial layer in the first epitaxial layer of the segment and the doping concentration N Di of the second epitaxial layer of the i-th segment in the M-segment second epitaxial layer satisfy the preset conditions so that the super The junction structure achieves charge balance.
  • the first epitaxial pillar and the second epitaxial pillar have the same width.
  • each section of the first epitaxial layer and each section of the second epitaxial layer have the same thickness.
  • N Ai is not equal to N Di
  • the width of the first epitaxial pillar or the second epitaxial pillar ranges from 1 to 6 ⁇ m.
  • each section of the first epitaxial layer and each section of the second epitaxial layer ranges from 5 to 10 um.
  • the doping concentration N Ai and the doping concentration N Di range from 1e15 to 1e17cm -3 .
  • the first epitaxial pillar and the second epitaxial pillar in the superjunction structure include multiple epitaxial layers, which need to be formed through multiple deep trench etching and filling.
  • the aspect ratio becomes smaller and smaller, which can solve the void problem caused by single epitaxial filling of traditional deep trenches; in addition, compared with the multiple epitaxial processes, when making super-junction structures, multiple epitaxial processes
  • Epitaxial pillars that require 8 to 9 photolithography processes can be made.
  • Epitaxial pillars that are made using multiple trench etchings only require M photolithography processes. Generally, M takes a value of 2 to 3 times, that is, it usually only requires 2 to 3 times.
  • Deep trench etching process is used to make each epitaxial pillar.
  • the lateral diffusion of the epitaxial pillar is smaller, and the cell pitch (cell gap) is two
  • the gap between the epitaxial pillars can be made smaller, and the doping concentration of each epitaxial pillar is also easier to control.
  • first epitaxial pillar and the second epitaxial pillar in the superjunction structure include multiple epitaxial layers, and the electric field intensity at the longitudinal center axis of the first epitaxial pillar forms an inflection point at the interface of any two adjacent first epitaxial layers. , can form a triangular wave electric field distribution. Compared with the parabolic electric field distribution formed by a traditional single epitaxial layer of the same concentration, the breakdown voltage of the superjunction semiconductor device of the present disclosure is less affected by the fluctuation of the epitaxial filling concentration and has a larger process window. .
  • the doping concentration N Ai of the i-th section of the first epitaxial layer among the M-sections of first epitaxial layers and the doping concentration N Di of the i-th section of the second epitaxial layer among the M-sections of second epitaxial layers can be set.
  • Figure 1 shows a flow chart of a single epitaxial filling process of deep trenches in the prior art.
  • FIG. 2 shows a schematic flowchart of a method of manufacturing a superjunction semiconductor device according to an embodiment of the present disclosure.
  • FIG. 3 shows a schematic structural diagram of a superjunction semiconductor device according to an embodiment of the present disclosure.
  • FIG. 4 shows a schematic flowchart of each step in a method for manufacturing a superjunction semiconductor device according to an embodiment of the present disclosure.
  • FIG. 5 shows a schematic flowchart of each step in a method for manufacturing a superjunction semiconductor device according to an embodiment of the present disclosure.
  • FIG. 6 shows a schematic flowchart of some steps in a method for manufacturing a superjunction semiconductor device according to an embodiment of the present disclosure.
  • FIG. 7A shows a schematic diagram of the effective doping concentration distribution and the electric field distribution of the electric field intensity at the central axis of the second epitaxial pillar along the depth direction of the second epitaxial pillar according to an embodiment of the present disclosure.
  • FIG. 7B shows a schematic diagram of the electric field distribution along the depth direction of the N-type epitaxial pillar of the N-type epitaxial pillar longitudinal center axis of the even-numbered segment doped superjunction semiconductor device and the uniformly doped superjunction semiconductor device.
  • FIG. 7C shows the variation curves of the breakdown voltage of the even-numbered segment doped superjunction semiconductor device and the uniformly doped superjunction semiconductor device as a function of the P-type epitaxial pillar concentration.
  • 7D shows a schematic diagram of the electric field distribution along the depth direction of the N-type epitaxial pillar of the N-type epitaxial pillar longitudinal center axis of the odd-numbered segment doped superjunction semiconductor device and the uniformly doped superjunction semiconductor device.
  • FIG. 7E shows the variation curves of breakdown voltages with the concentration of P-type epitaxial pillars for odd-numbered segment doped superjunction semiconductor devices and uniformly doped superjunction semiconductor devices.
  • FIG. 8 shows a schematic structural diagram of a superjunction semiconductor device according to an embodiment of the present disclosure.
  • FIG. 9 shows a schematic structural diagram of a superjunction semiconductor device according to yet another embodiment of the present disclosure.
  • FIG. 10 shows a schematic structural diagram of a superjunction semiconductor device according to yet another embodiment of the present disclosure.
  • FIG. 1 shows a flow chart of a deep trench single epitaxial filling process in the prior art.
  • the deep trench single epitaxial filling process may include the following steps:
  • silicon oxide 12 and photoresist 13 required for deep trench etching are formed on the N epitaxial layer 11;
  • the present disclosure provides a superjunction semiconductor device and a preparation method thereof.
  • FIG. 2 shows a schematic flow chart of a method for preparing a superjunction semiconductor device according to an embodiment of the present disclosure. As shown in Figure 2, the method includes the following steps:
  • step S201 at least one Ai deep trench is etched in a first predetermined area of the wafer through a deep trench etching process, and the Ai deep trench is filled with a first epitaxial layer with a doping concentration of N Ai Forming the i-th layer of epitaxial pillars of the first conductivity type;
  • step S202 at least one Di deep trench is etched in a second predetermined area of the wafer through a deep trench etching process, and the Di deep trench is filled with a second epitaxial layer with a doping concentration of N Di Forming the epitaxial pillars of the i-th layer of the second conductivity type; the Di deep trench is located between the epitaxial pillars of the i-th layer of the first conductivity type;
  • the first epitaxial pillar includes M segments of the first epitaxial layer
  • the second epitaxial pillar includes M segments of the second epitaxial layer.
  • Epitaxial layer; the value of i ranges from 1 to M, and M is an integer greater than or equal to 2. As i increases, the depth of the Ai deep trench gradually decreases, and the depth of the Di deep trench also gradually decreased.
  • FIG. 3 shows a schematic structural diagram of a superjunction semiconductor device according to an embodiment of the present disclosure.
  • a superjunction structure 30 can be formed in the wafer 20 .
  • the superjunction structure 30 includes at least one first epitaxial pillar 31 of the first conductivity type and at least one first epitaxial pillar 31 of the first conductivity type.
  • the first epitaxial pillar 31 and the second epitaxial pillar 32 are alternately arranged laterally. The lateral direction is parallel to the wafer surface, so that a superjunction can be formed. type structure 30.
  • the first epitaxial pillar 31 includes M segments of first epitaxial layers 311
  • the second epitaxial pillar 32 includes M segments of second epitaxial layers 321
  • the The first conductivity type is opposite to the second conductivity type.
  • the first conductivity type is N-type
  • the second conductivity type is P-type
  • the first conductivity type is P-type
  • the second conductivity type is P-type.
  • the second conductivity type is N type.
  • the M is an integer greater than or equal to 2; optionally, the value of M may range from 2 to 10. For example, the value of M in Figure 3 is 4.
  • the doping concentration N Ai of the i-th first epitaxial layer among the M-section first epitaxial layers is the same as the doping concentration N Ai of the i-th second epitaxial layer among the M-section second epitaxial layers.
  • the impurity concentration N Di satisfies the preset conditions so that the superjunction structure reaches charge balance.
  • the doping concentration N Ai of the M-section first epitaxial layers in the first epitaxial pillar 31 may be the same or different, and the doping concentration N Ai of the M-section second epitaxial layer 321 in the second epitaxial pillar 32 may be the same or different.
  • the concentrations N Di may be the same or different.
  • the first epitaxial pillar and the second epitaxial pillar in the superjunction structure include multiple epitaxial layers, which need to be formed through multiple trench etching and filling processes.
  • the aspect ratio is getting smaller and smaller, which can solve the void problem caused by single epitaxial filling of traditional deep trenches, and the cost is lower compared with multiple epitaxial processes.
  • the method further includes:
  • a thin silicon oxide layer is formed on the surface of the epitaxial pillar of the first conductivity type in the i-th layer by thermal oxidation;
  • a thin silicon oxide layer is formed on the surface of the i-th epitaxial pillar of the second conductivity type by thermal oxidation.
  • Step S201 After performing step S201 to obtain the i-th epitaxial pillar of the first conductivity type, a thin silicon oxide layer will be formed on the surface of the i-th epitaxial pillar of the first conductivity type through thermal oxidation, and then the execution can be performed.
  • Step S202 Deep trench etching of at least one Di deep trench.
  • the thin silicon oxide layer can serve as a barrier layer to protect the epitaxial pillar of the first conductivity type of the i-th layer from being etched.
  • a thin silicon oxide layer will be formed on the surface of the i-th epitaxial pillar of the second conductivity type through thermal oxidation, and then the cycle can be completed.
  • Step S201 is performed to continue deep trench etching.
  • the silicon oxide thin layer can serve as a barrier layer to protect the second conductivity type epitaxial pillar of the i-th layer from being etched.
  • At least one Ai deep trench is etched on the wafer through a deep trench etching process, including:
  • At least one Ai deep trench is etched on the wafer through a deep trench etching process.
  • photoresist there are two types of photoresist, including positive photoresist and negative photoresist.
  • the part of the positive photoresist that is exposed to light will dissolve in the photoresist developer, but not the photoresist.
  • the part exposed to light will not dissolve in the photoresist developer; the part exposed to light in the negative photoresist will not dissolve in the photoresist developer, while the part not exposed to light will dissolve in the photoresist developer.
  • FIG. 4 shows an example according to an embodiment of the present disclosure.
  • a schematic flow chart of each step in the preparation method of a superjunction semiconductor device; the preparation method of a superjunction semiconductor device according to an embodiment of the present disclosure includes:
  • Step 401 As shown in Figure 4, step S201 is performed to obtain at least one A1 deep trench by etching on the N-type epitaxial layer 41 through a deep trench etching process, and filling the A1 deep trench with a concentration of Form the first layer of P-type epitaxial pillars, namely P1 pillars 42, for the P-type epitaxial material of N A1 ; form a thin silicon oxide layer 43 on the surface of the P1 pillar by thermal oxidation, and then form the light required for N-type deep trench etching. block 44;
  • Thermal oxidation described here refers to a process in which silicon reacts chemically with gases containing oxidizing substances, such as water vapor and oxygen, at high temperatures to produce a dense silicon dioxide (SiO2) film on the surface of the silicon wafer.
  • oxidizing substances such as water vapor and oxygen
  • the part of the positive photoresist that is exposed to light will dissolve in the photoresist developer, while the part that is not exposed to light will not. It will dissolve in the photoresist developer; the part of the negative photoresist exposed to light will not dissolve in the photoresist developer, while the part not exposed to light will dissolve in the photoresist developer.
  • a whole layer of photoresist can be covered first, and then developed to form a pattern required for N-type deep trench etching, that is, a pattern of photoresist 44 required for N-type deep trench etching.
  • Step 402. As shown in Figure B in Figure 4, step S202 is performed to obtain at least one D1 deep trench, that is, an N-type deep trench, by etching the N-type epitaxial layer through a deep trench etching process.
  • the N-type epitaxial material with a concentration of ND1 is filled in the trench to form the first layer of epitaxial pillars of the second conductivity type, that is, the N1 pillar 45; the D1 deep trench is located between the adjacent P1 pillars 42;
  • etching refers to the actual transfer of the photoresist produced after development to the material under the photoresist to form a pattern defined by photolithography technology, that is, as shown in Figure B in Figure 4, etching away The part not covered by the pattern of the photoresist 44 required for N-type deep trench etching.
  • etching includes dry etching and wet etching.
  • the deep trench etching process in this disclosure is dry etching.
  • the dry etching process usually refers to the use of glow discharge to generate plasma containing charged particles such as ions and electrons as well as highly chemically active neutral atoms, molecules and free radicals to pattern. Etching technology of pattern transfer.
  • the thin silicon oxide layer on the surface of the P1 pillar can act as a barrier to protect the P1 pillar from being etched when etching the D1 deep trench.
  • the depth needs to be consistent with the etching depth of the A1 deep trench, and the N-type epitaxial layer material with a concentration of N D1 is filled to form the N1 pillar.
  • the N-type epitaxial layer material with a concentration of N D1 is filled to form the N1 pillar.
  • Step 403 as shown in Figure C of Figure 4, a silicon oxide thin layer 46 is formed on the surface of the N1 pillar 45 by thermal oxidation, and then a photoresist 47 required for A2 deep trench etching is formed.
  • the opening of the photoresist 47 is larger than the opening of the P1 pillar. In this way, the A2 deep trench etching can be facilitated.
  • Step 404 as shown in D in Figure 4, continue with step S201, and etch the previously filled P1 pillar to a predetermined depth through A2 deep trench etching (the thickness of the P1 pillar after etching remains 5 to 10um). Then, the P-type epitaxial layer with a concentration of N A2 is filled to form a second layer of P-type epitaxial pillars, namely P2 pillars 48; a thin silicon oxide layer 49 is formed on the surface of the P2 pillars by thermal oxidation.
  • Step 405. As shown in Figure E in Figure 4, proceed to step S202. Use the same process as above to etch the N1 pillar to the same remaining thickness as the P1 pillar, and fill it with N-type epitaxial material with a concentration of ND2 to form the second layer.
  • the epitaxial pillar of the second conductivity type is the N2 pillar 410;
  • Step 406 as shown in Figure 4 F, the same process method is used to cycle through steps S201 to S202 to fill and etch the Pi pillars and Ni pillars.
  • the P-type epitaxial pillars thus formed are the first epitaxial pillars 31 and 31.
  • the N-type epitaxial pillar, that is, the second epitaxial pillar 32, is composed of five epitaxial layers with the same thickness but different concentrations.
  • the above preparation method may also include the following steps:
  • An annealing process is used to bring the first epitaxial pillar and the second epitaxial pillar into contact.
  • the annealing process refers to a heat treatment process that is slowly heated to a certain temperature, maintained for a sufficient time, and then cooled at an appropriate speed.
  • the method when the wafer includes a semiconductor substrate and an epitaxial layer, the method includes:
  • An epitaxial layer of the second conductivity type is grown on an upper surface of the semiconductor substrate of the second conductivity type.
  • the epitaxial layer can be grown using an epitaxial layer growth process.
  • the epitaxial layer growth process refers to the principle of nucleation using the two-dimensional structural similarity on the crystal interface. On a single crystal wafer, along its original A process of growing a single crystal layer with a complete crystal lattice in the direction of the crystallographic axis and which can have different impurity concentrations and thicknesses.
  • Epitaxial growth processes include vapor phase epitaxy, liquid phase epitaxy, molecular beam epitaxy, etc. Currently, the vapor phase epitaxy process is commonly used.
  • the second conductivity type is N-type
  • an N-type epitaxial layer can be generated on the upper surface of the N+ substrate.
  • the method may further include the following steps:
  • a second conductivity type trench implant is performed to form a superjunction field stop layer.
  • the specific steps are as follows:
  • the A1 deep trench is etched to obtain the A1 deep trench, trench implantation of second conductivity type ions is performed, and the A1 deep trench is filled with a first epitaxial layer with a doping concentration of N A1 to form a first layer of the first conductivity type.
  • Epitaxial pillar after etching the D1 deep trench, perform trench implantation of second conductivity type ions, and fill the D1 deep trench with a second epitaxial layer with a doping concentration of N D1 to form the first layer of the second conductivity type
  • the epitaxial pillar; the second conductivity type trench injection in the A1 and D1 deep trenches forms a superjunction field stop layer;
  • the Ai deep trench After etching the Ai deep trench, fill the Ai deep trench with a first epitaxial layer with a doping concentration of N Ai to form an epitaxial pillar of the i-th layer of the first conductivity type; after etching the Di deep trench, fill the Di The second epitaxial layer with a doping concentration of N Di is filled in the deep trench to form an epitaxial column of the i-th layer of the second conductivity type; the value of i is 2 to M, and the M is an integer greater than or equal to 2, forming a super Knot structure;
  • First conductivity type ions are implanted on the surface, a first conductivity type body region is formed at the first epitaxial pillar, and a field limiting ring is formed in the terminal region.
  • the implantation refers to ion implantation.
  • the electric field attenuation gradient is proportional to the charge concentration. Therefore, a higher concentration of the superjunction field cutoff layer can cause the electric field to quickly attenuate and cut off at this layer, preventing the depletion region from extending to the back of the device.
  • the superjunction field stop layer can also be called a buffer layer.
  • the wafer is an N-low-doped high-resistance wafer.
  • the first conductivity type is P-type and the second conductivity type is N-type.
  • Figure 5 shows a wafer according to the present disclosure.
  • a schematic flow chart of each step in the preparation method of the superjunction semiconductor device according to the embodiment of the present disclosure; the preparation method of the superjunction semiconductor device according to the embodiment of the present disclosure includes:
  • Step 501 As shown in Figure A in Figure 5, step S201 is performed to obtain at least one A1 deep trench on the N-low-doped high-resistance wafer 51 through a deep trench etching process.
  • N-type trench injection is performed at the bottom of the trench to form a portion of the superjunction field stop layer 52 below the A1 deep trench;
  • the A1 deep trench is filled with a P-type epitaxial material with a concentration of N A1 to form the first layer of P-type
  • the epitaxial pillar is the P1 pillar 53;
  • a silicon oxide thin layer 54 is formed on the surface of the P1 pillar by thermal oxidation, and then the photoresist 55 required for N-type deep trench etching is formed;
  • Step 502. As shown in Figure B in Figure 5, step S202 is performed to obtain at least one D1 deep trench, that is, an N-type deep trench, on the N-low-doped high-resistance wafer 51 through a deep trench etching process.
  • the D1 deep trench is filled with an N-type epitaxial material with a concentration of N D1 to form a first layer of second conductive type epitaxial pillars, namely N1 pillars 57; the D1 deep trench is located between adjacent P1 pillars;
  • the thin silicon oxide layer on the surface of the P1 pillar can be used as a barrier layer to protect the P1 pillar from being etched when etching the D1 deep trench.
  • the depth needs to be consistent with the etching depth of the A1 deep trench, and the N-type epitaxial layer material with a concentration of N D1 is filled to form the N1 pillar. It should be noted here that in order to better protect the P1 pillar from being etched when etching the D1 deep trench, as shown in Figure B in Figure 5, there is a gap between the etched D1 deep trench and the A1 deep trench. There are scheduled intervals.
  • Step 503. As shown in Figure 5C, a thin silicon oxide layer 58 is formed on the surface of the N1 pillar 57 by thermal oxidation, and then the photoresist 59 required for A2 deep trench etching is formed.
  • the opening of the photoresist 59 is larger than P1. the opening of the column;
  • Step 505 continue with step S201, and etch the previously filled P1 pillar to a predetermined depth through A2 deep trench etching (the thickness of the P1 pillar after etching remains 5 to 10um). Then, the P-type epitaxial layer with a concentration of N A2 is filled to form a second layer of P-type epitaxial pillars, namely P2 pillars 510; a silicon oxide thin layer 511 is formed on the surface of the P2 pillar 510 by thermal oxidation.
  • Step 505 proceed to step S202, use the same process as above to etch the N1 pillar to the same remaining thickness as the P1 pillar, and fill it with N-type epitaxial material with a concentration of ND2 to form the second layer.
  • the epitaxial pillar of the second conductivity type is the N2 pillar 512;
  • Step 506 as shown in Figure F in Figure 5, the same process method is used to cycle from step S201 to step S202 to fill and etch the Pi pillar and Ni pillar, so that the P-type epitaxial pillar, that is, the first epitaxial pillar 31 and the N-type epitaxial pillar
  • the epitaxial pillar, that is, the second epitaxial pillar 32 is composed of five epitaxial layers with the same thickness but different concentrations.
  • Figure 6 shows a schematic flow diagram of some steps in a method for preparing a superjunction semiconductor device according to an embodiment of the present disclosure; after performing the above steps to form P-type epitaxial pillars and N-type epitaxial pillars, a surface process and a backside process need to be performed.
  • the main processes are The process is shown in Figure 6, including the following steps:
  • Step 407 As shown in Figure A in Figure 6, a surface process is performed, and P-type implantation is performed on the surface to form a P-body region 61 and a terminal field-limited ring 62; thermal oxidation is performed on the surface of the N-type epitaxial pillar to form a gate oxide layer 63. Then polysilicon is deposited to form a polysilicon gate layer 64, thereby forming a surface MIS (Metal-Insulator-Semiconductor, metal-insulator-semiconductor structure) structure.
  • MIS Metal-Insulator-Semiconductor, metal-insulator-semiconductor structure
  • a backside process also needs to be performed, and the method may further include the following steps:
  • Second conductive type ions are implanted and laser annealed on the back side of the low-doped high-resistance wafer to form a second conductive type substrate.
  • the N- low-doped high-resistance wafer is still used as an example.
  • a backside process is performed, and the low-doping high-resistance wafer is processed through a backside thinning process. Thin the thickness to a preset thickness. For example, the entire wafer thickness is 50 ⁇ 70um.
  • the low-doped high-resistance wafer can be thinned from the back to near the superjunction field cutoff layer; then N-type processing is performed on the back. Implantation and laser annealing are performed to form an N+ substrate 65.
  • the N-type implantation refers to the use of ion implantation to inject N-type material, and the N-type material refers to a material with electrons as the main conductor.
  • the backside thinning process is an important semiconductor manufacturing process.
  • the purpose is to remove excess material on the backside of the wafer to effectively reduce the wafer packaging volume, reduce thermal resistance, improve the heat dissipation performance of the device, and reduce the cost of the packaged chip.
  • the risk of cracking due to uneven heating improves product reliability; at the same time, the mechanical and electrical properties of the thinned chip are also significantly improved.
  • backside thinning processes such as grinding, polishing, dry polishing, electrochemical etching, wet etching, plasma-assisted chemical etching and atmospheric pressure plasma etching.
  • grinding thinning technology is a highly efficient and low-cost thinning technology that has been widely used. This technology achieves wafer thinning by rotating a grinding wheel on the wafer surface to apply pressure, damage, crack, and remove it.
  • the backside process may also include the following steps:
  • First conductive type ions are implanted and laser annealed on the back side of the low-doped high-resistance wafer to form a first conductive type substrate.
  • the superjunction semiconductor device may be an SJ-IGBT (Super Junction Insulated Gate Bipolar Transistor) device.
  • SJ-IGBT Super Junction Insulated Gate Bipolar Transistor
  • the difference between the backside process and the above is that the backside thinning process will The thickness of the low-doping high-resistance wafer is thinned to a preset thickness. For example, the entire wafer thickness is 50-70um.
  • the low-doping high-resistance wafer can be thinned from the back to near the superjunction field stop layer. ; Then perform P-type implantation and laser annealing on the back to form a P+ substrate.
  • the P-type implantation refers to the use of ion implantation to inject P-type material, and the P-type material refers to a material whose main conductivity is holes.
  • the above preparation method may also include the following steps:
  • a first conductive type body region is formed on the first epitaxial pillar, and a gate oxide layer and a polysilicon gate layer are formed on the surface of the second epitaxial pillar.
  • P-type implantation can be performed at the P-type epitaxial pillar to form the P-body region
  • thermal oxidation can be performed on the surface of the N-type epitaxial pillar to form a gate oxide layer
  • polysilicon can be deposited to form a polysilicon gate layer.
  • thermal oxidation is performed on the surface of the N-type epitaxial pillar to form a gate oxide layer 63
  • polysilicon is deposited to form a polysilicon gate layer 64, thus forming a surface MIS structure.
  • the above preparation method may also include the following steps:
  • Trench etching and thermal oxidation are performed on the upper end of the second epitaxial pillar to form a trench-shaped trench gate oxide layer, and then polysilicon is deposited to form a trench polysilicon gate layer.
  • P-type implantation can be performed at the P-type epitaxial pillar to form the P-body region
  • trench etching can be performed on the upper end of the N-type epitaxial pillar surface
  • thermal oxidation can be performed to form a trench gate oxide layer
  • the trench gate oxide layer can be formed.
  • Polysilicon is deposited on the inside of the groove of the trench gate oxide layer to form a trench polysilicon gate layer, thereby forming a trench MIS structure.
  • the value range of the gap between adjacent Ai deep trenches and Di deep trenches is greater than 0 and less than or equal to 0.05um; it is convenient for the two types of deep trenches to be etched without affecting each other. .
  • the electric field intensity at the central axis of any first epitaxial column forms an inflection point at the interface of any two adjacent first epitaxial layers, and the central axis passes through the first epitaxial column transversely.
  • the geometric center of the cross section extends along the longitudinal direction, the transverse direction is a direction parallel to the wafer surface, and the longitudinal direction is a direction perpendicular to the wafer surface. Due to the charge balance within the superjunction structure, the electric field intensity at the central axis of any second epitaxial pillar will also form an inflection point at the interface of any two adjacent second epitaxial layers.
  • the first epitaxial pillar and the second epitaxial pillar in the superjunction semiconductor device provided by the present disclosure include multiple epitaxial layers, which can be formed through multiple trench filling processes.
  • the aspect ratio becomes increasingly larger. is small, which can solve the void problem caused by single epitaxial filling of traditional deep trenches; moreover, during reverse breakdown of the device, the electric field intensity at the longitudinal center axis of the first epitaxial pillar is higher than that of any two adjacent first epitaxial layers.
  • An inflection point is formed at the junction, which can form a triangular wave electric field distribution.
  • the breakdown voltage of the superjunction semiconductor device of the present disclosure is less affected by the fluctuation of the epitaxial filling concentration and has a higher Large craft window.
  • the first epitaxial pillar includes M segments of first epitaxial layers with different doping concentrations
  • the second epitaxial pillar includes M segments of different doping concentrations.
  • the second epitaxial layer ; the doping concentration N Ai of the i-th first epitaxial layer in the M-section first epitaxial layer and the doping concentration N Di of the i-th second epitaxial layer in the M-section second epitaxial layer. Satisfying the preset conditions enables the superjunction structure to achieve charge balance.
  • NA1 > ND1 , NA2 ⁇ ND2 , NA3 ND3 , NA4 > ND4 , NA5 ⁇ ND5 .
  • the first epitaxial pillar and the second epitaxial pillar have the same width.
  • the width of the first epitaxial pillar or the second epitaxial pillar ranges from 1 to 6 ⁇ m.
  • each section of the first epitaxial layer and each section of the second epitaxial layer have the same thickness.
  • each section of the first epitaxial layer and each section of the second epitaxial layer ranges from 5 to 10 um.
  • the first epitaxial pillar and the second epitaxial pillar have the same width, and the thickness of each first epitaxial layer segment and each second epitaxial layer segment is the same.
  • N Ai is not equal to N Di
  • the doping concentration N Ai and the doping concentration N Di range from 1e15 to 1e17cm -3 respectively.
  • the doping concentration is used to express the number of doped impurity atoms in the matrix, and the unit is the number of doping atoms per cubic centimeter.
  • FIG. 7A shows a schematic diagram of the effective doping concentration distribution and the electric field distribution of the electric field intensity at the central axis of the second epitaxial pillar along the depth direction of the second epitaxial pillar according to an embodiment of the present disclosure.
  • the x-coordinate in FIG. 7A is the second epitaxial pillar.
  • the depth of the epitaxial pillar 32 along the depth direction AA' of the second epitaxial pillar 32, the y1 coordinate is the effective doping concentration N Ai -N Di , and the y2 coordinate is the electric field intensity at the longitudinal center axis of the second epitaxial pillar, assuming that the present disclosure
  • N A1 > N D1 , N A2 ⁇ N D2 , N A3 N D3 , N A4 > N D4 , N A5 ⁇ N D5 , then the effective doping concentration N Ai -N Di is as shown in the pulse line 701 in Figure 7A .
  • the second epitaxial pillar can be obtained
  • the change of the electric field intensity at the longitudinal center axis of 32 along the depth direction of the second epitaxial pillar, that is, the AA' direction, is shown as the triangular zigzag line 702 in Figure 7A, and the effective doping of the superjunction semiconductor device in the prior art shown in Figure 1
  • the impurity concentration is a straight line. Due to the influence of the trench angle, the electric field intensity at the central axis of the first epitaxial pillar of the superjunction semiconductor device shown in Figure 1 changes along the AA' direction as shown in the curve 703 in Figure 7A.
  • the longitudinal central axis of the second epitaxial pillar 32 formed of multiple sections of second epitaxial layers with different doping concentrations can form the triangular wave electric field distribution shown in FIG. 7A, which is at the junction of any two adjacent first epitaxial layers, namely a1, Inflection points will be formed at a2, a3 and a4 (it should be noted here that the longitudinal center axis of the first epitaxial pillar 31 formed by multiple first epitaxial layers with different doping concentrations is also formed along the depth direction of the first epitaxial pillar 31 Triangular wave electric field distribution, shape symmetrical to curve 702).
  • the breakdown voltage of the superjunction semiconductor device of the present disclosure is less affected by the fluctuation of the epitaxial filling concentration and has a greater process window.
  • *W
  • FIG. 7B shows a schematic diagram of the electric field distribution along the depth direction of the N-type epitaxial pillar in the N-type epitaxial pillar longitudinal center axis of the even-numbered segment doped superjunction semiconductor device and the uniformly doped superjunction semiconductor device, as shown in FIG.
  • the electric field intensity at the longitudinal center axis of the epitaxial column forms an inflection point at the junction of the two epitaxial layers, which is the b1 position in Figure 7B.
  • the overall electric field distribution is a triangular wave distribution, and the peak value of the triangular wave is located at the junction of the two epitaxial layers, which is in Figure 7B. At position b1.
  • FIG. 7C shows the variation curves of the breakdown voltage of the even-numbered segment doped superjunction semiconductor device and the uniformly doped superjunction semiconductor device as a function of the concentration of the P-type epitaxial pillar.
  • *W
  • the doping concentration of the P-type epitaxial pillar is N A
  • and the doping concentration of the N-type epitaxial pillar is ND , where N A A
  • FIG. 7D shows a schematic diagram of the electric field distribution along the depth direction of the N-type epitaxial pillar of the N-type epitaxial pillar longitudinal center axis of the odd-numbered segment doped superjunction semiconductor device and the uniformly doped superjunction semiconductor device, as shown in FIG.
  • the electric field distribution at the longitudinal center axis of the N-type epitaxial pillar of a uniformly doped superjunction semiconductor device is a parabolic distribution with the opening downward.
  • the electric field intensity at the longitudinal center axis of the epitaxial column forms an inflection point at the junction of the two epitaxial layers, that is, the positions d1 and d2 in Figure 7D.
  • the electric field distribution in the area where each two adjacent epitaxial layers are located presents a triangular wave distribution, that is, at the d1 position.
  • the electric field intensity in the area where the two epitaxial layers at the junction are located is shown in Figure 7D.
  • the electric field intensity variation curve is on the left side of d1 and between d1 and d2.
  • the electric field intensity in the area where the two epitaxial layers are interfacing at the d2 position is as shown in Figure 7D as d2.
  • the electric field intensity change curves on the right and between d1 and d2 are both triangular wave curves.
  • the peak value of the triangular wave is located at the junction of the two epitaxial layers, which is the position of d1 and d2 in Figure 7D.
  • N A2 ND2
  • the electric field intensity distribution at the longitudinal center axis corresponding to the area where the second epitaxial layer is located is relatively gentle, almost a straight line.
  • FIG. 7E shows the variation curves of the breakdown voltage of the odd-numbered segment doped superjunction semiconductor device and the uniformly doped superjunction semiconductor device as a function of the concentration of the P-type epitaxial pillar.
  • the doping concentration of P-type epitaxial pillars can be -3% to 3% based on the original doping concentration.
  • the breakdown voltage meets the requirements; and for the odd-numbered doped superjunction semiconductor device of the present disclosure, the P-type epitaxial column doping concentration can be in the range of -10% to 6% based on the original doping concentration.
  • the breakdown voltage meets the requirements. It can be seen that when the breakdown voltage meets the requirements, the odd-numbered segment doped superjunction semiconductor device of the present disclosure has a larger device process manufacturing window.
  • the present disclosure also provides a superjunction semiconductor device, which can be prepared by the above-mentioned preparation method.
  • the superjunction semiconductor device can include a wafer 20 and a superjunction structure 30 .
  • the superjunction structure 30 is formed in the wafer 20 and includes at least one first epitaxial pillar 31 of the first conductivity type and at least one second epitaxial pillar 32 of the second conductivity type.
  • the first epitaxial pillar 31 and The second epitaxial pillars 32 are alternately arranged in a transverse direction, and the transverse direction is parallel to the wafer surface, so that a superjunction structure 30 can be formed.
  • the first epitaxial pillar 31 includes M segments of first epitaxial layers 311, and the second epitaxial pillar 32 includes M segments of second epitaxial layers 321.
  • the first conductivity type is opposite to the second conductivity type. One is electron conductive, the other is mainly hole conductive.
  • the first conductivity type is N-type (that is, electrons are mainly involved in conduction)
  • the second conductivity type is P-type (that is, holes are mainly involved in conduction); or, the first conductivity type is N-type.
  • the conductivity type is P type
  • the second conductivity type is N type.
  • the M is an integer greater than or equal to 2; optionally, the value of M may range from 2 to 10. For example, the value of M in Figure 3 is 4.
  • the present disclosure also provides a superjunction semiconductor device.
  • the superjunction semiconductor device may include a wafer 20 and a superjunction structure 30 .
  • the wafer 20 refers to a silicon wafer used for making silicon semiconductor circuits.
  • the original material is silicon.
  • High-purity polysilicon is dissolved and mixed with silicon crystal seeds, and then slowly pulled out. , forming a cylindrical single crystal silicon. After the silicon ingot is ground, polished, and sliced, it forms a silicon wafer, that is, a wafer.
  • FIG. 8 shows a schematic structural diagram of a superjunction semiconductor device according to an embodiment of the present disclosure
  • FIG. 9 shows a schematic structural diagram of a superjunction semiconductor device according to yet another embodiment of the present disclosure.
  • the wafer may include a semiconductor substrate 21 and an epitaxial layer 22 as shown in Figure 8.
  • the wafer preparation includes two major steps: substrate preparation and epitaxial process.
  • the substrate is made of semiconductor single crystal material. Wafers and substrates can be directly entered into the wafer manufacturing process to produce semiconductor devices, or they can be processed by epitaxial processes to produce epitaxial wafers.
  • Epitaxy refers to the process of growing a new layer of single crystal on a single crystal substrate that has been carefully processed by cutting, grinding, polishing, etc.
  • the new single crystal can be the same material as the substrate, or it can be a different material (homogeneous). epitaxy or heteroepitaxy). Because the new single crystal layer extends and grows according to the crystal phase of the substrate, it is called an epitaxial layer (the thickness is usually a few microns, taking silicon as an example: silicon epitaxial growth means growing on a silicon single crystal substrate with a certain crystal orientation.
  • epitaxial wafer epitaxial layer + substrate.
  • Device fabrication typically unfolds on epitaxial layers.
  • the wafer may also be a lightly doped high-resistance wafer 23 such as an FZ (Float Zone) wafer, as shown in FIG. 9 .
  • Doping in this disclosure is a process in the semiconductor manufacturing process that introduces impurities into pure intrinsic semiconductors to change their electrical properties. The introduced impurities are related to the type of semiconductor to be manufactured. Common doping techniques for semiconductors There are two main types.
  • the first is high-temperature (thermal) diffusion, which is a technology that introduces doping gas into a high-temperature furnace containing silicon wafers to diffuse impurities into the silicon wafer;
  • the second is ion implantation, which uses ions to The ions to be doped are injected into the material in the form of an ion beam under the acceleration and guidance of the implanter.
  • the ion beam undergoes a series of physical and chemical reactions with the atoms or molecules in the material.
  • the incident ions gradually lose energy and cause surface composition and structure of the material. and properties change, finally remaining in the material.
  • Intrinsic semiconductors are doped to form impurity semiconductors with better conductivity.
  • N-type semiconductors Due to different conductivity types, they can generally be divided into N-type semiconductors and P-type semiconductors. For example, every phosphorus atom doped into an intrinsic semiconductor can One free electron is generated, while the number of holes generated by intrinsic excitation remains unchanged. In this way, in a semiconductor doped with phosphorus, the number of free electrons far exceeds the number of holes, becoming majority carriers (referred to as majority carriers), while holes become minority carriers (referred to as minority carriers). Obviously, electrons are mainly involved in conduction, so this kind of semiconductor is called an electronic semiconductor, or N-type semiconductor for short. This kind of doping is also called N-type doping. Each boron atom incorporated into an intrinsic semiconductor can provide a hole.
  • the number of holes in the semiconductor can be much greater than the number of intrinsically excited electrons, making it a majority carrier. Currents, while electrons become minority carriers. Obviously, holes are mainly involved in conduction, so this kind of semiconductor is called a hole-type semiconductor, or P-type semiconductor for short. This kind of doping is also called P-type doping.
  • the superjunction structure is composed of a P-type doped columnar region and an N-type doped columnar region.
  • the number of charges in the P-type doped region is equal to the number of charges in the N-type doped region, it reaches
  • the superjunction has the best effect, and the balance relationship between its withstand voltage and on-resistance is optimal.
  • a superjunction structure 30 is formed in the wafer 20 and includes at least one first epitaxial pillar 31 of the first conductivity type and at least one second conductivity type.
  • the first epitaxial pillars 31 and the second epitaxial pillars 32 are alternately arranged in a transverse direction, and the transverse direction is parallel to the wafer surface, so that a superjunction structure 30 can be formed.
  • the first epitaxial pillar 31 includes M segments of first epitaxial layers 311
  • the second epitaxial pillar 32 includes M segments of second epitaxial layers 321 , so
  • the first conductivity type is opposite to the second conductivity type, one is mainly electron conductive, and the other is mainly hole conductive.
  • the first conductivity type is N-type (that is, electrons are mainly involved in conduction)
  • the second conductivity type is P-type (that is, holes are mainly involved in conduction); or, the first conductivity type is N-type.
  • the conductivity type is P type
  • the second conductivity type is N type.
  • the M is an integer greater than or equal to 2; optionally, the value of M may range from 2 to 10.
  • the value of M in Figure 3 is 4.
  • the first epitaxial pillar 31 includes M segments of a first epitaxial layer 311 with different doping concentrations
  • the second epitaxial pillar 32 includes M segments of a second epitaxial layer with different doping concentrations.
  • the first epitaxial pillar and the second epitaxial pillar in the superjunction structure provided by the present disclosure include multiple segments of epitaxial layers with different doping concentrations. Since the doping concentration N Ai of the i-th segment of the M-segment first epitaxial layer is It is different from the doping concentration N Di of the i-th second epitaxial layer in the M-section second epitaxial layer and satisfies that when M is an even number, if i is an odd number, then N Ai >N Di , if i is an even number, then N Ai ⁇ N Di ; therefore, during reverse breakdown of the device, compared with traditional epitaxial pillars with the same doping concentration, the breakdown voltage is less affected by the fluctuation of the doping concentration of the epitaxial pillar, that is, when When the breakdown voltage meets the requirements, the doping concentration of the even-numbered epitaxial layer of the present disclosure can have a larger fluctuation range and a larger process window.
  • N Ai N Di
  • N Ai N Di
  • N Ai N Di
  • N Ai >N Di if i is an even number and less than (M+1)/2
  • N Ai ⁇ N Di if i is an odd number and greater than (M+1)/2
  • N Ai ⁇ N Di if i is an even number and greater than (M+1)/2
  • NA1 > ND1 , NA2 ⁇ ND2 , NA3 ND3 , NA4 > ND4 , NA5 ⁇ ND5 .
  • the first epitaxial pillar and the second epitaxial pillar in the superjunction structure provided by the present disclosure include multiple segments of epitaxial layers with different doping concentrations. Since the doping concentration N Ai of the i-th segment of the M-segment first epitaxial layer is It is different from the doping concentration N Di of the i-th second epitaxial layer in the M-section second epitaxial layer and satisfies that when M is an even number, if i is an odd number, then N Ai >N Di , if i is an even number, then N Ai ⁇ N Di ; therefore, during reverse breakdown of the device, compared with traditional epitaxial pillars with the same doping concentration, the breakdown voltage is less affected by the fluctuation of the doping concentration of the epitaxial pillar, that is, when When the breakdown voltages all meet the requirements, the doping concentration of the odd-numbered epitaxial layers of the present disclosure can have a larger fluctuation range and a larger process window.
  • the first epitaxial pillar and the second epitaxial pillar have the same width.
  • the width of the first epitaxial pillar or the second epitaxial pillar ranges from 1 to 6 ⁇ m.
  • each section of the first epitaxial layer and each section of the second epitaxial layer have the same thickness.
  • each section of the first epitaxial layer and each section of the second epitaxial layer ranges from 5 to 10 um.
  • the first epitaxial pillar and the second epitaxial pillar have the same width, and the thickness of each first epitaxial layer segment and each second epitaxial layer segment is the same.
  • N Ai is not equal to N Di
  • the doping concentration N Ai and the doping concentration N Di range from 1e15 to 1e17cm -3 .
  • the doping concentration is used to express the number of doped impurity atoms in the matrix, and the unit is the number of doping atoms per cubic centimeter.
  • the wafer includes: a second conductivity type semiconductor substrate 21; a second conductivity type epitaxial layer 22 deposited on the semiconductor substrate 21, Wherein, the superjunction structure 30 is formed in the epitaxial layer 22 of the second conductivity type.
  • the semiconductor substrate may be an N+ substrate, where N+ represents high-concentration N-type doping, and the epitaxial layer may be an N-epitaxial layer.
  • the material of the substrate can be other wide bandgap semiconductor materials such as GaN (gallium nitride), SiC (silicon carbide), etc.
  • the wafer 20 includes a low-doping high-resistance wafer 23 of the second conductivity type; the superjunction semiconductor device also includes:
  • Superjunction field stop (Field Stop) layer 28 is located under the superjunction structure in the wafer; for example, as shown in Figure 9, the second conductivity type is N-type, then the superjunction field stop The layer may be formed by N-type implantation. Of course, if the second conductivity type is P-type, the superjunction field stop layer can be formed by P-type implantation, and the implantation here refers to ion implantation.
  • the superjunction terminal structure 29 is located at the edge of the superjunction semiconductor device.
  • the super-junction terminal structure 29 may include terminal structures such as field-limited rings, field plates, laterally variable doping (VLD), and junction terminal extensions (JTE).
  • the super-junction terminal structure 29 Can include field limiting rings.
  • a substrate 24 is provided below the second conductivity type low-doped high-resistance wafer.
  • the substrate 24 may be a second conductivity type substrate, or , when the superjunction semiconductor device is an SJ-IGBT device, the substrate 24 may be a first conductive type substrate.
  • the superjunction semiconductor device further includes: a first conductive type body region 25 , a gate oxide layer 26 and a polysilicon gate layer 27 .
  • the first conductive type body region 25 is formed on the surface of the superjunction structure.
  • the first conductive type body region 25 can be formed by implanting first conductive type ions on the surface of the first epitaxial pillar.
  • the gate oxide layer 26 is located on the upper surface of the second epitaxial pillar; the polysilicon gate layer 27 is located on the upper surface of the gate oxide layer 26 , thus forming a surface MIS structure.
  • the preparation process of the superjunction semiconductor device shown in Figure 8 may include:
  • a superjunction structure 30 is formed on the epitaxial layer 22.
  • the superjunction structure 30 includes at least one first epitaxial pillar of the first conductivity type and at least one second epitaxial pillar of the second conductivity type.
  • the first epitaxial pillars and the second epitaxial pillars are alternately arranged laterally, the first epitaxial pillars include M segments of first epitaxial layers with different doping concentrations, and the second epitaxial pillars include M segments of doping concentrations.
  • a different second epitaxial layer, the first conductivity type is opposite to the second conductivity type, and the M is an integer greater than or equal to 2;
  • a first conductive type body region 25 is formed on the first epitaxial pillar, and a gate oxide layer 26 and a polysilicon gate layer 27 are formed on the surface of the second epitaxial pillar.
  • An annealing process is used to bring the first epitaxial pillar and the second epitaxial pillar into contact.
  • the preparation process of the superjunction semiconductor device shown in Figure 9 may include:
  • a superjunction structure 30 is formed on the low-doped high-resistance wafer 23, and a superjunction field stop layer 28 is formed below the superjunction structure.
  • the superjunction structure 30 includes at least one first First epitaxial pillars of a conductive type and at least one second epitaxial pillar of a second conductive type.
  • the first epitaxial pillars and the second epitaxial pillars are alternately arranged laterally.
  • the first epitaxial pillars include M-stage doping concentrations. Different first epitaxial layers, the second epitaxial pillar includes M segments of second epitaxial layers with different doping concentrations, the first conductivity type is opposite to the second conductivity type, and M is an integer greater than or equal to 2. ;
  • a surface process is performed, first conductive type ions are implanted on the surface, a first conductive type body region 25 is formed at the first epitaxial pillar, and a superjunction terminal structure 29, that is, a field limiting ring, is formed in the terminal region;
  • a gate oxide layer 26 and a polysilicon gate layer 27 are formed on the surface of the two epitaxial pillars;
  • An annealing process is used to bring the first epitaxial pillar and the second epitaxial pillar into contact.
  • FIG. 10 shows a schematic structural diagram of a superjunction semiconductor device according to yet another embodiment of the present disclosure.
  • the superjunction semiconductor device further includes: a first conductive type body region 25.
  • the superjunction semiconductor device may be an SGT (Shielded Gate Transistor) device.
  • SGT Shided Gate Transistor
  • the first conductive type body region 25 is formed on the surface of the superjunction structure.
  • the first conductive type body region 25 can be formed by implanting first conductive type ions on the surface of the first epitaxial pillar.
  • the trench gate oxide layer 210 is in a groove shape and is located in the groove at the upper end of the second epitaxial pillar; the trench polysilicon gate layer 211 is located in the groove of the trench gate oxide layer 210, thus forming a trench MIS. structure.
  • the preparation process of the superjunction semiconductor device shown in Figure 10 may include:
  • a superjunction structure 30 is formed on the low-doped high-resistance wafer 23, and a superjunction field stop layer 28 is formed below the superjunction structure;
  • the superjunction structure 30 includes at least one first First epitaxial pillars of a conductive type and at least one second epitaxial pillar of a second conductive type.
  • the first epitaxial pillars and the second epitaxial pillars are alternately arranged laterally.
  • the first epitaxial pillars include M-stage doping concentrations. Different first epitaxial layers, the second epitaxial pillar includes M segments of second epitaxial layers with different doping concentrations, the first conductivity type is opposite to the second conductivity type, and M is an integer greater than or equal to 2. ;
  • a surface process is performed to form a first conductive type body region 25 at the first epitaxial pillar, a superjunction terminal structure 29, that is, a field limiting ring, is formed in the terminal area, and trench etching is performed on the upper end of the second epitaxial pillar.
  • Thermal oxidation forms a trench-shaped trench gate oxide layer 210, and then polysilicon deposition is performed to form a trench polysilicon gate layer 211;
  • An annealing process is used to bring the first epitaxial pillar and the second epitaxial pillar into contact.
  • the present disclosure also provides a superjunction semiconductor device.
  • the superjunction semiconductor device may include a wafer 20 and a superjunction structure 30 .
  • the superjunction structure is composed of a P-type doped columnar region and an N-type doped columnar region.
  • the number of charges in the P-type doped region is equal to the number of charges in the N-type doped region, it reaches
  • the superjunction effect is optimal, and the balance relationship between its withstand voltage and on-resistance is optimal. Therefore, in this embodiment, the charges in the superjunction structure are balanced.
  • a superjunction structure 30 is formed in the wafer 20 and includes at least one first epitaxial pillar 31 of the first conductivity type and at least one second conductivity type.
  • the first epitaxial pillars 31 and the second epitaxial pillars 32 are alternately arranged laterally, so that a superjunction structure 30 can be formed.
  • the first epitaxial pillar 31 includes M segments of first epitaxial layer 311
  • the second epitaxial pillar 32 includes M segments of second epitaxial layer 321
  • the first conductivity type is opposite to the second conductivity type, one is mainly electron conductive, and the other is mainly hole conductive.
  • the first conductivity type is N-type (that is, electrons are mainly involved in conduction)
  • the second conductivity type is P-type (that is, holes are mainly involved in conduction); or, the first conductivity type is N-type.
  • the conductivity type is P type
  • the second conductivity type is N type.
  • the M is an integer greater than or equal to 2; optionally, the value of M may range from 2 to 10.
  • the value of M in Figure 3 is 4.
  • the electric field intensity at the central axis of any first epitaxial pillar forms an inflection point at the interface of any two adjacent first epitaxial layers, and the central axis passes through the first epitaxial layer.
  • the geometric center of the column's transverse section extends along a longitudinal direction, the transverse direction is a direction parallel to the wafer surface, and the longitudinal direction is a direction perpendicular to the wafer surface. Due to the charge balance within the superjunction structure, the electric field intensity at the central axis of any second epitaxial pillar will also form an inflection point at the interface of any two adjacent second epitaxial layers.
  • the electric field intensity at the longitudinal center axis of the second epitaxial column 32 changes along the depth direction of the second epitaxial column, that is, the direction AA′, as shown in the triangular zigzag line 702 in FIG. 7A , and the existing The effective doping concentration of the superjunction semiconductor device shown in Figure 1 is a straight line. Due to the influence of the trench angle, the electric field intensity at the central axis of the first epitaxial pillar of the superjunction semiconductor device shown in Figure 1 is along the AA' direction. The change is shown in the curve 703 in Figure 7A.
  • the longitudinal center axis of the second epitaxial column 32 formed by multiple sections of second epitaxial layers with different doping concentrations can form the triangular wave electric field distribution shown in Figure 7A, which occurs at any two Inflection points will be formed at the junctions of adjacent first epitaxial layers, namely a1, a2, a3 and a4 (it should be noted here that the longitudinal center axis of the first epitaxial pillar 31 formed by multiple first epitaxial layers with different doping concentrations A triangular wave electric field distribution is also formed along the depth direction of the first epitaxial pillar 31, and the shape is symmetrical to the curve 702).
  • the breakdown voltage of the superjunction semiconductor device of the present disclosure is less affected by fluctuations in epitaxial filling concentration, and has a larger process window.
  • the first epitaxial pillar and the second epitaxial pillar in the superjunction semiconductor device provided by the present disclosure include multiple epitaxial layers, which can be formed through multiple trench filling processes.
  • the aspect ratio becomes increasingly larger. is small, which can solve the void problem caused by single epitaxial filling of traditional deep trenches; moreover, during reverse breakdown of the device, the electric field intensity at the longitudinal center axis of the first epitaxial pillar is higher than that of any two adjacent first epitaxial layers.
  • An inflection point is formed at the junction, which can form a triangular wave electric field distribution.
  • the breakdown voltage of the superjunction semiconductor device of the present disclosure is less affected by the fluctuation of the epitaxial filling concentration, and has a higher Large craft window.
  • the first epitaxial pillar includes M segments of first epitaxial layers with different doping concentrations
  • the second epitaxial pillar includes M segments of different doping concentrations.
  • the second epitaxial layer ; the doping concentration N Ai of the i-th first epitaxial layer in the M-section first epitaxial layer and the doping concentration N Di of the i-th second epitaxial layer in the M-section second epitaxial layer. Satisfying the preset conditions enables the superjunction structure to achieve charge balance.
  • N Ai when M is an even number, if i is an odd number, then N Ai > N Di , and if i is an even number, then N Ai ⁇ N Di ; for example, assume that M is 4 , then, N A1 > N D1 , N A2 ⁇ N D2 , N A3 > N D3 , N A4 ⁇ N D4 .
  • the electric field intensity at the longitudinal center axis of the N-type epitaxial pillar of the semiconductor device forms an inflection point at the junction of the two epitaxial layers, which is the b1 position in Figure 7B.
  • the overall electric field distribution is a triangular wave distribution, and the peak value of the triangular wave is located at the junction of the two epitaxial layers. The position is b1 in Figure 7B.
  • the doping concentration of P-type epitaxial pillars can be -3% to 3% based on the original doping concentration.
  • the breakdown voltage meets the requirements; and for the even-numbered superjunction semiconductor device doped in the present disclosure, the P-type epitaxial column doping concentration can be in the range of -8% to 6% based on the original doping concentration.
  • the internal change occurs, the breakdown voltage meets the requirements. It can be seen that when the breakdown voltage meets the requirements, the even-numbered segment doped superjunction semiconductor device of the present disclosure has a larger device process manufacturing window.
  • the electric field distribution at the longitudinal center axis of the N-type epitaxial pillar of a uniformly doped superjunction semiconductor device is a parabolic distribution with the opening downward.
  • the electric field intensity of the semiconductor device at the longitudinal center axis of the N-type epitaxial column forms an inflection point at the junction of the two epitaxial layers, that is, the positions d1 and d2 in Figure 7D.
  • the electric field distribution in the area where each two adjacent epitaxial layers are located presents a triangular wave distribution.
  • the electric field intensity in the area where the two epitaxial layers intersect at the d1 position is as shown in the electric field intensity change curve on the left side of d1 and between d1 and d2 in Figure 7D, and the electric field intensity in the area where the two epitaxial layers intersect at the d2 position.
  • these two parts of the electric field intensity change curves are triangular wave curves.
  • the peak value of the triangular wave is located at the junction of the two epitaxial layers, that is, d1 and d2 in Figure 7D. At the d2 position.
  • N A2 ND2
  • the electric field intensity distribution at the longitudinal center axis corresponding to the area where the second epitaxial layer is located is relatively gentle, almost a straight line.
  • the doping concentration of P-type epitaxial pillars can be -3% to 3% based on the original doping concentration.
  • the breakdown voltage meets the requirements; and for the odd-numbered doped superjunction semiconductor device of the present disclosure, the P-type epitaxial column doping concentration can be in the range of -10% to 6% based on the original doping concentration.
  • the breakdown voltage meets the requirements. It can be seen that when the breakdown voltage meets the requirements, the odd-numbered segment doped superjunction semiconductor device of the present disclosure has a larger device process manufacturing window.
  • the first epitaxial pillar and the second epitaxial pillar have the same width.
  • the width of the first epitaxial pillar or the second epitaxial pillar ranges from 1 to 6 ⁇ m.
  • each section of the first epitaxial layer and each section of the second epitaxial layer have the same thickness.
  • each section of the first epitaxial layer and each section of the second epitaxial layer ranges from 5 to 10 um.
  • the first epitaxial pillar and the second epitaxial pillar have the same width, and the thickness of each first epitaxial layer segment and each second epitaxial layer segment is the same.
  • N Ai is not equal to N Di
  • the doping concentration N Ai and the doping concentration N Di range from 1e15 to 1e17cm -3 .
  • the doping concentration is used to express the number of doped impurity atoms in the matrix, and the unit is the number of doping atoms per cubic centimeter.
  • the wafer includes: a second conductivity type semiconductor substrate 21; a second conductivity type epitaxial layer 22 deposited on the semiconductor substrate 21, Wherein, the superjunction structure 30 is formed in the epitaxial layer 22 of the second conductivity type.
  • the semiconductor substrate may be an N+ substrate, where N+ represents high-concentration N-type doping, and the epitaxial layer may be an N-epitaxial layer.
  • the material of the substrate can be other wide bandgap semiconductor materials such as GaN (gallium nitride), SiC (silicon carbide), etc.
  • the wafer 20 includes a low-doping high-resistance wafer 23 of the second conductivity type; the superjunction semiconductor device also includes:
  • Superjunction field stop (Field Stop) layer 28 is located under the superjunction structure in the wafer; for example, as shown in Figure 9, the second conductivity type is N-type, then the superjunction field stop The layer may be formed by N-type implantation. Of course, if the second conductivity type is P-type, the superjunction field stop layer can be formed by P-type implantation, and the implantation here refers to ion implantation.
  • the superjunction terminal structure 29 is located at the edge of the superjunction semiconductor device.
  • the super-junction terminal structure 29 may include terminal structures such as field-limited rings, field plates, laterally variable doping (VLD), and junction terminal extensions (JTE).
  • the super-junction terminal structure 29 Can include field limiting rings.
  • a substrate 24 is provided below the second conductivity type low-doped high-resistance wafer.
  • the substrate 24 may be a second conductivity type substrate, or , when the superjunction semiconductor device is an SJ-IGBT device, the substrate 24 may be a first conductive type substrate.
  • the superjunction semiconductor device further includes: a first conductive type body region 25 , a gate oxide layer 26 and a polysilicon gate layer 27 .
  • the first conductive type body region 25 is formed on the surface of the superjunction structure.
  • the first conductive type body region 25 can be formed by implanting first conductive type ions on the surface of the first epitaxial pillar.
  • the gate oxide layer 26 is located on the upper surface of the second epitaxial pillar; the polysilicon gate layer 27 is located on the upper surface of the gate oxide layer 26 , thus forming a surface MIS structure.
  • FIG. 10 shows a schematic structural diagram of a superjunction semiconductor device according to an embodiment of the present disclosure.
  • the superjunction semiconductor device further includes: a first conductive type body region 25, Trench gate oxide layer 210 and trench polysilicon gate layer 211.
  • the superjunction semiconductor device may be an SGT device.
  • the first conductive type body region 25 is formed on the surface of the superjunction structure and can be formed on the surface of the first epitaxial pillar.
  • the first conductive type body region 25 is formed by implanting first conductive type ions.
  • the trench gate oxide layer 210 is in a groove shape and is located in the groove at the upper end of the second epitaxial pillar; the trench polysilicon gate layer 211 is located in the groove of the trench gate oxide layer 210, thus forming a trench MIS structure.
  • the preparation method of the superjunction semiconductor device provided by the present disclosure can be formed through multiple trench etching and filling processes with reference to the method described in FIGS. 2 to 6 in the above embodiments.
  • the aspect ratio is getting smaller and smaller, which can solve the void problem caused by single epitaxial filling of traditional deep trenches.
  • the cost is lower and the deep trench etching process is used.
  • the lateral diffusion of the epitaxial pillar is smaller, the cell pitch can be made smaller, and the doping concentration of each epitaxial pillar is also easier to control.

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Abstract

本公开涉及功率半导体领域，具体公开了一种超结半导体器件及其制备方法，该制备方法包括：通过深沟槽刻蚀工艺在晶圆的第一预定区域刻蚀得到至少一个Ai深沟槽，在所述Ai深沟槽中填充掺杂浓度为NAi的第一外延层形成第i层第一导电类型的外延柱；通过深沟槽刻蚀工艺在晶圆的第二预定区域刻蚀得到至少一个Di深沟槽，在所述Di深沟槽中填充掺杂浓度为NDi的第二外延层形成第i层第二导电类型的外延柱；循环上述步骤在晶圆中制作超结结构。该技术方案可以解决传统深沟槽单次外延填充产生的空洞问题；主要用于制备超结半导体器件。

Description

超结半导体器件及其制备方法 技术领域
本公开涉及功率半导体领域，具体涉及一种超结半导体器件及其制备方法。
背景技术
随着能源转型及汽车电动化高速发展，不断提升电力电子系统效率成为世界各系统厂商的迫切需求。功率半导体器件作为电力电子系统的“心脏”，其本身的性能决定了整个系统的效率。相比于传统功率半导体器件MOSFET(Metal Oxide Semiconductor Field Effect Transistor，金氧半场效晶体管)器件，超结半导体器件SJ-MOSFET(Superjunction MOSFET，超结金氧半场效晶体管)由于采用电荷平衡耐压层结构，打破了所谓的“硅极限”，可显著降低器件导通电阻(在同样电压等级条件下，电阻可降低5～10倍)，提高系统效率。
目前，超结半导体器件的制作工艺主要有两种：一种是多次外延工艺，另一种是深沟槽单次外延填充工艺；其中，多次外延工艺具有外延次数多、成本高等缺点，故现有常用的制作工艺是深沟槽单次外延填充工艺。该深沟槽单次外延填充工艺的流程需要一次深沟刻蚀在N型外延层中形成深沟槽，然后在深沟槽内填充P型外延材料形成交替排列的P柱和N柱；该工艺流程中深沟槽刻蚀及外延层填充均只需一次，工艺相对简单。但是，由于深沟槽深宽比较大(大于10:1)，这给深沟槽内的外延层填充带来困难，容易在深沟槽顶部形成空洞，影响器件性能。
发明内容
为了解决相关技术中的问题，本公开实施例提供一种超结半导体器件及其制备方法。
第一方面，本公开实施例中提供了一种超结半导体器件的制备方法。
该超结半导体器件的制备方法，包括：
通过深沟槽刻蚀工艺在晶圆的第一预定区域刻蚀得到至少一个Ai深沟槽，在所述Ai深沟槽中填充掺杂浓度为N Ai的第一外延层形成第i层第一导电类型的外延柱；
通过深沟槽刻蚀工艺在晶圆的第二预定区域刻蚀得到至少一个Di深沟槽，在所述Di深沟槽中填充掺杂浓度为N Di的第二外延层形成第i层第二导电类型的外延柱；所述Di深沟槽位于所述第i层第一导电类型的外延柱之间；
循环进行上述步骤直至i＝M，得到第一外延柱和第二外延柱，所述第一外延柱包括M段第一外延层，所述第二外延柱包括M段第二外延层；所述i取值为1至M，所述M为大于等于2的整数，随着i的增大，所述Ai深沟槽的深度逐渐减小，所述Di深沟槽的深度也逐渐减小。
在一种可能的实施方式中，所述方法还包括：
在第i层第一导电类型的外延柱表面通过热氧化的方式形成氧化硅薄层；
在第i层第二导电类型的外延柱表面通过热氧化的方式形成氧化硅薄层。
在一种可能的实施方式中，所述通过深沟槽刻蚀工艺在晶圆上刻蚀得到至少一个Ai深沟槽，包括：
在i大于等于2时，形成Ai深沟槽刻蚀所需的光阻，所述光阻的开口大于第i-1层第一导电类型的外延柱的开口；
基于所述光阻，通过深沟槽刻蚀工艺在晶圆上刻蚀得到至少一个Ai深沟槽。
在一种可能的实施方式中，所述方法还包括：
采用退火工艺使第一外延柱和第二外延柱相接触。
在一种可能的实施方式中，在所述晶圆包括半导体衬底和外延层时，所述方法包括：
在第二导电类型的半导体衬底的上表面生长第二导电类型的外延层。
在一种可能的实施方式中，所述晶圆为包括第二导电类型离子的低掺杂高阻晶圆，所述方法还包括：
在刻蚀得到A1深沟槽之后，进行第二导电类型离子的沟槽注入，在所述A1深沟槽中填充掺杂浓度为N A1的第一外延层形成第1层第一导电类型的外延柱；刻蚀D1深沟槽之后，进行第二导电类型离子的沟槽注入，在所述D1深沟槽中填充掺杂浓度为N D1的第二外延层形成第1层第二导电类型的外延柱；A1和D1深沟槽中第二导电类型沟槽注入形成超结场截止层；
刻蚀Ai深沟槽之后在所述Ai深沟槽中填充掺杂浓度为N Ai的第一外延层形成第i层第一导电类型的外延柱；刻蚀Di深沟槽之后在所述Di深沟槽中填充掺杂浓度为N Di的第二外延层形成第i层第二导电类型的外延柱；所述i取值为2至M，所述M为大于等于2的整数，形成超结型结构；
在所述晶圆和所述超结型结构表面同时进行第一导电类型离子的注入，在所述第一外延柱处形成第一导电类型体区，在终端区形成场限环。
在一种可能的实施方式中，所述方法还包括：
通过背面减薄工艺将所述低掺杂高阻晶圆的厚度减薄至预设厚度；
在所述低掺杂高阻晶圆的背面进行第二导电类型离子注入并进行激光退火，形成第二导电类型的衬底。
在一种可能的实施方式中，所述方法还包括：
通过背面减薄工艺将所述低掺杂高阻晶圆的厚度减薄至预设厚度；
在所述低掺杂高阻晶圆的背面进行第一导电类型离子注入并进行激光退火，形成第一导电类型的衬底。
在一种可能的实施方式中，所述方法还包括：
在所述第一外延柱处形成第一导电类型体区，在所述第二外延柱表面形成栅氧层和多晶硅栅层。
在一种可能的实施方式中，所述方法还包括：
在所述第一外延柱处形成第一导电类型体区；
在所述第二外延柱的上端进行沟槽刻蚀并热氧化形成沟槽状的沟槽栅氧化层，然后进行多晶硅淀积形成沟槽多晶硅栅层。
在一种可能的实施方式中，相邻的Ai深沟槽和Di深沟槽之间的间隙的取值范围包括大于0小于等于0.05um。
在一种可能的实施方式中，任一第一外延柱的中心轴线处的电场强度在任意两个相邻第一外延层的交界处形成拐点，所述中心轴线通过所述第一外延柱横向截面的几何中心并沿纵向延伸，所述横向为平行于所述晶圆表面的方向，所述纵向为垂直于所述晶圆表面的方向。
在一种可能的实施方式中，所述第一外延柱包括M段掺杂浓度不同的第一外延层，所述第二外延柱包括M段掺杂浓度不同的第二外延层；所述M段第一外延层中第i段第一外延层的掺杂浓度N Ai与所述M段第二外延层中第i段第二外延层的掺杂浓度N Di满足预设条件使所述超结型结构达到电荷平衡。
在一种可能的实施方式中，在所述M为偶数的情况下，若i为奇数，则N Ai>N Di，若i为偶数，则N Ai<N Di。
在一种可能的实施方式中，在所述M为奇数的情况下，若i＝(M+1)/2，则N Ai＝N Di，若i为奇数且小于(M+1)/2，则N Ai>N Di，若i为偶数且小于(M+1)/2，则N Ai<N Di，若i为奇数且大于(M+1)/2，则N Ai<N Di，若i为偶数且大于(M+1)/2，则N Ai>N Di。
在一种可能的实施方式中，所述第一外延柱与所述第二外延柱的宽度均相同。
在一种可能的实施方式中，所述第一外延柱或所述第二外延柱的宽度的取值范围包括1～6um。
在一种可能的实施方式中，每段第一外延层和每段第二外延层的厚度均相同。
在一种可能的实施方式中，当N Ai不等于N Di时，|N A1-N D1|＝|N A2-N D2|＝……＝|N AM-N DM|<2e12/W；其中，W为所述第一外延柱或所述第二外延柱的宽度。
在一种可能的实施方式中，每段第一外延层和每段第二外延层的厚度的取值范围包括5～10um。
在一种可能的实施方式中，所述M的取值范围为2～10。
在一种可能的实施方式中，所述第一导电类型为N型，所述第二导电类型为P型；
或者，所述第一导电类型为P型，所述第二导电类型为N型。
在一种可能的实施方式中，所述掺杂浓度N Ai和所述掺杂浓度N Di的取值范围包括1e15～1e17cm -3。
第二方面，本公开实施例中提供了一种超结半导体器件。
该超结半导体器件，包括应用第一方面所述的方法制作的超结半导体器件，所述超结半导体器件包括：
晶圆；
超结型结构，形成于所述晶圆中，包括至少一个第一导电类型的第一外延柱及至少一个第二导电类型的第二外延柱，所述第一外延柱与所述第二外延柱横向交替排布，所述第一外延柱包括M段第一外延层，所述第二外延柱包括M段第二外延层，所述第一导电类型与所述第二导电类型相反，所述M为大于等于2的整数，所述横向为平行于晶圆表面的方向。
第三方面，本公开实施例中提供了一种超结半导体器件。
该超结半导体器件，包括：
晶圆；
超结型结构，形成于所述晶圆中，包括至少一个第一导电类型的第一外延柱及至少一个第二导电类型的第二外延柱，所述第一外延柱与所述第二外延柱横向交替排布，所述第一外延柱包括M段掺杂浓度不同的第一外延层，所述第二外延柱包括M段掺杂浓度不同的第二外延层，所述第一导电类型与所述第二导电类型相反，所述M为大于等于2的整数，所述横向为平行于晶圆表面的方向；
其中，所述M段第一外延层中第i段第一外延层的掺杂浓度N Ai与所述M段第二外延层中第i段第二外延层的掺杂浓度N Di满足预设条件使所述超结型结构达到电荷平衡；在所述M为偶数的情况下，若i为奇数，则N Ai>N Di，若i为偶数，则N Ai<N Di。
在一种可能的实施方式中，在所述M为奇数的情况下，若i＝(M+1)/2，则N Ai＝N Di，若i为奇数且小于(M+1)/2，则N Ai>N Di，若i为偶数且小于(M+1)/2，则N Ai<N Di，若i为奇数且大于(M+1)/2，则N Ai<N Di，若i为偶数且大于(M+1)/2，则N Ai>N Di。
在一种可能的实施方式中，所述第一外延柱与所述第二外延柱的宽度均相同。
在一种可能的实施方式中，每段第一外延层和每段第二外延层的厚度均相同。
在一种可能的实施方式中，当N Ai不等于N Di时，|N A1-N D1|＝|N A2-N D2|＝……＝|N AM-N DM|<2e12/W；其中，W为所述第一外延柱或所述第二外延柱的宽度。
在一种可能的实施方式中，所述第一外延柱或所述第二外延柱的宽度的取值范围包括1～6um。
在一种可能的实施方式中，每段第一外延层和每段第二外延层的厚度的取值范围包括5～10um。
在一种可能的实施方式中，所述M的取值范围为2～10。
在一种可能的实施方式中，所述晶圆包括：
第二导电类型的半导体衬底；
第二导电类型的外延层，沉积于所述半导体衬底上，其中，所述超结型结构形成于所述第二导电类型的外延层中。
在一种可能的实施方式中，所述晶圆包括第二导电类型的低掺杂高阻晶圆；所述超结半导体器件还包括：
超结场截止层，位于所述晶圆中的所述超结型结构下方；
超结终端结构，位于所述超结半导体器件边缘。
在一种可能的实施方式中，所述超结终端结构包括场限环。
在一种可能的实施方式中，还包括：
第二导电类型的衬底，位于所述第二导电类型的低掺杂高阻晶圆下方。
在一种可能的实施方式中，还包括：
第一导电类型的衬底，位于所述第二导电类型的低掺杂高阻晶圆下方。
在一种可能的实施方式中，还包括：
第一导电类型体区，形成于所述超结型结构表面；
栅氧层，位于所述第二外延柱的上表面；
多晶硅栅层，位于所述栅氧层的上表面。
在一种可能的实施方式中，还包括：
第一导电类型体区，形成于所述超结型结构表面；
沟槽栅氧层，呈凹槽状，位于所述第二外延柱的上端凹槽中；
沟槽多晶硅栅层，位于所述沟槽栅氧层的凹槽内。
在一种可能的实施方式中，所述第一导电类型为N型，所述第二导电类型为P型；
或者，所述第一导电类型为P型，所述第二导电类型为N型。
在一种可能的实施方式中，所述掺杂浓度N Ai和所述掺杂浓度N Di的取值范围包括1e15～1e17cm -3。
第四方面，本公开实施例中提供了一种超结半导体器件。
该超结半导体器件，包括：
晶圆；
超结结构，形成于所述晶圆中，包括至少一个第一导电类型的第一外延柱及至少一个第二导电类型的第二外延柱，所述第一外延柱与所述第二外延柱横向交替排布，所述第一外延柱包括M段第一外延层，所述第二外延柱包括与所述第一外延层对应的M段第二外延层，所述第一导电类型与所述第二导电类型相反，所述M为大于等于2的整数；
其中，任一第一外延柱的中心轴线处的电场强度在任意两个相邻第一外延层的交界处形成拐点，所述中心轴线通过所述第一外延柱横向截面的几何中心并沿纵向延伸，所述横向为平行于所述晶圆表面的方向，所述纵向为垂直于所述晶圆表面的方向。
在一种可能的实施方式中，所述第一外延柱包括M段掺杂浓度不同的第一外延层，所述第二外延柱包括M段掺杂浓度不同的第二外延层；所述M段第一外延层中第i段第一外延层的掺杂浓度N Ai与所述M段第二外延层中第i段第二外延层的掺杂浓度N Di满足预设条件使所述超结型结构达到电荷平衡。
在一种可能的实施方式中，在所述M为偶数的情况下，若i为奇数，则N Ai>N Di，若i为偶数，则N Ai<N Di。
在一种可能的实施方式中，在所述M为奇数的情况下，若i＝(M+1)/2，则N Ai＝N Di，若i为奇数且小于(M+1)/2，则N Ai>N Di，若i为偶数且小于(M+1)/2，则N Ai<N Di，若i为奇数且大于(M+1)/2，则N Ai<N Di，若i为偶数且大于(M+1)/2，则N Ai>N Di。
在一种可能的实施方式中，所述第一外延柱与所述第二外延柱的宽度均相同。
在一种可能的实施方式中，每段第一外延层和每段第二外延层的厚度均相同。
在一种可能的实施方式中，当N Ai不等于N Di时，|N A1-N D1|＝|N A2-N D2|＝……＝|N AM-N DM|<2e12/W；其中，W为所述第一外延柱或所述第二外延柱的宽度。
在一种可能的实施方式中，所述第一外延柱或所述第二外延柱的宽度的取值范围包括1～6um。
在一种可能的实施方式中，每段第一外延层和每段第二外延层的厚度的取值范围包括5～10um。
在一种可能的实施方式中，所述掺杂浓度N Ai和所述掺杂浓度N Di的取值范围包括1e15～1e17cm -3。
根据本公开实施例提供的技术方案，该超结型结构中第一外延柱和第二外延柱包括多段外延层，需要通过多次的深沟槽刻蚀和填充来形成，在多次的沟槽填充过程中，深宽比越来越小，可以解决传统深沟槽单次外延填充产生的空洞问题；另外，其与多次外延工艺相比，制作超结型结构时，多次外延工艺需要8至9次光刻工艺才能制成的外延柱，使用多次沟槽刻蚀制作的外延柱只需要M次光刻工艺，一般M取值2到3次，即通常只需要2至3次光刻工艺就能制成，需要的光刻工艺次数更少，成本较低，且采用深沟槽刻蚀工艺制作各外延柱，外延柱横向扩散更小，cell pitch(单元间隙)即两个外延柱之间的间隙可以做的更小，而且各外延柱掺杂浓度也更容易控制。
进一步的，该超结型结构中第一外延柱和第二外延柱包括多段外延层，第一外延柱的纵向中心轴线处的电场强度在任意两个相邻第一外延层的交界处形成拐点，可以形成三角波电场分布，与传统单次同一浓度外延层形成的抛物线电场分布相比，本公开的超结半导体器件的击穿电压受外延填充浓度的波动影响较小，具有更大的工艺窗口。
进一步的，可以设置所述M段第一外延层中第i段第一外延层的掺杂浓度N Ai与所述M段第二外延层中第i段第二外延层的掺杂浓度N Di不同且满足在所述M为偶数的情况下，若i为奇数，则N Ai>N Di，若i为偶数，则N Ai<N Di；在所述M为奇数的情况下，若i＝(M+1)/2，则N Ai＝N Di，若i为奇数且小于(M+1)/2，则N Ai>N Di，若i为偶数且小于(M+1)/2，则N Ai<N Di，若i为奇数且大于(M+1)/2，则N Ai<N Di，若i为偶数且大于(M+1)/2，则N Ai>N D；故在器件反向击穿时，与传统单次深沟槽各外延柱具有同一浓度外延层相比，击穿电压受外延层的掺杂浓度的波动影响较小，在击穿电压均满足要求的情况下，本公开的各外延层的掺杂浓度的范围较大，具有更大的工艺窗口。
进一步的，在N Ai不等于N Di时，设置|N A1-N D1|＝|N A2-N D2|＝……＝|N AM-N DM|<2e12/W，则在击穿电压均满足要求的情况下，各外延层的掺杂浓度的波动范围可以进一步增大，具有更大的工艺窗口。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
结合附图，通过以下非限制性实施方式的详细描述，本公开的其它特征、目的和优点将变得更加明显。在附图中：
图1示出现有技术中的深沟槽单次外延填充工艺的流程图。
图2示出根据本公开的实施例的超结半导体器件的制备方法的流程示意图。
图3示出根据本公开的实施例的超结半导体器件的结构示意图。
图4示出根据本公开的实施例的超结半导体器件的制备方法中各步骤流程示意图。
图5示出根据本公开的实施例的超结半导体器件的制备方法中各步骤流程示意图。
图6示出根据本公开的实施例的超结半导体器件的制备方法中部分步骤流程示意图。
图7A示出根据本公开的实施例的第二外延柱的中心轴线处的电场强度沿第二外延柱的深度方向的有效掺杂浓度分布和电场分布示意图。
图7B示出了偶数段掺杂的超结半导体器件与均匀掺杂的超结半导体器件的N型外延柱纵向中心轴线处的电场强度沿N型外延柱的深度方向的电场分布示意图。
图7C示出偶数段掺杂的超结半导体器件与均匀掺杂的超结半导体器件的击穿电压随P型外延柱浓度的变化曲线。
图7D示出了奇数段掺杂的超结半导体器件与均匀掺杂的超结半导体器件的N型外延柱纵向中心轴线处的电场强度沿N型外延柱的深度方向的电场分布示意图。
图7E示出奇数段掺杂的超结半导体器件与均匀掺杂的超结半导体器件的击穿电压随P型外延柱浓度的变化曲线。
图8示出根据本公开的实施例的超结半导体器件的结构示意图。
图9示出根据本公开的又一实施例的超结半导体器件的结构示意图。
图10示出根据本公开的又一实施例的超结半导体器件的结构示意图。
具体实施方式
下文中，将参考附图详细描述本公开的示例性实施例，以使本领域技术人员可容易地实现它们。此外，为了清楚起见，在附图中省略了与描述示例性实施例无关的部分。
在本公开中，应理解，诸如“包括”或“具有”等的术语旨在指示本说明书中所公开的特征、数字、步骤、行为、部件、部分或其组合的存在，并且不欲排除一个或多个其他特征、数字、步骤、行为、部件、部分或其组合存在或被添加的可能性。
另外还需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。下面将参考附图并结合实施例来详细说明本公开。
上文提及，目前，超结半导体器件的制作工艺主要有两种：一种是多次外延工艺，另一种是深沟槽单次外延填充工艺；其中，多次外延工艺具有外延次数多、成本高等缺点，故现有常用的制作工艺是深沟槽单次外延填充工艺。图1示出现有技术中的深沟槽单次外延填充工艺的流程图，如图1所示，该深沟槽单次外延填充工艺的流程可以包括以下步骤：
(1)如图1中A图所示，在N外延层11上形成氧化硅12及深沟槽刻蚀所需的光阻13；
(2)如图1中B图所示，将光阻13图形转移到氧化硅阻挡层14并刻蚀N外延层至所需深度，得到深沟槽15；
(3)如图1中C图所示，在深沟槽15内填充P型外延材料形成交替排列的P柱和N柱；
(4)如图1中D图所示，去除表面的氧化硅阻挡层14然后形成P型体区16、栅氧17及多晶硅栅18。
上述的工艺流程中，深沟槽刻蚀及外延层填充均只需一次，工艺相对简单。但是，由于深沟槽深宽比较大 (大于10:1)，这给深沟槽内的外延层填充带来困难，容易在深沟槽顶部形成空洞，影响器件性能。
为了解决上述问题，本公开提供了一种超结半导体器件及其制备方法。
本公开提供了一种超结半导体器件的制备方法，图2示出根据本公开的实施例的超结半导体器件的制备方法的流程示意图，如图2所示，该方法包括以下步骤：
在步骤S201中，通过深沟槽刻蚀工艺在晶圆的第一预定区域刻蚀得到至少一个Ai深沟槽，在所述Ai深沟槽中填充掺杂浓度为N Ai的第一外延层形成第i层第一导电类型的外延柱；
在步骤S202中，通过深沟槽刻蚀工艺在晶圆的第二预定区域刻蚀得到至少一个Di深沟槽，在所述Di深沟槽中填充掺杂浓度为N Di的第二外延层形成第i层第二导电类型的外延柱；所述Di深沟槽位于所述第i层第一导电类型的外延柱之间；
在步骤S203中，循环进行上述步骤直至i＝M，得到第一外延柱和第二外延柱，所述第一外延柱包括M段第一外延层，所述第二外延柱包括M段第二外延层；所述i取值为1至M，所述M为大于等于2的整数，随着i的增大，所述Ai深沟槽的深度逐渐减小，所述Di深沟槽的深度也逐渐减小。
在一种可能的实施方式中，图3示出根据本公开的实施例的超结半导体器件的结构示意图。如图3所示，通过多次深沟槽刻蚀工艺，可以在晶圆20中形成超结型结构30，该超结型结构30包括至少一个第一导电类型的第一外延柱31及至少一个第二导电类型的第二外延柱32，所述第一外延柱31与所述第二外延柱32横向交替排布，所述横向为平行于晶圆表面的方向，如此就可以形成超结型结构30。
在一种可能的实施方式中，如图3所示，所述第一外延柱31包括M段的第一外延层311，所述第二外延柱32包括M段第二外延层321，所述第一导电类型与所述第二导电类型相反，在所述第一导电类型为N型时，所述第二导电类型为P型；或者，所述第一导电类型为P型时，所述第二导电类型为N型。所述M为大于等于2的整数；可选的，所述M的取值范围可以是2至10，示例的，图3中M取值为4。
在一种可能的实施方式中，所述M段第一外延层中第i段第一外延层的掺杂浓度N Ai与所述M段第二外延层中第i段第二外延层的掺杂浓度N Di满足预设条件使所述超结型结构达到电荷平衡。
在一种可能的实施方式中，第一外延柱31中M段第一外延层的掺杂浓度N Ai可以均相同也可以不同，第二外延柱32中M段第二外延层321的掺杂浓度N Di可以均相同也可以不同。
本公开制备的超结半导体器件，该超结结构中第一外延柱和第二外延柱包括多段外延层，需要通过多次的沟槽刻蚀和填充来形成，在多次的沟槽填充过程中，深宽比越来越小，可以解决传统深沟槽单次外延填充产生的空洞问题，且与多次外延工艺相比，成本较低。
在一种可能的实施方式中，所述方法还包括：
在第i层第一导电类型的外延柱表面通过热氧化的方式形成氧化硅薄层；
在第i层第二导电类型的外延柱表面通过热氧化的方式形成氧化硅薄层。
在该实施方式中，在执行步骤S201得到第i层第一导电类型的外延柱后，会在第i层第一导电类型的外延柱表面通过热氧化的方式形成氧化硅薄层，然后才能执行步骤S202深沟槽刻蚀至少一个Di深沟槽，该氧化硅薄层能够作为阻挡层保护第i层第一导电类型的外延柱不被刻蚀。
在该实施方式中，在执行步骤S202得到第i层第二导电类型的外延柱后，会在第i层第二导电类型的外延柱表面通过热氧化的方式形成氧化硅薄层，然后才能循环执行步骤S201继续进行深沟槽刻蚀，该氧化硅薄层能够作为阻挡层保护第i层第二导电类型的外延柱不被刻蚀。
在一种可能的实施方式中，所述通过深沟槽刻蚀工艺在晶圆上刻蚀得到至少一个Ai深沟槽，包括：
在i大于等于2时，形成Ai深沟槽刻蚀所需的光阻，所述光阻的开口大于第i-1层第一导电类型的外延柱的开口；
基于所述光阻，通过深沟槽刻蚀工艺在晶圆上刻蚀得到至少一个Ai深沟槽。
在该实施方式中，光阻有两种，包括正向光阻(positive photoresist)和负向光阻(negative photoresist)，正向光阻照到光的部分会溶于光阻显影液，而没有照到光的部分不会溶于光阻显影液；负向光阻照到光的部分不会溶于光阻显影液，而没有照到光的部分会溶于光阻显影液。可以先覆盖一整层光阻，然后显影形成Ai深沟槽刻蚀所需的光阻，然后就可以按照该光阻图案，通过深沟槽刻蚀工艺在晶圆上刻蚀得到至少一个Ai深沟槽，在形成Ai深沟槽刻蚀所需的光阻时，该光阻的开口大于第i-1层第一导电类型的外延柱的开口，如此，可以方便在第i- 1层第一导电类型的外延柱处进行Ai深沟槽的刻蚀。这里需要说明的是，当i＝1时，形成Ai深沟槽刻蚀所需的光阻的开口为预设值。
示例的，以所述晶圆包括半导体衬底和外延层为例进行说明，假设该第一导电类型为P型，该第二导电类型为N型，图4示出根据本公开的实施例的超结半导体器件的制备方法中各步骤流程示意图；本公开实施例超结半导体器件的制备方法包括：
步骤401、如图4中A图所示，进行步骤S201，通过深沟槽刻蚀工艺在N型外延层41上刻蚀得到至少一个A1深沟槽，在所述A1深沟槽中填充浓度为N A1的P型外延材料形成第1层P型外延柱即P1柱42；在P1柱表面通过热氧化的方式形成氧化硅薄层43，然后形成N型深沟槽刻蚀所需的光阻44；
这里所述的热氧化指的是硅与含有氧化物质的气体，例如水汽和氧气在高温下进行化学反应，而在硅片表面产生一层致密的二氧化硅(SiO2)薄膜的工艺。光阻有两种，包括正向光阻(positive photoresist)和负向光阻(negative photoresist)，正向光阻照到光的部分会溶于光阻显影液，而没有照到光的部分不会溶于光阻显影液；负向光阻照到光的部分不会溶于光阻显影液，而没有照到光的部分会溶于光阻显影液。可以先覆盖一整层光阻，然后显影形成N型深沟槽刻蚀所需图案即N型深沟槽刻蚀所需的光阻44的图案。
步骤402、如图4中B图所示，进行步骤S202，通过深沟槽刻蚀工艺在N型外延层上刻蚀得到至少一个D1深沟槽即N型深沟槽，在所述D1深沟槽中填充浓度为N D1的N型外延材料形成第1层第二导电类型的外延柱即N1柱45；所述D1深沟槽位于相邻的P1柱42之间；
这里所述的刻蚀是指将显影后所产生的光阻真实地转印到光阻下的材质上，形成由光刻技术定义的图形，即如图4中B图所示，刻蚀掉N型深沟槽刻蚀所需的光阻44的图案未覆盖的部分，通常情况下，刻蚀包括干式刻蚀和湿式刻蚀，本公开中的深沟槽刻蚀工艺是干式刻蚀工艺，该干式刻蚀工艺通常指利用辉光放电(glow discharge)方式，产生包含离子、电子等带电粒子以及具有高度化学活性的中性原子、分子及自由基的电浆，来进行图案转印(pattern transfer)的刻蚀技术。
由于氧化硅对硅有着很高的刻蚀选择比，因此在刻蚀D1深沟槽时P1柱表面的氧化硅薄层能够作为阻挡层保护P1柱不被刻蚀，D1深沟槽的刻蚀深度需和A1深沟槽的刻蚀深度一致，并填充浓度为N D1的N型外延层材料形成N1柱。这里需要说明的是，为了更好地保护在刻蚀D1深沟槽时该P1柱不被刻蚀，如图4中B图所示，刻蚀的D1深沟槽与A1深沟槽之间有预定的间隔。
步骤403、如图4中C图所示，在N1柱45表面通过热氧化的方式形成氧化硅薄层46，然后形成A2深沟槽刻蚀所需的光阻47。
如图4中C图所示，在形成A2深沟槽刻蚀所需的光阻47时，该光阻47的开口大于P1柱的开口，如此，可以方便进行A2深沟槽的刻蚀。
步骤404、如图4中D图所示，继续进行步骤S201，通过A2深沟槽刻蚀，将先前填充的P1柱刻蚀至预定深度(刻蚀后的P1柱厚度剩余5～10um)，然后填充浓度为N A2的P型外延层形成第2层P型外延柱即P2柱48；在P2柱表面通过热氧化的方式形成氧化硅薄层49。
步骤405、如图4中E图所示，进行步骤S202，采用上述同样工艺方法将N1柱刻蚀至和P1柱相同的剩余厚度，并填充浓度为N D2的N型外延材料形成第2层第二导电类型的外延柱即N2柱410；
步骤406、如图4中F图所示，采用同样工艺方法循环进行步骤S201至步骤S202，进行Pi柱和Ni柱的填充和刻蚀，如此形成的P型外延柱即第一外延柱31和N型外延柱即第二外延柱32分别由5段厚度相同但各自浓度不同的外延层组成。
在一种可能的实施方式中，上述制备方法还可以包括以下步骤：
采用退火工艺使第一外延柱和第二外延柱相接触。
在该实施方式中，退火工艺指的是缓慢加热到一定温度，保持足够时间，然后以适宜速度冷却的一种热处理工艺。
在一种可能的实施方式中，在所述晶圆包括半导体衬底和外延层时，所述方法包括：
在第二导电类型的半导体衬底的上表面生长第二导电类型的外延层。
在该实施方式中，可以使用外延层生长工艺来生长外延层，该外延层生长工艺指的是利用晶体界面上的二维结构相似性成核的原理，在一块单晶片上，沿着其原来的结晶轴方一向再生长一层晶格完整、且可以具有不 同的杂质浓度和厚度的单晶层的工艺。外延生长工艺包括气相外延、液相外延和分子束外延等，目前常用的是气相外延工艺。
仍以上述示例为例，第二导电类型为N型，可以在N+衬底的上表面生成N型外延层。
在一种可能的实施方式中，在所述晶圆包括第二导电类型的低掺杂高阻晶圆，所述方法还可以包括以下步骤：
在分别形成所述A1深沟槽和D1深沟槽之后，进行第二导电类型沟槽注入，形成超结场截止层，具体步骤如下：
在刻蚀得到A1深沟槽之后，进行第二导电类型离子的沟槽注入，在所述A1深沟槽中填充掺杂浓度为N A1的第一外延层形成第1层第一导电类型的外延柱；刻蚀D1深沟槽之后，进行第二导电类型离子的沟槽注入，在所述D1深沟槽中填充掺杂浓度为N D1的第二外延层形成第1层第二导电类型的外延柱；A1和D1深沟槽中第二导电类型沟槽注入形成超结场截止层；
刻蚀Ai深沟槽之后在所述Ai深沟槽中填充掺杂浓度为N Ai的第一外延层形成第i层第一导电类型的外延柱；刻蚀Di深沟槽之后在所述Di深沟槽中填充掺杂浓度为N Di的第二外延层形成第i层第二导电类型的外延柱；所述i取值为2至M，所述M为大于等于2的整数，形成超结型结构；
在表面进行第一导电类型离子的注入，在所述第一外延柱处形成第一导电类型体区，在终端区形成场限环。
在该实施方式中，该注入指的是离子注入。
在该实施方式中，根据泊松方程，电场衰减梯度与电荷浓度成正比，因此较高浓度的超结场截止层能够使电场迅速衰减并在该层截止，防止耗尽区扩展至器件的背表面而导致穿通，该超结场截止层也可称为缓冲层。
示例的，以所述晶圆为N-低掺杂高阻晶圆为例进行说明，假设该第一导电类型为P型，该第二导电类型为N型，图5示出根据本公开的实施例的超结半导体器件的制备方法中各步骤流程示意图；本公开实施例超结半导体器件的制备方法包括：
步骤501、如图5中A图所示，进行步骤S201，通过深沟槽刻蚀工艺在N-低掺杂高阻晶圆51上刻蚀得到至少一个A1深沟槽，在该A1深沟槽的底部进行N型沟槽注入，在A1深沟槽下方形成部分的超结场截止层52；在所述A1深沟槽中填充浓度为N A1的P型外延材料形成第1层P型外延柱即P1柱53；在P1柱表面通过热氧化的方式形成氧化硅薄层54，然后形成N型深沟槽刻蚀所需的光阻55；
步骤502、如图5中B图所示，进行步骤S202，通过深沟槽刻蚀工艺在N-低掺杂高阻晶圆51上刻蚀得到至少一个D1深沟槽即N型深沟槽，在该D1深沟槽的底部进行N型沟槽注入，形成另一部分的超结场截止层56，与上述A1深沟槽下方的部分超结场截止层共同形成该超结场截止层；在所述D1深沟槽中填充浓度为N D1的N型外延材料形成第1层第二导电类型的外延柱即N1柱57；所述D1深沟槽位于相邻的P1柱之间；
由于氧化硅对硅有着很高的刻蚀选择比，因此在刻蚀D1深沟槽时P1柱表面的氧化硅薄层能够作为阻挡层保护P1柱不被刻蚀，D1深沟槽的刻蚀深度需和A1深沟槽的刻蚀深度一致，并填充浓度为N D1的N型外延层材料形成N1柱。这里需要说明的是，为了更好地保护在刻蚀D1深沟槽时该P1柱不被刻蚀，如图5中B图所示，刻蚀的D1深沟槽与A1深沟槽之间有预定的间隔。
步骤503、如图5中C图所示，在N1柱57表面通过热氧化的方式形成氧化硅薄层58，然后形成A2深沟槽刻蚀所需的光阻59，光阻59开口大于P1柱的开口；
步骤505、如图5中D图所示，继续进行步骤S201，通过A2深沟槽刻蚀，将先前填充的P1柱刻蚀至预定深度(刻蚀后的P1柱厚度剩余5～10um)，然后填充浓度为N A2的P型外延层形成第2层P型外延柱即P2柱510；在P2柱510表面通过热氧化的方式形成氧化硅薄层511。
步骤505、如图5中E图所示，进行步骤S202，采用上述同样工艺方法将N1柱刻蚀至和P1柱相同的剩余厚度，并填充浓度为N D2的N型外延材料形成第2层第二导电类型的外延柱即N2柱512；
步骤506、如图5中F图所示，采用同样工艺方法循环进行步骤S201至步骤S202，进行Pi柱和Ni柱的填充和刻蚀，使得P型外延柱即第一外延柱31和N型外延柱即第二外延柱32分别由5段厚度相同但各自浓度不同的外延层组成。
图6示出根据本公开的实施例的超结半导体器件的制备方法中部分步骤流程示意图；在进行上述步骤形成P型外延柱和N型外延柱之后，需要进行表面工艺和背面工艺，主要工艺流程如图6所示，包括以下步骤：
步骤407、如图6中A图所示，进行表面工艺，在表面进行P型注入，形成P体区61和终端场限环62；在N型外延柱表面进行热氧化形成栅氧层63，然后进行多晶硅淀积形成多晶硅栅层64，如此形成表面MIS(Metal-Insulator-Semiconductor，金属-绝缘层-半导体结构)结构。
在一种可能的实施方式中，在进行上述步骤之后，还需要进行背面工艺，所述方法还可以包括以下步骤：
通过背面减薄工艺将所述低掺杂高阻晶圆的厚度减薄至预设厚度；
在所述低掺杂高阻晶圆的背面进行第二导电类型离子注入并进行激光退火，形成第二导电类型的衬底。
在该实施方式中，仍以N-低掺杂高阻晶圆为例进行说明，如图6中B图所示，进行背面工艺，通过背面减薄工艺将所述低掺杂高阻晶圆的厚度减薄至预设厚度，示例的，整个晶圆厚度为50～70um，可以将该低掺杂高阻晶圆从背面减薄至该超结场截止层附近；然后在背部进行N型注入并进行激光退火，形成N+衬底65。该N型注入指的是采用离子注入的方式注入N型材料，该N型材料指的是以电子为主导电的材料。
在该实施方式中，背面减薄工艺是一步重要的半导体制造工艺，目的是去除晶圆背面多余材料，以有效减小晶圆封装体积，降低热阻，提高器件的散热性能，降低封装后芯片因受热不均而开裂的风险，提高产品可靠性；同时，减薄后的芯片机械性能与电气性能也得到显著提高。背面减薄工艺有很多种，如磨削、抛光、干式抛光、电化学腐蚀、湿法腐蚀、等离子辅助化学腐蚀和常压等离子腐蚀等。其中，磨削减薄技术是一种效率高、成本较低的减薄技术，已得到广泛应用，该技术通过砂轮在晶圆表面旋转施压、损伤、破裂、移除而实现晶圆减薄。
在一种可能的实施方式中，该背面工艺也可以是下述步骤：
通过背面减薄工艺将所述低掺杂高阻晶圆的厚度减薄至预设厚度；
在所述低掺杂高阻晶圆的背面进行第一导电类型离子注入并进行激光退火，形成第一导电类型的衬底。
在该实施方式中，该超结半导体器件可以是SJ-IGBT(Super Junction Insulated Gate Bipolar Transistor，超结绝缘栅双极型晶体管)器件，该背面工艺与上述不同的是，通过背面减薄工艺将低掺杂高阻晶圆的厚度减薄至预设厚度，示例的，整个晶圆厚度为50～70um，可以将该低掺杂高阻晶圆从背面减薄至该超结场截止层附近；然后在背部进行P型注入并进行激光退火，形成P+衬底。该P型注入指的是采用离子注入的方式注入P型材料，该P型材料指的是以空穴为主导电的材料。
在一种可能的实施方式中，上述制备方法还可以包括以下步骤：
在所述第一外延柱处形成第一导电类型体区，在所述第二外延柱表面形成栅氧层和多晶硅栅层。
仍以上述示例为例，可以在P型外延柱处进行P型注入形成P体区，在N型外延柱表面进行热氧化形成栅氧层，然后进行多晶硅淀积形成多晶硅栅层。示例的，如图6中A图所示，在N型外延柱表面进行热氧化形成栅氧层63，然后进行多晶硅淀积形成多晶硅栅层64，如此形成表面MIS结构。
在一种可能的实施方式中，上述制备方法还可以包括以下步骤：
在所述第一外延柱处形成第一导电类型体区；
在所述第二外延柱的上端进行沟槽刻蚀并热氧化形成沟槽状的沟槽栅氧化层，然后进行多晶硅淀积形成沟槽多晶硅栅层。
在该实施方式中，可以在P型外延柱处进行P型注入形成P体区，在N型外延柱表面进行上端进行沟槽刻蚀，然后进行热氧化形成沟槽栅氧层，接着在沟槽栅氧层的凹槽内上进行多晶硅淀积形成沟槽多晶硅栅层，如此形成沟槽MIS结构。
在一种可能的实施方式中，相邻的Ai深沟槽和Di深沟槽之间的间隙的取值范围为大于0小于等于0.05um；方便两类深沟槽互不影响地进行刻蚀。
在一种可能的实施方式中，任一第一外延柱的中心轴线处的电场强度在任意两个相邻第一外延层的交界处形成拐点，所述中心轴线通过所述第一外延柱横向截面的几何中心并沿纵向延伸，所述横向为平行于所述晶圆表面的方向，所述纵向为垂直于所述晶圆表面的方向。由于超结结构内电荷平衡，该任一第二外延柱的中心轴线处的电场强度在任意两个相邻第二外延层的交界处也会形成拐点。
本公开提供的超结半导体器件中第一外延柱和第二外延柱包括多段外延层，可以通过多次的沟槽填充来形成，在多次的沟槽填充过程中，深宽比越来越小，可以解决传统深沟槽单次外延填充产生的空洞问题；而且，在器件反向击穿时，第一外延柱的纵向中心轴线处的电场强度在任意两个相邻第一外延层的交界处形成拐点， 可以形成三角波电场分布，与传统单次同一浓度外延层形成的抛物线电场分布相比，本公开的超结半导体器件的击穿电压受外延填充浓度的波动影响较小，具有更大的工艺窗口。
在一种可能的实施方式中，为了形成上述的三角波电场分布，所述第一外延柱包括M段掺杂浓度不同的第一外延层，所述第二外延柱包括M段掺杂浓度不同的第二外延层；所述M段第一外延层中第i段第一外延层的掺杂浓度N Ai与所述M段第二外延层中第i段第二外延层的掺杂浓度N Di满足预设条件使所述超结型结构达到电荷平衡。
在一种可能的实施方式中，在所述M为偶数的情况下，为了形成上述的三角波电场分布，若i为奇数，则N Ai>N Di，若i为偶数，则N Ai<N Di。
在该实施方式中，假设M为4，则，N A1>N D1，N A2<N D2，N A3>N D3，N A4<N D4。
在一种可能的实施方式中，在所述M为奇数的情况下，形成上述的三角波电场分布，若i＝(M+1)/2，则N Ai＝N Di，若i为奇数且小于(M+1)/2，则N Ai>N Di，若i为偶数且小于(M+1)/2，则N Ai<N Di，若i为奇数且大于(M+1)/2，则N Ai<N Di，若i为偶数且大于(M+1)/2，则N Ai>N Di。
示例的，假设M为5，则，N A1>N D1，N A2<N D2，N A3＝N D3，N A4>N D4，N A5<N D5。
在一种可能的实施方式中，所述第一外延柱与所述第二外延柱的宽度均相同。
在一种可能的实施方式中，所述第一外延柱或所述第二外延柱的宽度的取值范围为1～6um。
在一种可能的实施方式中，每段第一外延层和每段第二外延层的厚度均相同。
在一种可能的实施方式中，每段第一外延层和每段第二外延层的厚度的取值范围为5～10um。
在一种可能的实施方式中，为了满足电荷平衡条件，在所述第一外延柱与所述第二外延柱的宽度均相同，每段第一外延层和每段第二外延层的厚度均相同时，且掺杂浓度满足当N Ai不等于N Di时，|N A1-N D1|＝|N A2-N D2|＝……＝|N AM-N DM|<2e12/W；其中，W为所述第一外延柱或所述第二外延柱的宽度。
在一种可能的实施方式中，所述掺杂浓度N Ai和所述掺杂浓度N Di的取值范围分别为1e15～1e17cm -3。该掺杂浓度用于表示掺杂的杂质原子在基质中的数量，单位为每立方厘米的掺杂原子个数。
以下将本公开的不同掺杂浓度外延层的超结半导体器件与现有技术中单次同一浓度外延层的超结半导体器件的性能进行对比测试：
图7A示出根据本公开的实施例的第二外延柱的中心轴线处的电场强度沿第二外延柱的深度方向的有效掺杂浓度分布和电场分布示意图，图7A中的x坐标为第二外延柱32沿第二外延柱32的深度方向AA’方向的深度，y1坐标为有效掺杂浓度N Ai-N Di，y2坐标为第二外延柱的纵向中心轴线处的电场强度，假设本公开提供的超结半导体器件中的第一外延柱31有M＝5段第一外延层，第二外延柱32有M＝5段第二外延层，且N A1>N D1，N A2<N D2，N A3＝N D3，N A4>N D4，N A5<N D5，则有效掺杂浓度N Ai-N Di就是图7A中脉冲折线701所示，基于泊松方程，可以得到第二外延柱32的纵向中心轴线处的电场强度沿第二外延柱的深度方向即AA’方向的变化如图7A中的三角波折线702所示，而图1所示的现有技术中超结半导体器件的有效掺杂浓度为一条直线，由于沟槽角度影响，该图1所示的超结半导体器件的第一外延柱的中心轴线处的电场强度沿AA’方向的变化如图7A中的曲线703所示，多段不同掺杂浓度的第二外延层形成的第二外延柱32的纵向中心轴线处可以形成图7A所示的三角波电场分布，其在任意两个相邻第一外延层的交界处即a1、a2、a3和a4处都会形成拐点(这里需要说明的是，多段不同掺杂浓度的第一外延层形成的第一外延柱31的纵向中心轴线处沿该第一外延柱31的深度方向也形成三角波电场分布，形状与曲线702对称)。与现有技术中产生抛物线电场分布的单次同一浓度外延柱形成的超结半导体器件的相比，本公开的超结半导体器件的击穿电压受外延填充浓度的波动影响较小，具有更大的工艺窗口。
以下以具体实例进行说明：
在一个具体的实例中，该超结半导体器件为偶数段掺杂的超结半导体器件，M＝2，该偶数段掺杂的超结半导体器件中第一外延柱为P型外延柱(也称P柱)，第二外延柱为N型外延柱，M＝2，N A1＝3.99e15cm - 3<N D1＝4.2e15cm -3，N A2＝4.2e15cm -3>N D2＝3.99e15cm -3，W＝4.5um，|N A1-N D1|*W＝|N A2-N D2|*W<2e12；该均匀掺杂的超结半导体器件中P型外延柱的掺杂浓度N A，N型外延柱的掺杂浓度N D，其中，N A＝N D＝4.2e15cm -3。将上述的均匀掺杂的超结半导体器件和偶数段掺杂的超结半导体器件比较如下：
图7B示出了偶数段掺杂的超结半导体器件与均匀掺杂的超结半导体器件的N型外延柱纵向中心轴线处的电场强度沿N型外延柱的深度方向的电场分布示意图，如图7B所示，均匀掺杂的超结半导体器件的N型外延柱纵 向中心轴线处的电场分布为开口向下的抛物线分布，而M＝2时，偶数段掺杂的超结半导体器件的N型外延柱纵向中心轴线处的电场强度在两段外延层的交界处即图7B中b1位置处形成拐点，整体的电场分布呈三角波分布，该三角波峰值位于两段外延层的交界处即图7B中b1位置处。
同时，图7C示出偶数段掺杂的超结半导体器件与均匀掺杂的超结半导体器件的击穿电压随P型外延柱浓度的变化曲线。由图7C可以看出，击穿电压的目标值为600V时，现有技术中均匀掺杂的超结半导体器件，P型外延柱掺杂浓度可以在原定掺杂浓度的基础上在-3％到3％范围内变化时，击穿电压满足要求；而本公开偶数段掺杂的超结半导体器件，P型外延柱掺杂浓度可以在原定掺杂浓度的基础上在-8％到6％范围内变化时，击穿电压均满足要求，可以看出在击穿电压满足要求的情况下，本公开偶数段掺杂的超结半导体器件具有更大的器件工艺制造窗口。
在另一个具体的实例中，该超结半导体器件为奇数段掺杂的超结半导体器件，M＝3，该奇数段掺杂的超结半导体器件中第一外延柱为P型外延柱(也称P柱)，第二外延柱为N型外延柱，N A1＝4.1e15cm -3<N D1＝4.3e15cm -3，N A2＝4.2e15cm -3＝N D2＝4.2e15cm -3，N A3＝4.3e15cm -3>N D1＝4.1e15cm -3，W＝4.5um，|N A1-N D1|*W＝|N A3-N D3|*W<2e12；该均匀掺杂的超结半导体器件中P型外延柱的掺杂浓度N A，N型外延柱的掺杂浓度N D，其中，N A＝N D＝4.2e15cm -3。将上述的均匀掺杂的超结半导体器件和奇数段掺杂的超结半导体器件比较如下：
图7D示出了奇数段掺杂的超结半导体器件与均匀掺杂的超结半导体器件的N型外延柱纵向中心轴线处的电场强度沿N型外延柱的深度方向的电场分布示意图，如图7D所示，均匀掺杂的超结半导体器件的N型外延柱纵向中心轴线处的电场分布为开口向下的抛物线分布，而M＝3时，奇数段掺杂的超结半导体器件在N型外延柱纵向中心轴线处的电场强度在两段外延层的交界处即图7D中d1和d2位置处形成拐点，每相邻两段外延层所在区域的电场分布呈三角波分布，即在d1位置处交界的两段外延层所在区域的电场强度如图7D中d1左侧以及d1和d2之间的电场强度变化曲线，在d2位置处交界的两段外延层所在区域的电场强度如图7D中d2右侧以及d1和d2之间的电场强度变化曲线，这两部分电场强度变化曲线均是三角波曲线，该三角波峰值位于两段外延层的两两交界处即图7D中d1和d2位置处。这里需要说明的是，由于N A2＝N D2，故第二段外延层所在区域(即d1位置至d2位置之间区域)对应的纵向中心轴线处的电场强度分布较平缓，几乎是一条直线。
同时，图7E示出奇数段掺杂的超结半导体器件与均匀掺杂的超结半导体器件的击穿电压随P型外延柱浓度的变化曲线。如图7E所示，击穿电压的目标值为600V时，现有均匀掺杂的超结半导体器件，P型外延柱掺杂浓度可以在原定掺杂浓度的基础上在-3％到3％范围内变化时，击穿电压满足要求；而本公开奇数段掺杂的超结半导体器件，P型外延柱掺杂浓度可以在原定掺杂浓度的基础上在-10％到6％范围内变化时，击穿电压均满足要求，可以看出在击穿电压满足要求的情况下，本公开奇数段掺杂的超结半导体器件具有更大的器件工艺制造窗口。
本公开还提供了一种超结半导体器件，该超结半导体器件可以通过上述的制备方法制备而成，如图3所示，该超结半导体器件可以包括晶圆20和超结型结构30。该超结型结构30形成于所述晶圆20中，包括至少一个第一导电类型的第一外延柱31及至少一个第二导电类型的第二外延柱32，所述第一外延柱31与所述第二外延柱32横向交替排布，所述横向为平行于晶圆表面的方向，如此就可以形成超结型结构30。
所述第一外延柱31包括M段第一外延层311，所述第二外延柱32包括M段第二外延层321，所述第一导电类型与所述第二导电类型相反，一种主要是电子导电，另一种主要是空穴导电。示例的，在所述第一导电类型为N型(即参与导电的主要是电子)时，所述第二导电类型为P型(即参与导电的主要是空穴)；或者，所述第一导电类型为P型时，所述第二导电类型为N型。所述M为大于等于2的整数；可选的，所述M的取值范围可以是2至10，示例的，图3中M取值为4。
本实施方式中涉及的技术术语和技术特征与图2至图7E所示及相关实施方式中提及的技术术语和技术特征相同或相似，对于本实施方式相关实施方式中涉及的技术术语和技术特征的解释和说明可参考上述对于图2-图7E所示及相关实施方式的解释的说明，此处不再赘述。
本公开还提供了一种超结半导体器件，如图3所示，该超结半导体器件可以包括晶圆20和超结型结构30。
在本公开一种可能的实施方式中，该晶圆20是指制作硅半导体电路所用的硅晶片，其原始材料是硅，高纯度的多晶硅溶解后掺入硅晶体晶种，然后慢慢拉出，形成圆柱形的单晶硅，硅晶棒在经过研磨，抛光，切片后，形成硅晶圆片，也就是晶圆。
在本公开一种可能的实施方式中，图8示出根据本公开的实施例的超结半导体器件的结构示意图；图9示出根据本公开的又一实施例的超结半导体器件的结构示意图。该晶圆可以如图8所示包括由半导体衬底21和外延层22，该晶圆制备包括衬底制备和外延工艺两大环节，衬底(substrate)是由半导体单晶材料制造而成的晶圆片，衬底可以直接进入晶圆制造环节生产半导体器件，也可以进行外延工艺加工生产外延片。外延(epitaxy)是指在经过切、磨、抛等仔细加工的单晶衬底上生长一层新单晶的过程，新单晶可以与衬底为同一材料，也可以是不同材料(同质外延或者是异质外延)。由于新生单晶层按衬底晶相延伸生长，从而被称之为外延层(厚度通常为几微米，以硅为例：硅外延生长其意义是在具有一定晶向的硅单晶衬底上生长一层具有和衬底相同晶向的电阻率与厚度不同的晶格结构完整性好的晶体)，而长了外延层的衬底称为外延片(外延片＝外延层+衬底)。器件制作通常在外延层上展开。
在本公开一种可能的实施方式中，该晶圆也可以如图9所示，是轻掺杂高阻晶圆23如FZ(Float Zone)晶圆等。本公开中的掺杂(doping)是半导体制造工艺中，为纯的本征半导体引入杂质，使之电气属性被改变的过程，引入的杂质与要制造的半导体种类有关，半导体的常用掺杂技术主要有两种，第一种为高温(热)扩散即将掺杂气体导入放有硅片的高温炉，将杂质扩散到硅片内的一种技术；第二种为离子注入法，即通过离子注入机的加速和引导，将要掺杂的离子以离子束形式入射到材料中去，离子束与材料中的原子或分子发生一系列理化反应，入射离子逐渐损失能量，并引起材料表面成分、结构和性能发生变化，最后停留在材料中。本征半导体经过掺杂就形成导电性能更好的杂质半导体，由于导电类型不同，一般可分为N型半导体和P型半导体，示例的，在本征半导体中每掺入1个磷原子就可产生1个自由电子，而本征激发产生的空穴的数目不变。这样，在掺入磷的半导体中，自由电子的数目就远远超过了空穴数目，成为多数载流子(简称多子)，空穴则为少数载流子(简称少子)。显然，参与导电的主要是电子，故这种半导体称为电子型半导体，简称N型半导体，此种掺杂也称为N型掺杂。在本征半导体中每掺入1个硼原子就可以提供1个空穴，当掺入一定数量的硼原子时，就可以使半导体中空穴的数目远大于本征激发电子的数目，成为多数载流子，而电子则成为少数载流子。显然，参与导电的主要是空穴，故这种半导体称为空穴型半导体，简称P型半导体，此种掺杂也称为P型掺杂。
在该实施方式中，超结型结构是由P型掺杂的柱状区域和N型掺杂的柱状区域组成，当P型掺杂区域的电荷数量同N型掺杂区域的电荷数量相当，达到平衡时，超结效果最佳，其耐压与导通电阻的平衡关系最优。
在本公开一种可能的实施方式中，如图3所示，超结型结构30形成于所述晶圆20中，包括至少一个第一导电类型的第一外延柱31及至少一个第二导电类型的第二外延柱32，所述第一外延柱31与所述第二外延柱32横向交替排布，所述横向为平行于晶圆表面的方向，如此就可以形成超结型结构30。
在本公开一种可能的实施方式中，如图3所示，所述第一外延柱31包括M段第一外延层311，所述第二外延柱32包括M段第二外延层321，所述第一导电类型与所述第二导电类型相反，一种主要是电子导电，另一种主要是空穴导电。示例的，在所述第一导电类型为N型(即参与导电的主要是电子)时，所述第二导电类型为P型(即参与导电的主要是空穴)；或者，所述第一导电类型为P型时，所述第二导电类型为N型。所述M为大于等于2的整数；可选的，所述M的取值范围可以是2至10，示例的，图3中M取值为4。
在本公开一种可能的实施方式中，所述第一外延柱31包括M段掺杂浓度不同的第一外延层311，所述第二外延柱32包括M段掺杂浓度不同的第二外延层321；所述M段第一外延层311中第i段第一外延层的掺杂浓度N Ai与所述M段第二外延层321中第i段第二外延层的掺杂浓度N Di满足预设条件使所述超结型结构达到电荷平衡。
在本公开一种可能的实施方式中，在所述M为偶数的情况下，若i为奇数，则N Ai>N Di，若i为偶数，则N Ai<N Di。示例的，如图3所示，该M为4，则，N A1>N D1，N A2<N D2，N A3>N D3，N A4<N D4。
本公开提供的超结结构中第一外延柱和第二外延柱包括多段不同掺杂浓度的外延层，由于所述M段第一外延层中第i段第一外延层的掺杂浓度N Ai与所述M段第二外延层中第i段第二外延层的掺杂浓度N Di不同且满足在所述M为偶数的情况下，若i为奇数，则N Ai>N Di，若i为偶数，则N Ai<N Di；故在器件反向击穿时，与传统的具有同一掺杂浓度外延柱相比，击穿电压受外延柱的掺杂浓度的波动影响较小，即在击穿电压均满足要求的情况下，本公开的偶数段的外延层的掺杂浓度可以有较大的波动范围，具有更大的工艺窗口。
在本公开一种可能的实施方式中，所述M为奇数的情况下，若i＝(M+1)/2，则N Ai＝N Di，若i为奇数且小于(M+1)/2，则N Ai>N Di，若i为偶数且小于(M+1)/2，则N Ai<N Di，若i为奇数且大于(M+1)/2，则 N Ai<N Di，若i为偶数且大于(M+1)/2，则N Ai>N Di。
示例的，假设M为5，则，N A1>N D1，N A2<N D2，N A3＝N D3，N A4>N D4，N A5<N D5。
本公开提供的超结结构中第一外延柱和第二外延柱包括多段不同掺杂浓度的外延层，由于所述M段第一外延层中第i段第一外延层的掺杂浓度N Ai与所述M段第二外延层中第i段第二外延层的掺杂浓度N Di不同且满足在所述M为偶数的情况下，若i为奇数，则N Ai>N Di，若i为偶数，则N Ai<N Di；故在器件反向击穿时，与传统的具有同一掺杂浓度外延柱相比，击穿电压受外延柱的掺杂浓度的波动影响较小，即在击穿电压均满足要求的情况下，本公开的奇数段的外延层的掺杂浓度可以有较大的波动范围，具有更大的工艺窗口。
在一种可能的实施方式中，所述第一外延柱与所述第二外延柱的宽度均相同。
在一种可能的实施方式中，所述第一外延柱或所述第二外延柱的宽度的取值范围为1～6um。
在一种可能的实施方式中，每段第一外延层和每段第二外延层的厚度均相同。
在一种可能的实施方式中，每段第一外延层和每段第二外延层的厚度的取值范围为5～10um。
在一种可能的实施方式中，为了满足电荷平衡条件，在所述第一外延柱与所述第二外延柱的宽度均相同，每段第一外延层和每段第二外延层的厚度均相同时，且掺杂浓度满足当N Ai不等于N Di时，|N A1-N D1|＝|N A2-N D2|＝……＝|N AM-N DM|<2e12/W；其中，W为所述第一外延柱或所述第二外延柱的宽度。
在一种可能的实施方式中，所述掺杂浓度N Ai和所述掺杂浓度N Di的取值范围包括1e15～1e17cm -3。该掺杂浓度用于表示掺杂的杂质原子在基质中的数量，单位为每立方厘米的掺杂原子个数。
在一种可能的实施方式中，如图8所示，所述晶圆包括：第二导电类型的半导体衬底21；第二导电类型的外延层22，沉积于所述半导体衬底21上，其中，所述超结型结构30形成于所述第二导电类型的外延层22中。
示例的，第二导电类型为N型时，该半导体衬底可以是N+衬底，N+表示高浓度N型掺杂，该外延层可以是N外延层。该衬底的材料可以是其它宽禁带半导体材料如GaN(氮化镓)、SiC(碳化硅)等。
在一种可能的实施方式中，如图9所示，所述晶圆20包括第二导电类型的低掺杂高阻晶圆23；所述超结半导体器件还包括：
超结场截止(Field Stop)层28，位于所述晶圆中的所述超结型结构下方；示例的，如图9所示，该第二导电类型为N型，则该超结场截止层可以是N型注入形成。当然，若该第二导电类型为P型，则该超结场截止层可以是P型注入形成，这里的注入指的是离子注入。
超结终端结构29，位于所述超结半导体器件边缘。
所述超结终端结构29可以包括场限环、场板、横向变掺杂(VLD)和结终端扩展(JTE)等终端结构，优选的，如图9所示，所述超结终端结构29可以包括场限环。
在一种可能的实施方式中，如图9所示，该第二导电类型的低掺杂高阻晶圆下方设置有衬底24，该衬底24可以是第二导电类型的衬底，或者，超结半导体器件为SJ-IGBT器件时，该衬底24可以是第一导电类型的衬底。
在一种可能的实施方式中，如图8和图9所示，该超结半导体器件还包括：第一导电类型体区25、栅氧层26及多晶硅栅层27。
如图8或图9所示，该第一导电类型体区25，形成于所述超结型结构表面处，可以通过在第一外延柱的表面进行第一导电类型离子的注入形成该第一导电类型体区25。该栅氧层26位于所述第二外延柱的上表面；该多晶硅栅层27位于所述栅氧层26的上表面，如此形成表面MIS结构。
示例的，图8所示的超结半导体器件的制备过程可以包括：
在第二导电类型的半导体衬底21的上表面生长第二导电类型的外延层22；
通过步骤S201至步骤S203，在该外延层22上形成超结型结构30，该超结型结构30包括至少一个第一导电类型的第一外延柱及至少一个第二导电类型的第二外延柱，所述第一外延柱与所述第二外延柱横向交替排布，所述第一外延柱包括M段掺杂浓度不同的第一外延层，所述第二外延柱包括M段掺杂浓度不同的第二外延层，所述第一导电类型与所述第二导电类型相反，所述M为大于等于2的整数；
在所述第一外延柱处形成第一导电类型体区25，在所述第二外延柱表面形成栅氧层26和多晶硅栅层27。
采用退火工艺使第一外延柱和第二外延柱相接触。
示例的，图9所示的超结半导体器件的制备过程可以包括：
通过步骤S501至S506，在低掺杂高阻晶圆23上形成超结型结构30，在所述超结型结构下方形成超结场截 止层28，该超结型结构30包括至少一个第一导电类型的第一外延柱及至少一个第二导电类型的第二外延柱，所述第一外延柱与所述第二外延柱横向交替排布，所述第一外延柱包括M段掺杂浓度不同的第一外延层，所述第二外延柱包括M段掺杂浓度不同的第二外延层，所述第一导电类型与所述第二导电类型相反，所述M为大于等于2的整数；
进行表面工艺，在表面进行第一导电类型离子的注入，在所述第一外延柱处形成第一导电类型体区25，在终端区形成超结终端结构29即场限环；在所述第二外延柱表面形成栅氧层26和多晶硅栅层27；
进行背面工艺，通过背面减薄工艺将所述低掺杂高阻晶圆的厚度减薄至预设厚度；在所述低掺杂高阻晶圆的背面进行第二导电类型离子注入并进行激光退火，形成第二导电类型的衬底24。
采用退火工艺使第一外延柱和第二外延柱相接触。
在一种可能的实施方式中，图10示出根据本公开的又一实施例的超结半导体器件的结构示意图，如图10所示，该超结半导体器件还包括：第一导电类型体区25、沟槽栅氧层210及沟槽多晶硅栅层211。
该超结半导体器件可以是SGT(Shielded Gate Transistor，屏蔽栅极沟槽)器件，如图10所示，该SGT器件中，该第一导电类型体区25，形成于所述超结型结构表面处，可以通过在第一外延柱的表面进行第一导电类型离子的注入形成该第一导电类型体区25。沟槽栅氧层210呈凹槽状，位于所述第二外延柱的上端凹槽中；沟槽多晶硅栅层211，位于所述沟槽栅氧层210的凹槽内，如此形成沟槽MIS结构。
示例的，图10所示的超结半导体器件的制备过程可以包括：
通过步骤S501至S506，在低掺杂高阻晶圆23上形成超结型结构30，在所述超结型结构下方形成超结场截止层28；该超结型结构30包括至少一个第一导电类型的第一外延柱及至少一个第二导电类型的第二外延柱，所述第一外延柱与所述第二外延柱横向交替排布，所述第一外延柱包括M段掺杂浓度不同的第一外延层，所述第二外延柱包括M段掺杂浓度不同的第二外延层，所述第一导电类型与所述第二导电类型相反，所述M为大于等于2的整数；
进行表面工艺，在所述第一外延柱处形成第一导电类型体区25，在终端区形成超结终端结构29即场限环，在所述第二外延柱的上端进行沟槽刻蚀并热氧化形成沟槽状的沟槽栅氧化层210，然后进行多晶硅淀积形成沟槽多晶硅栅层211；
进行背面工艺，通过背面减薄工艺将所述低掺杂高阻晶圆的厚度减薄至预设厚度；在所述低掺杂高阻晶圆的背面进行第二导电类型离子注入并进行激光退火，形成第二导电类型的衬底24；
采用退火工艺使第一外延柱和第二外延柱相接触。
本公开还提供了一种超结半导体器件，如图3所示，该超结半导体器件可以包括晶圆20和超结型结构30。
在该实施方式中，超结型结构是由P型掺杂的柱状区域和N型掺杂的柱状区域组成，当P型掺杂区域的电荷数量同N型掺杂区域的电荷数量相当，达到平衡时，超结效果最佳，其耐压与导通电阻的平衡关系最优，故本实施方式中，该超结型结构内电荷平衡。
在本公开一种可能的实施方式中，如图3所示，超结型结构30形成于所述晶圆20中，包括至少一个第一导电类型的第一外延柱31及至少一个第二导电类型的第二外延柱32，所述第一外延柱31与所述第二外延柱32横向交替排布，如此就可以形成超结型结构30。
在本公开一种可能的实施方式中，如图3所示，所述第一外延柱31包括M段的第一外延层311，所述第二外延柱32包括M段的第二外延层321，所述第一导电类型与所述第二导电类型相反，一种主要是电子导电，另一种主要是空穴导电。示例的，在所述第一导电类型为N型(即参与导电的主要是电子)时，所述第二导电类型为P型(即参与导电的主要是空穴)；或者，所述第一导电类型为P型时，所述第二导电类型为N型。所述M为大于等于2的整数；可选的，所述M的取值范围可以是2至10，示例的，图3中M取值为4。
在本公开一种可能的实施方式中，任一第一外延柱的中心轴线处的电场强度在任意两个相邻第一外延层的交界处形成拐点，所述中心轴线通过所述第一外延柱横向截面的几何中心并沿纵向延伸，所述横向为平行于所述晶圆表面的方向，所述纵向为垂直于所述晶圆表面的方向。由于超结结构内电荷平衡，该任一第二外延柱的中心轴线处的电场强度在任意两个相邻第二外延层的交界处也会形成拐点。
示例的，如图7A所示，第二外延柱32的纵向中心轴线处的电场强度沿第二外延柱的深度方向即AA’方向的变化如图7A中的三角波折线702所示，而现有图1所示的超结半导体器件的有效掺杂浓度为一条直线，由于 沟槽角度影响，该图1所示的超结半导体器件的第一外延柱的中心轴线处的电场强度沿AA’方向的变化如图7A中的曲线703所示，多段不同掺杂浓度的第二外延层形成的第二外延柱32的纵向中心轴线处可以形成图7A所示的三角波电场分布，其在任意两个相邻第一外延层的交界处即a1、a2、a3和a4处都会形成拐点(这里需要说明的是，多段不同掺杂浓度的第一外延层形成的第一外延柱31的纵向中心轴线处沿该第一外延柱31的深度方向也形成三角波电场分布，形状与曲线702对称)。与现有产生抛物线电场分布的单次同一浓度外延柱形成的超结半导体器件的相比，本公开的超结半导体器件的击穿电压受外延填充浓度的波动影响较小，具有更大的工艺窗口。
本公开提供的超结半导体器件中第一外延柱和第二外延柱包括多段外延层，可以通过多次的沟槽填充来形成，在多次的沟槽填充过程中，深宽比越来越小，可以解决传统深沟槽单次外延填充产生的空洞问题；而且，在器件反向击穿时，第一外延柱的纵向中心轴线处的电场强度在任意两个相邻第一外延层的交界处形成拐点，可以形成三角波电场分布，与传统单次同一浓度外延层形成的抛物线电场分布相比，本公开的超结半导体器件的击穿电压受外延填充浓度的波动影响较小，具有更大的工艺窗口。
在一种可能的实施方式中，为了形成上述的三角波电场分布，所述第一外延柱包括M段掺杂浓度不同的第一外延层，所述第二外延柱包括M段掺杂浓度不同的第二外延层；所述M段第一外延层中第i段第一外延层的掺杂浓度N Ai与所述M段第二外延层中第i段第二外延层的掺杂浓度N Di满足预设条件使所述超结型结构达到电荷平衡。
在一种可能的实施方式中，在所述M为偶数的情况下，若i为奇数，则N Ai>N Di，若i为偶数，则N Ai<N Di；示例的，假设M为4，则，N A1>N D1，N A2<N D2，N A3>N D3，N A4<N D4。
示例的，如图7B所示，均匀掺杂的超结半导体器件的N型外延柱纵向中心轴线处的电场分布为开口向下的抛物线分布，而M＝2时，偶数段掺杂的超结半导体器件的N型外延柱纵向中心轴线处的电场强度在两段外延层的交界处即图7B中b1位置处形成拐点，整体的电场分布呈三角波分布，该三角波峰值位于两段外延层的交界处即图7B中b1位置处。如图7C所示，击穿电压的目标值为600V时，现有均匀掺杂的超结半导体器件，P型外延柱掺杂浓度可以在原定掺杂浓度的基础上在-3％到3％范围内变化时，击穿电压满足要求；而本公开偶数段掺杂的超结半导体器件，P型外延柱掺杂浓度可以在原定掺杂浓度的基础上在-8％到6％范围内变化时，击穿电压均满足要求，可以看出在击穿电压满足要求的情况下，本公开偶数段掺杂的超结半导体器件具有更大的器件工艺制造窗口。
在一种可能的实施方式中，在所述M为奇数的情况下，若i＝(M+1)/2，则N Ai＝N Di，若i为奇数且小于(M+1)/2，则N Ai>N Di，若i为偶数且小于(M+1)/2，则N Ai<N Di，若i为奇数且大于(M+1)/2，则N Ai<N Di，若i为偶数且大于(M+1)/2，则N Ai>N Di。假设M为5，则，N A1>N D1，N A2<N D2，N A3＝N D3，N A4>N D4，N A5<N D5。
示例的，如图7D所示，均匀掺杂的超结半导体器件的N型外延柱纵向中心轴线处的电场分布为开口向下的抛物线分布，而M＝3时，奇数段掺杂的超结半导体器件在N型外延柱纵向中心轴线处的电场强度在两段外延层的交界处即图7D中d1和d2位置处形成拐点，每相邻两段外延层所在区域的电场分布呈三角波分布，即在d1位置处交界的两段外延层所在区域的电场强度如图7D中d1左侧以及d1和d2之间的电场强度变化曲线，在d2位置处交界的两段外延层所在区域的电场强度如图7D中d2右侧以及d1和d2之间的电场强度变化曲线，这两部分电场强度变化曲线均是三角波曲线，该三角波峰值位于两段外延层的两两交界处即图7D中d1和d2位置处。这里需要说明的是，由于N A2＝N D2，故第二段外延层所在区域(即d1位置至d2位置之间区域)对应的纵向中心轴线处的电场强度分布较平缓，几乎是一条直线。如图7E所示，击穿电压的目标值为600V时，现有均匀掺杂的超结半导体器件，P型外延柱掺杂浓度可以在原定掺杂浓度的基础上在-3％到3％范围内变化时，击穿电压满足要求；而本公开奇数段掺杂的超结半导体器件，P型外延柱掺杂浓度可以在原定掺杂浓度的基础上在-10％到6％范围内变化时，击穿电压均满足要求，可以看出在击穿电压满足要求的情况下，本公开奇数段掺杂的超结半导体器件具有更大的器件工艺制造窗口。
在一种可能的实施方式中，所述第一外延柱与所述第二外延柱的宽度均相同。
在一种可能的实施方式中，所述第一外延柱或所述第二外延柱的宽度的取值范围为1～6um。
在一种可能的实施方式中，每段第一外延层和每段第二外延层的厚度均相同。
在一种可能的实施方式中，每段第一外延层和每段第二外延层的厚度的取值范围为5～10um。
在一种可能的实施方式中，为了满足电荷平衡条件，在所述第一外延柱与所述第二外延柱的宽度均相同，每段第一外延层和每段第二外延层的厚度均相同时，且掺杂浓度满足当N Ai不等于N Di时，|N A1-N D1|＝|N A2-N D2|＝……＝|N AM-N DM|<2e12/W；其中，W为所述第一外延柱或所述第二外延柱的宽度。
在一种可能的实施方式中，所述掺杂浓度N Ai和所述掺杂浓度N Di的取值范围包括1e15～1e17cm -3。该掺杂浓度用于表示掺杂的杂质原子在基质中的数量，单位为每立方厘米的掺杂原子个数。
在一种可能的实施方式中，如图8所示，所述晶圆包括：第二导电类型的半导体衬底21；第二导电类型的外延层22，沉积于所述半导体衬底21上，其中，所述超结型结构30形成于所述第二导电类型的外延层22中。
示例的，第二导电类型为N型时，该半导体衬底可以是N+衬底，N+表示高浓度N型掺杂，该外延层可以是N外延层。该衬底的材料可以是其它宽禁带半导体材料如GaN(氮化镓)、SiC(碳化硅)等。
在一种可能的实施方式中，如图9所示，所述晶圆20包括第二导电类型的低掺杂高阻晶圆23；所述超结半导体器件还包括：
超结场截止(Field Stop)层28，位于所述晶圆中的所述超结型结构下方；示例的，如图9所示，该第二导电类型为N型，则该超结场截止层可以是N型注入形成。当然，若该第二导电类型为P型，则该超结场截止层可以是P型注入形成，这里的注入指的是离子注入。
超结终端结构29，位于所述超结半导体器件边缘。
所述超结终端结构29可以包括场限环、场板、横向变掺杂(VLD)和结终端扩展(JTE)等终端结构，优选的，如图9所示，所述超结终端结构29可以包括场限环。
在一种可能的实施方式中，如图9所示，该第二导电类型的低掺杂高阻晶圆下方设置有衬底24，该衬底24可以是第二导电类型的衬底，或者，超结半导体器件为SJ-IGBT器件时，该衬底24可以是第一导电类型的衬底。
在一种可能的实施方式中，如图8和图9所示，该超结半导体器件还包括：第一导电类型体区25、栅氧层26及多晶硅栅层27。
如图8或图9所示，该第一导电类型体区25，形成于所述超结型结构表面处，可以通过在第一外延柱的表面进行第一导电类型离子的注入形成该第一导电类型体区25。该栅氧层26位于所述第二外延柱的上表面；该多晶硅栅层27位于所述栅氧层26的上表面，如此形成表面MIS结构。
在一种可能的实施方式中，图10示出根据本公开的实施例的超结半导体器件的结构示意图，如图10所示，该超结半导体器件还包括：第一导电类型体区25、沟槽栅氧层210及沟槽多晶硅栅层211。
该超结半导体器件可以是SGT器件，如图10所示，该SGT器件中，该第一导电类型体区25，形成于所述超结型结构表面处，可以通过在第一外延柱的表面进行第一导电类型离子的注入形成该第一导电类型体区25。沟槽栅氧层210呈凹槽状，位于所述第二外延柱的上端凹槽中；沟槽多晶硅栅层211，位于所述沟槽栅氧层210的凹槽内，如此形成沟槽MIS结构。
这里需要说明的是，本公开提供的超结半导体器件的制备方法可以参考上述实施方式中图2至图6所述的方法，通过多次的沟槽刻蚀和填充来形成，在多次的沟槽填充过程中，深宽比越来越小，可以解决传统深沟槽单次外延填充产生的空洞问题，且与多次外延工艺相比，成本较低，且采用深沟槽刻蚀工艺制作各外延柱，外延柱横向扩散更小，cell pitch可以做的更小，而且各外延柱掺杂浓度也更容易控制。
以上描述仅为本公开的较佳实施例以及对所运用技术原理的说明。本领域技术人员应当理解，本公开中所涉及的发明范围，并不限于上述技术特征的特定组合而成的技术方案，同时也应涵盖在不脱离所述发明构思的情况下，由上述技术特征或其等同特征进行任意组合而形成的其它技术方案。例如上述特征与本公开中公开的(但不限于)具有类似功能的技术特征进行互相替换而形成的技术方案。

Claims (51)

  1. 一种超结半导体器件的制备方法，其特征在于，包括：
    步骤1：通过深沟槽刻蚀工艺在晶圆的第一预定区域刻蚀得到至少一个Ai深沟槽，在所述Ai深沟槽中填充掺杂浓度为N Ai的第一外延层形成第i层第一导电类型的外延柱；
    步骤2：通过深沟槽刻蚀工艺在晶圆的第二预定区域刻蚀得到至少一个Di深沟槽，在所述Di深沟槽中填充掺杂浓度为N Di的第二外延层形成第i层第二导电类型的外延柱；所述Di深沟槽位于所述第i层第一导电类型的外延柱之间；
    循环进行上述步骤1和步骤2直至i＝M，得到第一外延柱和第二外延柱，所述第一外延柱包括M段第一外延层，所述第二外延柱包括M段第二外延层；所述i取值为1至M，所述M为大于等于2的整数，随着i的增大，所述Ai深沟槽的深度逐渐减小，所述Di深沟槽的深度也逐渐减小。
  2. 根据权利要求1所述的方法，其特征在于，所述方法还包括：
    在第i层第一导电类型的外延柱表面通过热氧化的方式形成氧化硅薄层；
    在第i层第二导电类型的外延柱表面通过热氧化的方式形成氧化硅薄层。
  3. 根据权利要求1所述的方法，其特征在于，所述通过深沟槽刻蚀工艺在晶圆的第一预定区域刻蚀得到至少一个Ai深沟槽，包括：
    在i大于等于2时，形成Ai深沟槽刻蚀所需的光阻，所述光阻的开口大于第i-1层第一导电类型的外延柱的开口；
    基于所述光阻，通过深沟槽刻蚀工艺在晶圆的第一预定区域刻蚀得到至少一个Ai深沟槽。
  4. 根据权利要求1所述的方法，其特征在于，所述方法还包括：
    采用退火工艺使所述第一外延柱和所述第二外延柱相接触。
  5. 根据权利要求1所述的方法，其特征在于，在所述晶圆包括半导体衬底和外延层时，所述方法包括：
    在第二导电类型的半导体衬底的上表面生长第二导电类型的外延层。
  6. 根据权利要求1所述的方法，其特征在于，所述晶圆为包括第二导电类型离子的低掺杂高阻晶圆，所述方法还包括：
    在刻蚀得到A1深沟槽之后，进行第二导电类型离子的沟槽注入，在所述A1深沟槽中填充掺杂浓度为N A1的第一外延层形成第1层第一导电类型的外延柱；刻蚀D1深沟槽之后，进行第二导电类型离子的沟槽注入，在所述D1深沟槽中填充掺杂浓度为N D1的第二外延层形成第1层第二导电类型的外延柱；A1和D1深沟槽中第二导电类型沟槽注入形成超结场截止层；
    刻蚀Ai深沟槽之后在所述Ai深沟槽中填充掺杂浓度为N Ai的第一外延层形成第i层第一导电类型的外延柱；刻蚀Di深沟槽之后在所述Di深沟槽中填充掺杂浓度为N Di的第二外延层形成第i层第二导电类型的外延柱；所述i取值为2至M，所述M为大于等于2的整数，形成超结型结构；
    在所述晶圆和超结型结构表面同时进行第一导电类型离子的注入，在所述第一外延柱处形成第一导电类型体区，在终端区形成场限环。
  7. 根据权利要求6所述的方法，其特征在于，所述方法还包括：
    通过背面减薄工艺将所述低掺杂高阻晶圆的厚度减薄至预设厚度；
    在所述低掺杂高阻晶圆的背面进行第二导电类型离子注入并进行激光退火，形成第二导电类型的衬底。
  8. 根据权利要求6所述的方法，其特征在于，所述方法还包括：
    通过背面减薄工艺将所述低掺杂高阻晶圆的厚度减薄至预设厚度；
    在所述低掺杂高阻晶圆的背面进行第一导电类型离子注入并进行激光退火，形成第一导电类型的衬底。
  9. 根据权利要求5至8任一项所述的方法，其特征在于，所述方法还包括：
    在所述第一外延柱处形成第一导电类型体区，在所述第二外延柱表面形成栅氧层和多晶硅栅层。
  10. 根据权利要求6至8任一项所述的方法，其特征在于，所述方法还包括：
    在所述第一外延柱处形成第一导电类型体区；
    在所述第二外延柱的上端进行沟槽刻蚀并热氧化形成沟槽状的沟槽栅氧化层，然后进行多晶硅淀积形成沟 槽多晶硅栅层。
  11. 根据权利要求1所述的方法，其特征在于，相邻的Ai深沟槽和Di深沟槽之间的间隙的取值范围包括大于0小于等于0.05um。
  12. 根据权利要求1所述的方法，其特征在于，
    任一第一外延柱的中心轴线处的电场强度在任意两个相邻第一外延层的交界处形成拐点，所述中心轴线通过所述第一外延柱横向截面的几何中心并沿纵向延伸，所述横向为平行于所述晶圆表面的方向，所述纵向为垂直于所述晶圆表面的方向。
  13. 根据权利要求12所述的方法，其特征在于，
    所述第一外延柱包括M段掺杂浓度不同的第一外延层，所述第二外延柱包括M段掺杂浓度不同的第二外延层；M段第一外延层中第i段第一外延层的掺杂浓度N Ai与M段第二外延层中第i段第二外延层的掺杂浓度N Di满足预设条件使超结型结构达到电荷平衡。
  14. 根据权利要求13所述的方法，其特征在于，在所述M为偶数的情况下，若i为奇数，则N Ai>N Di，若i为偶数，则N Ai<N Di。
  15. 根据权利要求13所述的方法，其特征在于，在所述M为奇数的情况下，若i＝(M+1)/2，则N Ai＝N Di，若i为奇数且小于(M+1)/2，则N Ai>N Di，若i为偶数且小于(M+1)/2，则N Ai<N Di，若i为奇数且大于(M+1)/2，则N Ai<N Di，若i为偶数且大于(M+1)/2，则N Ai>N Di。
  16. 根据权利要求14或15所述的方法，其特征在于，
    所述第一外延柱与所述第二外延柱的宽度均相同。
  17. 根据权利要求1所述的方法，其特征在于，
    所述第一外延柱或所述第二外延柱的宽度的取值范围为1～6um。
  18. 根据权利要求16所述的方法，其特征在于，
    每段第一外延层和每段第二外延层的厚度均相同。
  19. 根据权利要求1所述的方法，其特征在于，每段第一外延层和每段第二外延层的厚度的取值范围为5～10um。
  20. 根据权利要求18所述的方法，其特征在于，当N Ai不等于N Di时，|N A1-N D1|＝|N A2-N D2|＝……＝|N AM-N DM|<2e12/W；其中，W为所述第一外延柱或所述第二外延柱的宽度。
  21. 根据权利要求1所述的方法，其特征在于，所述M的取值范围为2～10。
  22. 根据权利要求1所述的方法，其特征在于，
    所述第一导电类型为N型，所述第二导电类型为P型；
    或者，所述第一导电类型为P型，所述第二导电类型为N型。
  23. 根据权利要求1所述的方法，其特征在于，掺杂浓度N Ai和掺杂浓度N Di的取值范围分别为1e15～1e17cm -3。
  24. 一种超结半导体器件，其特征在于，包括应用权利要求1至23中任一项权利要求所述的方法制作的超结半导体器件，所述超结半导体器件包括：
    晶圆；
    超结型结构，形成于所述晶圆中，包括至少一个第一导电类型的第一外延柱及至少一个第二导电类型的第二外延柱，所述第一外延柱与所述第二外延柱横向交替排布，所述第一外延柱包括M段第一外延层，所述第二外延柱包括M段第二外延层，所述第一导电类型与所述第二导电类型相反，所述M为大于等于2的整数，所述横向为平行于晶圆表面的方向。
  25. 一种超结半导体器件，其特征在于，包括：
    晶圆；
    超结型结构，形成于所述晶圆中，包括至少一个第一导电类型的第一外延柱及至少一个第二导电类型的第二外延柱，所述第一外延柱与所述第二外延柱横向交替排布，所述第一外延柱包括M段掺杂浓度不同的第一外延层，所述第二外延柱包括M段掺杂浓度不同的第二外延层，所述第一导电类型与所述第二导电类型相反，所述M为大于等于2的整数，所述横向为平行于晶圆表面的方向；
    其中，M段第一外延层中第i段第一外延层的掺杂浓度N Ai与M段第二外延层中第i段第二外延层的掺杂浓度N Di满足预设条件使所述超结型结构达到电荷平衡；在所述M为偶数的情况下，若i为奇数，则N Ai>N Di，若i为偶数，则N Ai<N Di。
  26. 根据权利要求25所述的超结半导体器件，其特征在于，
    在所述M为奇数的情况下，若i＝(M+1)/2，则N Ai＝N Di，若i为奇数且小于(M+1)/2，则N Ai>N Di，若i为偶数且小于(M+1)/2，则N Ai<N Di，若i为奇数且大于(M+1)/2，则N Ai<N Di，若i为偶数且大于(M+1)/2，则N Ai>N Di。
  27. 根据权利要求25或26所述的超结半导体器件，其特征在于，
    所述第一外延柱与所述第二外延柱的宽度均相同。
  28. 根据权利要求27所述的超结半导体器件，其特征在于，
    每段第一外延层和每段第二外延层的厚度均相同。
  29. 根据权利要求28所述的超结半导体器件，其特征在于，当N Ai不等于N Di时，|N A1-N D1|＝|N A2-N D2|＝……＝|N AM-N DM|<2e12/W；其中，W为所述第一外延柱或所述第二外延柱的宽度。
  30. 根据权利要求25或26所述的超结半导体器件，其特征在于，
    所述第一外延柱或所述第二外延柱的宽度的取值范围为1～6um。
  31. 根据权利要求25或26所述的超结半导体器件，其特征在于，每段第一外延层和每段第二外延层的厚度的取值范围为5～10um。
  32. 根据权利要求25或26所述的超结半导体器件，其特征在于，所述M的取值范围为2～10。
  33. 根据权利要求26所述的超结半导体器件，其特征在于，所述晶圆包括：
    第二导电类型的半导体衬底；
    第二导电类型的外延层，沉积于所述半导体衬底上，其中，所述超结型结构形成于所述第二导电类型的外延层中。
  34. 根据权利要求26所述的超结半导体器件，其特征在于，所述晶圆包括第二导电类型的低掺杂高阻晶圆；所述超结半导体器件还包括：
    超结场截止层，位于所述晶圆中的所述超结型结构下方；
    超结终端结构，位于所述超结半导体器件边缘。
  35. 根据权利要求34所述的超结半导体器件，其特征在于，所述超结终端结构包括场限环。
  36. 根据权利要求34所述的超结半导体器件，其特征在于，还包括：
    第二导电类型的衬底，位于所述第二导电类型的低掺杂高阻晶圆下方。
  37. 根据权利要求34所述的超结半导体器件，其特征在于，还包括：
    第一导电类型的衬底，位于所述第二导电类型的低掺杂高阻晶圆下方。
  38. 根据权利要求33至37任一项所述的超结半导体器件，其特征在于，还包括：
    第一导电类型体区，形成于所述超结型结构表面；
    栅氧层，位于所述第二外延柱的上表面；
    多晶硅栅层，位于所述栅氧层的上表面。
  39. 根据权利要求34至37任一项所述的超结半导体器件，其特征在于，还包括：
    第一导电类型体区，形成于所述超结型结构表面；
    沟槽栅氧层，呈凹槽状，位于所述第二外延柱的上端凹槽中；
    沟槽多晶硅栅层，位于所述沟槽栅氧层的凹槽内。
  40. 根据权利要求25或26所述的超结半导体器件，其特征在于，
    所述第一导电类型为N型，所述第二导电类型为P型；
    或者，所述第一导电类型为P型，所述第二导电类型为N型。
  41. 根据权利要求25或26所述的超结半导体器件，其特征在于，掺杂浓度N Ai和掺杂浓度N Di的取值范围分别为1e15～1e17cm -3。
  42. 一种超结半导体器件，其特征在于，包括：
    晶圆；
    超结型结构，形成于所述晶圆中，包括至少一个第一导电类型的第一外延柱及至少一个第二导电类型的第二外延柱，所述第一外延柱与所述第二外延柱横向交替排布，所述第一外延柱包括M段第一外延层，所述第二外延柱包括与所述第一外延层对应的M段第二外延层，所述第一导电类型与所述第二导电类型相反，所述M为大于等于2的整数；
    其中，任一第一外延柱的中心轴线处的电场强度在任意两个相邻第一外延层的交界处形成拐点，所述中心轴线通过所述第一外延柱横向截面的几何中心并沿纵向延伸，所述横向为平行于所述晶圆表面的方向，所述纵向为垂直于所述晶圆表面的方向。
  43. 根据权利要求42所述的超结半导体器件，其特征在于，
    所述第一外延柱包括M段掺杂浓度不同的第一外延层，所述第二外延柱包括M段掺杂浓度不同的第二外延层；所述M段第一外延层中第i段第一外延层的掺杂浓度N Ai与所述M段第二外延层中第i段第二外延层的掺杂浓度N Di满足预设条件使所述超结型结构达到电荷平衡。
  44. 根据权利要求43所述的超结半导体器件，其特征在于，在所述M为偶数的情况下，若i为奇数，则N Ai>N Di，若i为偶数，则N Ai<N Di。
  45. 根据权利要求43所述的超结半导体器件，其特征在于，在所述M为奇数的情况下，若i＝(M+1)/2，则N Ai＝N Di，若i为奇数且小于(M+1)/2，则N Ai>N Di，若i为偶数且小于(M+1)/2，则N Ai<N Di，若i为奇数且大于(M+1)/2，则N Ai<N Di，若i为偶数且大于(M+1)/2，则N Ai>N Di。
  46. 根据权利要求44或45所述的超结半导体器件，其特征在于，
    所述第一外延柱与所述第二外延柱的宽度均相同。
  47. 根据权利要求46所述的超结半导体器件，其特征在于，
    每段第一外延层和每段第二外延层的厚度均相同。
  48. 根据权利要求47所述的超结半导体器件，其特征在于，当N Ai不等于N Di时，|N A1-N D1|＝|N A2-N D2|＝……＝|N AM-N DM|<2e12/W；其中，W为所述第一外延柱或所述第二外延柱的宽度。
  49. 根据权利要求42所述的超结半导体器件，其特征在于，
    所述第一外延柱或所述第二外延柱的宽度的取值范围为1～6um。
  50. 根据权利要求42所述的超结半导体器件，其特征在于，每段第一外延层和每段第二外延层的厚度的取值范围为5～10um。
  51. 根据权利要求43所述的超结半导体器件，其特征在于，所述掺杂浓度N Ai和所述掺杂浓度N Di的取值范围分别为1e15～1e17cm -3。
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