CN106229335A - 深沟槽填充方法 - Google Patents

深沟槽填充方法 Download PDF

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Publication number
CN106229335A
CN106229335A CN201610621874.8A CN201610621874A CN106229335A CN 106229335 A CN106229335 A CN 106229335A CN 201610621874 A CN201610621874 A CN 201610621874A CN 106229335 A CN106229335 A CN 106229335A
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extension
deep trench
filling
filled
groove
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姚亮
王飞
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02595—Microstructure polycrystalline

Abstract

本发明公开了一种深沟槽填充方法，在深沟槽内，先用外延填充，外延填充至沟槽侧壁的外延在底部合拢之后，再利用非导电介质对沟槽内剩余空隙进行填充至填充满沟槽。本发明所述的深沟槽填充方法，外延填充在外延底部合拢后顶部合拢前停止，保持底部和顶部的外延体积相接近。由于填充外延内部的杂质量与体积成正比，所以本填充方法可以减小深沟槽底部和上部的杂质量差异，提升耗尽区的均匀性，使得在反向耗尽时沟槽各个深度的耗尽程度差异不大，进而提升耗尽区的耐压效率，提升产品的耐压能力。

Description

深沟槽填充方法
技术领域
本发明涉及半导体制造领域，特别是指一种深沟槽填充方法。
背景技术
现有的深沟槽超级结产品，应用深沟槽刻蚀加外延填充方法进行超级结产品的PN结构的加工。而深沟槽产品的外延填充速率慢，需要长时间的外延生长才能将沟槽完全填满，占用外延设备的产能，不利于大规模量产。
深沟槽加工的侧壁会有一定角度，如图1所示，沟槽的剖面呈倒梯形，沟槽口沿的宽度大于沟槽底部的宽度。填充完成如图2所示，外延填充后导致顶部和底部的PN体积比例不一致，即沿着深沟槽不同深度的PN耗尽区的状况发生变化，如果沟槽的中间部分部分是完全耗尽，则沟槽上部在耗尽时会剩余空穴，沟槽下部在耗尽时会剩余电子，降低耗尽区的耐压能力。
发明内容
本发明所要解决的技术问题是提供一种深沟槽填充方法，缩短深沟槽的填充时间，同时提升产品的耐压能力。
为解决上述问题，本发明所述的深沟槽填充方法，在深沟槽内，先用外延填充，外延填充至沟槽侧壁的外延在底部合拢之后，再利用非导电介质进行填充至填充满沟槽。
外延填充至沟槽侧壁的外延在底部合拢，填充时间为完全填充时间的30％～80％。
所述的非导电介质包含但不仅限于二氧化硅、非掺杂多晶硅。
所述的外延为P型外延或N型外延。
本发明所述的深沟槽填充方法，外延填充在外延底部合拢后顶部合拢前停止，保持底部和顶部的外延体积相接近。由于填充外延内部的杂质量与体积成正比，所以本方法可以减小深沟槽底部和顶部的杂质量差异，提升耗尽区的均匀性，使得在反向耗尽时沟槽各个深度的耗尽程度差异不大，进而提升耗尽区的耐压效率，提升产品的耐压能力。
同时由于引入了外延以外的材料进行深沟槽填充，降低了外延的填充时间，可以提升外延设备的加工能力，可以进一步降低产品成本。
附图说明
图1是深沟槽的形貌示意图。
图2是现有深沟槽填充示意图。
图3是本发明深沟槽填充示意图。
附图标记说明
1是衬底，2是外延，3是非导电介质。
具体实施方式
本发明所述的深沟槽填充方法，如图3所示，在衬底1中具有深沟槽，在深沟槽内，先用P型或N型的外延2填充，外延2填充至沟槽侧壁的外延在底部合拢之后、顶部合拢之前，再利用非导电介质如二氧化硅或者非掺杂多晶硅等对沟槽内剩余空间继续进行填充至填充满沟槽。
一般填充时间为完全填充时间的30％～80％。
在外延填充时，由于外延生长是沿着深沟槽侧壁等速生长，在外延底部合拢到顶部合拢期间停止外延生长，外延的浓度通过实际填充的外延厚度进行计算。参考：
N外延浓度×N外延宽度＝P外延浓度×P外延生长宽度
来计算P型外延所需要浓度。深沟槽中间的空隙可以利用其它的不导电介质膜进行填充，比如二氧化硅或者不掺杂的多晶硅等。
通过上述深沟槽填充方法，外延填充在外延底部合拢后顶部合拢前停止，保持底部和顶部的外延体积相接近，可以减小深沟槽底部和顶部的杂质量差异，提升耗尽区的均匀性，使得在反向耗尽时沟槽各个深度的耗尽程度差异不大，进而提升耗尽区的耐压效率，提升产品的耐压能力。
以上仅为本发明的优选实施例，并不用于限定本发明。对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (4)

1.一种深沟槽外填充方法，其特征在于：在深沟槽内，先用外延填充，外延填充至沟槽侧壁的外延在底部合拢之后，再利用非导电介质进行填充至填充满沟槽。
2.如权利要求1所述的深沟槽外填充方法，其特征在于：外延填充至沟槽侧壁的外延在底部合拢，填充时间为完全填充时间的30％～80％。
3.如权利要求1所述的深沟槽外填充方法，其特征在于：所述的非导电介质包含但不仅限于二氧化硅、非掺杂多晶硅。
4.如权利要求1或2所述的深沟槽外填充方法，其特征在于：所述的外延为P型外延或N型外延。
CN201610621874.8A 2016-08-01 2016-08-01 深沟槽填充方法 Pending CN106229335A (zh)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107275205A (zh) * 2017-06-30 2017-10-20 上海华虹宏力半导体制造有限公司 超级结的沟槽填充方法
CN107799581A (zh) * 2017-09-19 2018-03-13 上海华虹宏力半导体制造有限公司 沟槽型超级结及其制造方法
CN114914191A (zh) * 2021-02-09 2022-08-16 格科半导体(上海)有限公司 深沟槽中外延生长的方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102386212A (zh) * 2010-08-31 2012-03-21 上海华虹Nec电子有限公司 半导体器件结构及其制作方法
CN104599966A (zh) * 2010-03-05 2015-05-06 万国半导体股份有限公司 带有沟槽-氧化物-纳米管超级结的器件结构及制备方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104599966A (zh) * 2010-03-05 2015-05-06 万国半导体股份有限公司 带有沟槽-氧化物-纳米管超级结的器件结构及制备方法
CN102386212A (zh) * 2010-08-31 2012-03-21 上海华虹Nec电子有限公司 半导体器件结构及其制作方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107275205A (zh) * 2017-06-30 2017-10-20 上海华虹宏力半导体制造有限公司 超级结的沟槽填充方法
CN107275205B (zh) * 2017-06-30 2019-10-11 上海华虹宏力半导体制造有限公司 超级结的沟槽填充方法
CN107799581A (zh) * 2017-09-19 2018-03-13 上海华虹宏力半导体制造有限公司 沟槽型超级结及其制造方法
CN114914191A (zh) * 2021-02-09 2022-08-16 格科半导体(上海)有限公司 深沟槽中外延生长的方法

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Application publication date: 20161214