CN102194880B - 带有沟槽-氧化物-纳米管超级结的器件结构及制备方法 - Google Patents

带有沟槽-氧化物-纳米管超级结的器件结构及制备方法 Download PDF

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CN102194880B
CN102194880B CN201110054042.XA CN201110054042A CN102194880B CN 102194880 B CN102194880 B CN 102194880B CN 201110054042 A CN201110054042 A CN 201110054042A CN 102194880 B CN102194880 B CN 102194880B
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groove
epitaxial loayer
device architecture
layer
semiconductor layer
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CN102194880A (zh
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哈姆扎·依玛兹
马督儿·博德
李亦衡
管灵鹏
王晓彬
陈军
安荷·叭剌
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Alpha and Omega Semiconductor Cayman Ltd
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Alpha and Omega Semiconductor Inc
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Priority claimed from US12/661,004 external-priority patent/US8390058B2/en
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Priority to CN201410765921.7A priority Critical patent/CN104538444B/zh
Priority to CN201410766372.5A priority patent/CN104599966B/zh
Priority to CN201410765884.XA priority patent/CN104377238B/zh
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Abstract

本发明带有沟槽-氧化物-纳米管超级结的器件结构及制备方法提出了一种沉积在第一导电类型的半导体衬底上的半导体功率器件。该半导体衬底承载着一个第二导电类型的外延层，其中半导体功率器件就位于超级结结构上。该超级结结构包含从外延层中的顶面上打开的多个沟槽；其中每个沟槽的沟槽侧壁都用第一导电类型的第一外延层覆盖，以便中和第二导电类型的外延层的电荷。第二外延层可以生长在第一外延层上方。每个沟槽都在一个剩余的沟槽缝隙空间内，用非掺杂的电介质材料填充。每个沟槽侧壁都带有一个倾斜角，以构成会聚的U-型沟槽。

Description

带有沟槽-氧化物-纳米管超级结的器件结构及制备方法
技术领域
本发明主要涉及半导体功率器件，更确切地说，本发明涉及带有沟槽侧壁的沟槽纳米管的结构和制备方法，其中用掺杂的外延层覆盖沟槽侧壁，然后用绝缘材料填充沟槽侧壁，以便用简化的制备工艺灵活地制备可测量的电荷平衡的半导体功率器件，同时获得高击穿电压以及很低的电阻。
背景技术
尽管关于带有垂直超级结结构的半导体器件，为了改善其电学特性，已有许多专利信息以及公开的技术文件，但是在超级结半导体器件的设计和制备的相关领域，仍然存在许多技术难题与制备局限。更确切地说，最常见的超级结器件包含金属氧化物半导体场效应管(MOSFET)和绝缘栅双极晶体管，关于这些器件，已有许多已公开的专利信息，包含美国专利5,438,215、5,216,275、4,754,310、6,828,631。藤平(Fujihira)在《半导体超级结器件理论》(日本应用物理快报，36卷，1997年10月，6254-6262页)一书中，提出了垂直超级结器件的结构。更确切地说，藤平发表的论文中的图2表示了一种垂直沟槽MOSFET超级结器件，在此引用为图1(1A)。藤平还在美国专利6,097,063中提出了一种具有漂流区的垂直半导体器件，当器件处于闭合模式时，漂流区中有漂流电流流过，当器件处于断开模式时，漂流区中的漂流电流耗尽。所形成的漂流区结构是具有多个第一导电类型的分立的漂流区，以及多个第二导电类型的分隔区，其中每个分隔区都位于分别相邻的漂流区中，并联形成p-n结。美国专利6,608,350提出了一种垂直超级结器件，带有介质材料层填充在沟槽中，美国专利5,981,996如图2(1B)所示，提出了一种垂直沟槽MISFET器件。
然而，在这些专利技术和公开内容中所述的超级结器件的结构和工作性能中，仍然存在诸多技术局限，从而限制了这些器件在实际应用中的有效性。传统超级结器件的难题与局限包含深沟槽的填充、形成在沟槽中的纳米管的尺寸限制、保持终止区附近的台面区域处电荷平衡、超级结器件的非箝位感应开关(UIS)能力不足、超级结功率器件的振荡问题、由于外延生长速度缓慢造成超级结器件的高制造成本、超级结结构中的N和P杂质在高温下相互扩散、在同一芯片上难以集成不同的器件、以及高压应用时的终止区域很大等相关技术问题。
因此，在功率半导体器件的设计和制备领域中，有必要提出形成功率器件的新颖的器件结构和制备方法，从而解决上述困难与局限。
发明内容
因此，本发明的一个方面是提出一种新型的、改良的器件结构和制备方法，通过在沟槽侧壁和底部，生长一个薄的N型掺杂外延层(例如砷外延层)，没有完全填充或部分填充沟槽，然后在第一外延层上方生长第二外延层，并用非掺杂的介质材料填充剩余的构成缝隙，从而解决用外延层填充深沟槽时，传统的制备方法中经常遇到的问题。第二外延层可以充分填充其余沟槽缝隙的底部，从而可以在缝隙中更加方便地沉积介质材料。
本发明的另一方面在于，提出了一种带有超级结结构的新型的、改良的器件结构和制备方法，利用电荷平衡原理，通过纳米管结构，降低Rds，并且元件间距很小，以获得6微米间距的600V MOSFET，其导通电阻率小于9豪欧/cm2。这就解决了用于高压器件时对于高Rds的限制。
本发明的另一方面在于，提出了一种带有超级结结构的新型的、改良的器件结构和制备方法，该结构利用较大的间距以及狭窄的N-外延层，并利用在每个有源元件叉指末端具有较大半径的单一元件，在有源区域台面结构的末端保持电荷平衡。
本发明的另一方面在于，提出了一种带有超级结结构的新型的、改良的器件结构和制备方法，在一个带有掺杂浓度分级的外延层中制备超级结结构，例如在一个N+衬底上用三个步骤形成P外延层，迫使击穿发生在漂流区较低的部分中，从而改善超级结MOSEFT器件的UIS性能。
本发明的另一方面在于，提出了一种带有超级结结构的新型的、改良的器件结构和制备方法，厚介质区位于栅电极以下，以降低栅-漏电容Crss，从而解决超级结功率器件的振荡问题。
本发明的另一方面在于，提出了一种带有超级结结构的新型的、改良的器件结构和制备方法，通过生长一个薄的单一层N-外延层(0.1-1.0微米的厚度范围)，部分填充沟槽，并用电介质/氧化物填充剩余的深沟槽，从而解决由于深沟槽中外延生长缓慢，而造成的超级结器件的高制造成本问题。此外，轻掺杂的N型外延层可以在N-外延层之后生长，在用电介质/氧化物填充剩余的深沟槽之前，充分填充沟槽，这有利于更加方便地用氧化物填充沟槽。
本发明的另一方面在于，提出了一种带有超级结结构的新型的、改良的器件结构和制备方法，在较宽的P-型区域附近形成一个非常薄的N-型纳米管层，并与较宽的P-型区域电荷平衡；作为示例，N-型纳米管层比较宽的P-型区域宽三倍，导致硼的掺杂浓度比N-型纳米管区域中的N-型掺杂浓度低三倍。因此，只能允许受限的硼扩散进入N型纳米管区，从而补偿多余的砷电荷。N-型纳米管区域的重N型掺杂(例如砷或锑)，不会过分移动，从而不会大量扩散到P-型区。这就解决了在高温下，N和P杂质相互扩散所带来的问题。
本发明的另一方面在于，提出了一种带有超级结结构的新型的、改良的器件结构和制备方法，增大第一器件分界线处的沟槽区域宽度，例如对于一个MOSFET器件以及一个第二器件(例如肖特基二极管)，是用介质材料充分填充大沟槽区域——与有源器件不同，有源器件是用硅充分填充，再用氧化硅(氧化物或SiO2)填充剩余部分。因此，不同的器件可以更加方便地集成在同一个硅芯片上。
本发明的另一方面在于，提出了一种带有超级结结构的新型的、改良的器件结构和制备方法，将一个肖特基二极管与一个受控的注入P-N二极管集成在一起，从而降低了二极管的恢复电荷，减少高压器件的漏电流。
本发明的另一方面在于，提出了一种带有超级结结构的新型的、改良的器件结构和制备方法，将一个高压(HV)肖特基二极管与一个受控的注入P-N二极管集成在同一个硅晶片上，作为一个绝缘栅双极晶体管(IGBT)，其中IGBT的背面带有发射极(对于N-通道器件而言为P-型)植入。从而解决了IGBT结构缺少嵌入式二极管的难题。
本发明的另一方面在于，提出了一种新型的、改良的终止结构，制备宽介质沟槽的方法是首先通过形成一个SiO2网络，然后刻蚀掉SiO2网络内的硅台面结构，并用自旋式玻璃、HDP或聚酰亚胺，填充刚刻蚀掉的区域，在金属化之前还是之后进行，取决于所选的介质材料的类型。由于制备所受的限制，用传统的刻蚀和填充方法很难制备又宽又深的介质沟槽，但是本发明的两步方法可以利用标准的制备工艺，形成一个高质量的又宽又深的介质填充沟槽。对于一个600V器件的每一侧面而言，利用终止区的这种宽氧化物沟槽，一个普通的6-10密耳宽的HV终止区，可以减至2密耳。对于低电流产品，这种HV终止区增大了晶片尺寸，对大晶片增大15％左右(在一个TO-220填充的能力中)，对较小的晶片增大50％左右(对于HV终止，为53×53密耳^2晶片，8密耳/侧)。因此，由于减小了适合高压应用器件的终止区，从而解决了高压MOSFET功率器件，需要大终止区的难题。
阅读以下详细说明并参照附图之后，本发明的这些和其他的特点和优势，对于本领域的技术人员而言，无疑将显而易见。
附图说明
图1表示现有一种垂直超级结功率器件的传统结构的剖面透视图。
图2表示现有一种垂直超级结功率器件的传统结构的剖面图。
图3表示本发明所述的带有沟槽纳米管超级结结构的MOSFET器件的剖面图。
图4-图6表示本发明所述的带有交替沟槽纳米管超级结结构的MOSFET器件的剖面图。
图7表示本发明所述的带有沟槽纳米管超级结结构的N-通道绝缘栅双极晶体管(IGBT)器件的剖面图。
图8和图9分别表示本发明所述的带有沟槽纳米管超级结结构的电荷注入控制电阻器的剖面图以及等效电路图。
图10为图8所示结构的俯视图。
图11为图8所示结构的另一个剖面图。
图12表示图3所示的MOSFET器件的另一个实施例的剖面图，该MOSFET器件带有沟槽纳米管超级结结构以及三个不同掺杂浓度的外延层。
图13和图14表示两种MOSFET器件的两个局部透视图，这两种MOSFET器件都带有本发明所述的沟槽纳米管超级结结构。
图15表示类似于图14所示的MOSFET器件的俯视图。
图16和图17表示本发明所述的功率器件的封闭元件结构的俯视图。
图18表示本发明所述的MOSFET器件的剖面图，该MOSFET器件带有沟槽纳米管超级结结构以及专门配置的终止区。
图19至图31为一系列表示图3所示的MOSFET器件的制备过程的剖面图。
图32至图41为一系列表示配置本发明所述的终止区的制备过程的剖面图。
图42为本发明所述的平面终止区的俯视图；图43和图44为其剖面图；图45表示整个终止区上夹断步骤的电压分布。
图46和图47表示带有肖特基器件的IGBT器件的剖面图。
具体实施方式
图3表示本发明所述的沟槽纳米管金属氧化物半导体场效应管(MOSFET)器件100的剖面图。MOSFET元件形成在一个P-型外延层110中，P-型外延层110位于N+衬底105上。多个沟槽纳米管115和多个沟槽形成在外延层110中。沟槽侧壁带有微小的倾斜角，以形成一个锥形沟槽。作为示例，侧壁可以略微倾斜87-89度。每个沟槽侧壁都被N+外延层115覆盖。另一个轻掺杂的P-外延层116生长在N+外延层115上方。由于剩余的沟槽宽度和沟槽的倾斜角，P-外延层116的侧壁朝着底部会合，并充分填充沟槽的底部。用氧化硅120等电介质填充沟槽剩余的中心部分。MOSFET器件100还包含形成在沟槽顶部的沟槽栅极130，沟槽栅极130被栅极氧化层125填充包围着，并通过氧化硅层120与下面的N+侧壁层115绝缘。MOSFET器件100还包含包围着沟槽栅极130的本体区。每个本体区都含有一个P-本体区135和一个重掺杂的P+本体接触区140。MOSFET器件100还包含N+源极区145，N+源极区145沉积在MOSFET器件100的顶面附近，被P本体区140和135包围着。MOSFET器件100还包含一个阻挡金属层150，以接触源极区145和P+本体接触区140，MOSFET器件100也可以连接到源极电极155上。栅极电极160也用于在沟槽栅极130上加载栅极电压。当打开MOSFET器件100时，会在本体区135中邻近沟槽栅极130的地方形成一个通道(图中没有表示出)。
P-外延层110和带有侧壁、被N外延层115和轻掺杂的N-外延层116覆盖的沟槽，构成纳米管结构，以使MOSFET器件获得电荷平衡。本发明提出了一种电荷平衡的高压器件，该器件可以高效地制备。N侧壁层115，即纳米管，同P外延层110的邻近部分达到电荷平衡，使得N侧壁层115构成MOSFET的漂流区，该漂流区在断开模式下耗尽。P-外延层116还包含一个位于本体区135下面的N-型植入区117，以便将通道连接到N侧壁层115中的漂流区上。通过从另一侧耗尽N外延层，以及允许更高的电荷储存在N外延层115中，P-外延层116可以提供进一步的电荷平衡，并改善Rdson。例如，如果再增加25％的P-型电荷储存在P-外延层116中，那么就可以再增加25％的N-型电荷储存在N-外延层115中，从而使Rdson降低25％。P-侧壁层116也充分填充深沟槽的底部。这会使沟槽中剩余缝隙的纵横比较小，可以轻松地用氧化填充物120填充这些缝隙，从而避免了形成空洞等制备问题。氧化填充物120使沟槽栅极130与漏极电势绝缘，并降低了栅-漏电容。
N-外延层115大约1微米宽，在相邻的N-外延层115之间的P外延层110大约6微米宽，这仅作为示例，不作为局限。可以认为P外延层110具有两半，每一半的宽度都为3微米，并与N外延层115保持电荷平衡。N外延层115和P外延层110电荷平衡的那部分，具有的电荷浓度约为1E12cm-2，因此P外延层110的掺杂浓度为3.33E15cm-3，N外延层115的掺杂浓度为1E16cm-3。此外，1微米宽的P外延层116所具有的电荷浓度为0.25E12cm-2，掺杂浓度为2.5E15cm-3，N外延层115的掺杂浓度可以升高到1.25E16cm-3，从而降低Rdson。
图4表示本发明所述的沟槽纳米管(MOSFET)器件100-1的一个可选实施例。MOSFET器件100-1除了轻掺杂的N--外延层116-1(而不是图3所示的P-外延层116)生长在N+外延层115上以外，其他都与图3所示的MOSFET器件100类似。因此，MOSFET器件100-1中并不需要N-型植入区117。轻掺杂的N--外延层116-1也充分填充沟槽的底部，以便于接下来形成氧化填充物120。由于形成N外延层115之后，可以利用同一个外延生长室制备N--外延层116-1，而要生长P外延层116的话，就需要将晶片移至另一个生长室，因此使用N--外延层116-1比P外延层116更易于制备。这也提高了器件的产量。在一个可选实施例中，N外延层116-1可以用一个本征或轻掺杂的P--层代替。
图5表示本发明所述的沟槽纳米管(MOSFET)器件100-2的一个可选实施例。MOSFET器件100-2与图3所示的MOSFET器件100基本类似，只是沟槽较宽，使得形成在N+外延层115上方的P外延层116-2仅仅衬在沟槽内，并不能充分填充沟槽底部。相反，氧化填充物120-2填充了沟槽底部的绝大部分。
图6表示本发明所述的沟槽纳米管(MOSFET)器件100-3的一个可选实施例。MOSFET器件100-3与图3所示的MOSFET器件100基本类似，只是P外延层116-3除了在氧化填充物120-3下方的底部较厚以外，在大多数区域中P外延层116-3都很薄，以至于在这些区域中N+外延层115-3都与它反向掺杂。可以选择的是，如果在生长P外延层116-3之后实施各向同性的轻刻蚀，那么就可以形成这种结构。各向同性的刻蚀可以除去P外延层116-3的边缘部分，留下P外延层116-3的底部。
图7表示本发明所述的带有沟槽纳米管结构的N-通道绝缘栅双极晶体管(IGBT)器件101的剖面图。该IGBT器件101形成在P-型外延层110中，P-型外延层110位于P衬底层105-1上，作为IGBT的集电极，N-通道截止层108沉积在P-外延层110和P+IGBT发射层105-1之间。IGBT器件101与图3所示的MOSFET器件的结构类似，也包含形成在外延层110中的多个沟槽纳米管，沟槽纳米管中含有多个沟槽。所形成的沟槽带有侧壁，侧壁具有微小的倾斜角，并且每个沟槽侧壁都覆盖有一个N纳米管层115、一个P-外延层116以及用氧化硅120填充的沟槽中心部分。IGBT器件101还包含沟槽栅极130，沟槽栅极130形成在沟槽顶部，被栅极氧化层125填充包围着，并通过氧化硅层120与N+侧壁层115绝缘。IGBT器件101还包含沟槽栅极周围的本体区。每个本体区都含有一个沉积在重掺杂的P+本体接触区140下面的P-本体区135。IGBT器件101还包含N+源极区145，N+源极区145沉积在顶面附近，并被P本体区135和140包围着。IGBT器件101还包含一个阻挡金属层150，阻挡金属层150将源极区145和本体区140连接到发射极电极155上。再形成一个栅极电极160，以便在沟槽栅极130上加载栅极电压。
P-外延层110和所形成的带有被N外延层115覆盖的侧壁的沟槽，构成纳米管结构，以形成IGBT器件中电荷平衡的漂流区。
图8表示本发明所述的带有沟槽纳米管结构的电荷注入控制二极管的剖面图。图9用图8中的肖特基二极管162以及PN结二极管161，表示电荷注入可调电阻器R1 163的等效电路的电路图。电荷注入可调电阻器R1 163与PN结二极管161串联，PN结二极管161与肖特基二极管162并联。电阻器163可以集成到器件中，例如作为一个金属和多晶硅电阻器，或者也可以外接到器件中，使用户可以选择所需的电阻值。P-型外延层110位于N/N+衬底层105上，作为PN结二极管和肖特基二极管的阴极。到P外延层110的欧姆接触形成在第三维中，一直到P+区176。肖特基二极管和PN结二极管都位于P外延层110上，所形成的P外延层110带有多个沟槽纳米管，沟槽纳米管含有多个沟槽。所形成的沟槽带有侧壁，侧壁具有微小的倾斜角，并且每个沟槽侧壁都覆盖有N纳米管层115、P-外延层116以及用氧化硅120填充的沟槽中心部分。较宽的沟槽可以形成在比其他的氧化填充物120更宽更深的氧化填充物121上。当它们形成在同一半导体晶片上时，这样有助于分离不同的器件。肖特基二极管含有一个N-区165，肖特基接触金属170覆盖着N区165的顶面。N区165沉积在纳米管115上方，靠近氧化层120，并与P外延层110和N掺杂区115相接触。PN结二极管含有一个P/P+区175/176，欧姆接触金属层180作为一个调制栅极，覆盖在P/P+区175/176的顶面上。P区175与P外延层110和纳米管层115相接触。电阻器R1 163控制P-N结二极管中的注入能级，是通过降低整个PN结二极管上的电压(通过电压VR1＝I二极管*R1)，致使PN结二极管上储存的电荷量减少，反向恢复得到增强。电阻器R1的值较大，会使反向恢复增强，并且传导率调制降低带来更少的正向传导。电阻器R1的值较小会带来相反的效果。将肖特基二极管与PN结二极管并联，会进一步减少PN结二极管中储存的电荷量。改变电阻器R1 163的大小，可以控制PN结二极管161中储存的电荷量以及二极管的性能。PN结二极管降低了高压(HV)肖特基二极管的漏电流，优化了复合器件的正向电压降Vf。
如图10以及图11的剖面图所示，肖特基二极管(用N区165表示)以及PN结二极管(用P/P+区175/176表示)位于外延层110的同一条纹上。
图12表示类似于图3所示的MOSFET器件，带有沟槽纳米管结构的MOSFET器件102的侧面剖面图。P外延层110作为一个分级的外延层110’，还带有通过三种不同掺杂浓度的三步外延生长形成三个P掺杂层110-1、110-2和110-3。外延掺杂浓度随高度的增加而增大，也就是说底部P掺杂层110-1的掺杂浓度最低，顶部P掺杂层110-3的掺杂浓度最高。分级的外延层110’通过将击穿区从外延层的顶部往下移，提高了器件的UIS。而且，通过将击穿场下移到P外延层110中，使注入到P外延区110的电荷多于N区115，也可以提高UIS。尽管，此例中用于制备分级外延层的是三步外延层，但是也可以使用更多步的外延层。还可选择使用单一逐渐分级的外延层，其掺杂浓度从上到下逐渐降低。
图13和图14表示作为条纹元件的两种不同器件的侧面透视图。为了解释说明，此处没有表示出源极和本体区——仅表示出栅极和外延层。图13表示的器件类似于图4所示的器件100-1，图14表示的器件类似于图3所示的器件100。图15表示图14所示器件的俯视图，不连续区122位于栅极130中，靠近部分P-外延层116。掩膜使氧化填充物120在制备过程中，不在区域122中被刻蚀。同一掩膜也使靠近不连续区122的P-外延层116中不被植入P-型植入物117，P-型植入物117在其他地方沿沟槽植入。在带有裸露P-外延层116的地方，为了保持电荷平衡，可以建立从源极电压到P-外延层116的连接。也可选择，不在栅极130中形成不连续区122，形成P-型植入物117的植入过程并非表层植入，而是带有掩膜的，从而允许P-外延层116的区域非反向掺杂，并连接到源极电压上。也可以选择的是，这种效果也可以通过带有掩膜的P-型植入步骤达到，从而形成P-型植入物117来创造P-外延层116被暴露的区域。
图16和图17表示带有封闭元件的MOSFET器件的俯视图。如图16和图17所示的封闭元件与条纹结构相比，在一个6×6的带有3微米的硅台面结构的封闭元件(即2.5微米的P-区、0.25微米的N-环以及3微米的沟槽开口)中，如图16和图17所示的封闭元件能够降低约30％的Rds电阻。图16表示不带有源极或本体区的纳米管结构的封闭元件布局。P-外延层110位于每个封闭元件的中心，并被N-型纳米管115和N--外延层116包围着。沟槽栅极130和栅极氧化物125围绕着封闭元件。图17中所表示的是源极和本体区，P+本体接触140位于每个封闭元件的中心，被N+源极区145包围着。为了简化，图中没有表示出P-植入区117。也可选择，在沟槽栅极和半导体的位置互换时，使用带有不连续栅极的封闭元件，使半导体衬底(包含源极和本体)包围沟槽栅极，沟槽栅极位于封闭元件的中心。
图18表示类似于图12所示的MOSFET器件102，带有沟槽纳米管结构的MOSFET器件的侧面剖面图。P外延层110作为三个P掺杂层110-1、110-2和110-3，是通过从上到下依次递减的三种不同掺杂浓度的外延生长过程形成的。MOSFET器件还包含一个高压终止区，带有一个又宽又深的终止沟槽189(例如30微米)，并用介质材料190和氧化物120填充终止沟槽189。所形成的终止沟槽189带有一个用氧化物120填充的沟槽的初始网络，它可以与有源沟槽的氧化物120同时形成。半导体台面结构(图中没有表示出)位于氧化物120的网络之间；然后刻蚀掉半导体台面结构，将介质材料190填充到所产生的缝隙中。终止区的终点为沉积在晶片外围边缘上的锯齿街区195。
图19至图31为一系列侧面剖面图，表示带有类似于图3所示纳米管的自对准的高压(HV)半导体功率器件的制备过程。图19表示起始N+半导体衬底205，即重掺杂的N+硅衬底，承载着生长在衬底205上方的P-型外延层210。P-型外延层210也可以看出是上层半导体衬底，N+半导体衬底205可看作是下层半导体衬底。可以选择生长P-型外延层210，具有三种或更多种不同的P-掺杂浓度，或者具有逐渐分级的掺杂浓度，其掺杂浓度从上到下逐渐降低。然后，形成氧化层211和氮化硅(Si3N4)层212，作为硬掩膜。在图20中，利用沟槽掩膜(图中没有表示出)首先刻蚀硬掩膜，包含氧化层211和氮化硅层212。然后进行硅刻蚀，在外延层210中打开沟槽213。打开沟槽213的沟槽宽度约为3.5微米，沟槽深度约为36至40微米，侧壁角约为88度。N纳米管层215外延生长在N纳米管层215上方，厚度约为0.25至0.5微米，用砷掺杂物掺杂，如图21所示。P-外延层216可以生长在N纳米管层215上方。如图22所示，由于沟槽213的尺寸和倾斜的侧壁，N--外延层216充分填充了沟槽的底部。然后，如图24所示，将很薄的高密度等离子(HDP)氧化层220沉积在沟槽内，并填充沟槽。
在图24中，利用背部刻蚀过程和/或化学机械平整化(CMP)工艺，除去顶面上的氧化硅(SiO2)220，直到氮化硅层212裸露出来。使用沟槽栅极掩膜(图中没有表示出)，将氧化层220刻蚀到大约1.5至2.0微米的深度。如图25所示，利用N-型植入，在P-外延层216的裸露侧壁上形成N-型植入物217。
在图26中，形成厚度约为350-1200埃的栅极氧化层225，沿P-外延层216覆盖在侧壁上。沉积栅极多晶硅层230，最好选用N+原位掺杂多晶硅层。背部刻蚀多晶硅230，利用CMP工艺平整其顶面，并除去硬掩膜氧化层211和氮化硅(Si3N4)层212。进一步刻蚀多晶硅层230，形成一个轻微凹陷的栅极230，栅极多晶硅230的顶面比台面结构表面大约低0.3微米。然后在顶面上方生长一个衬垫氧化层232。
在图27中，利用高能量硼或P-本体掺杂植入，形成本体区235。进行高能本体掺杂植入时，要带有一定的倾斜角，以阻止由于沟槽侧壁的负台面结构角，而在沟槽侧壁附近的区域中产生遮蔽。升高温度后，进行本体掺杂驱动，将本体区235扩散到P-外延层210、N纳米管层215和N--外延层216中。然后，在接近零度时，进行重硼植入，以便在本体区235上方的顶面附近形成P+本体接触区240。在图28中，利用源极掩膜(图中没有表示出)进行低能含磷的N+植入，以形成包围在P-本体区235和P+区240中的N+源极区245。在900摄氏度下，利用退火工艺进行植入激活30分钟。在一个可选实施例中，在一个更高的温度下进行N型植入，以便在P-本体区235下方产生埋入的N型区，同样用于将MOSFET通道区连接到作为N-型植入物217的N外延层215。
然后，在顶面上形成一个氮化硅(Si3N4)硬掩膜层(图中没有表示出)。利用终止掩膜(图中没有表示出)在终止区中进行各向同性的硅刻蚀，以便在氧化硅层之间的终止区中的台面结构区域中打开沟槽(图中没有表示出)，然后用电介质或SiO2填充刻蚀后的台面结构沟槽(例如图18所示的介质层190)。背部刻蚀介质层190，直到硬掩膜层裸露出来，然后刻蚀并除去硬掩膜(图中没有表示出)。在终止区中的这些工艺如图11所示。如图29所示的那样，沉积含有硼酸的硅玻璃(BPSG)钝化层250。在图30中，利用接触掩膜(图中没有表示出)，打开穿过BPSG层250的接触开口。在图31中，在顶面上沉积一个金属层，然后利用金属掩膜(图中没有表示出)，在金属层上形成源极金属260-S和栅极垫(图中没有表示出)的图案。在衬底205的底部也形成一个金属层，以制备漏极金属205-D，从而完成了整个超级结纳米管MOSFET 200。
参见图32至图41为一系列侧面剖面图，表示一种带有如图3所示的纳米管的自对准高压(HV)半导体功率器件的终止区的制备过程。图32表示初始N+半导体衬底205(例如重N+掺杂硅衬底)，承载着P-型外延层210，P-型外延层210作为层210-1、210-2和210-3，用三种不同的掺杂浓度，在衬底205的上方生长。所生长的P-型外延层210也可以具有逐渐分级的掺杂浓度，其掺杂浓度从上到下逐渐降低。然后，形成氧化层和氮化硅(Si3N4)层212，作为硬掩膜。在图33中，利用沟槽掩膜(图中没有表示出)，首先刻蚀硬掩膜212，包含一个氧化层和一个氮化硅层。然后，利用硅刻蚀打开有源沟槽213b和终止沟槽213a，进入外延层210中。打开的沟槽深度约为36至40微米，侧壁角约为88度。终止沟槽213a的宽度可能大于有源区沟槽213b，以保证如图所示的那样，填充在这些沟槽中的氧化物到达沟槽底部。然后，在沟槽213a和213b的侧壁上外延生长一个N-外延纳米管层215，其厚度约为0.25至0.5微米，并用砷掺杂物掺杂，随后在N纳米管215上方外延生长一个P-外延层216。如图34所示，在沟槽中沉积并填充有薄HDP氧化层220。要注意的是，由于终止沟槽213a的宽度较大，虽然P-外延层216充分了填充有源区域沟槽213b的底部，却仅能填充终止沟槽213a的一薄层衬里。因此，氧化层220在终止沟槽213a中填充的深度远小于在有源沟槽213b中的深度。可在边界区域使用又深又宽的氧化物填充较宽沟槽，以便在同一半导体晶片上制备不同器件时，区分这些不同的器件。
然后，利用背部刻蚀工艺和/或化学机械平整化(CMP)工艺，除去顶面上的氧化层220，直到氮化硅层212裸露出来。这时，会在终止区中形成一个氧化立柱223的网络，在该网络中含有半导体台面结构224。终止区覆盖着宽沟槽213a，利用覆盖着终止区的沟槽栅极掩膜218，刻蚀有源区沟槽213b中的氧化层220。然后，如图35所示，沿P-外延层216的裸露侧壁进行N-型植入，制备N-型植入区217。如图36所示，通过栅极氧化层225的衬垫，制备多晶硅栅极230。此时，可以除去有源区上的硬掩膜212。然后，如上所述，形成P-本体基极区235和重P+区240。利用源极掩膜(图中没有表示出)，如上所述，在有源单元区中，植入并形成N+源极区245，如图37所示。在图38中，利用终止硬掩膜249，将沟槽栅极掩膜218和剩余的硬掩膜212一起除去。在图39中，利用硅刻蚀，刻蚀半导体台面结构224，即外延层210-1、210-2和210-3，在终止区的氧化层220之间，留下临时刻蚀沟槽222。在图40中，用介质材料290填充在终止区中的氧化层220之间的刻蚀沟槽222，以便填充终止区中的刻蚀台面结构，形成又深又宽的终止氧化沟槽289。在图41中，除去终止硬掩膜249，进行如图29至图31所示的后续处理工艺，完成带有如图18所示的特制终止区的MOSFET器件的制备。
图42为俯视图，图43和图44分别为带有平面终止结构的如图42所示的MOSFET器件的沿A-A’线和B-B’线的剖面图。为了清晰起见，虽然大体表示出了由金属层形成的电连接，但是俯视图并没有表示出金属、氧化物和钝化层的顶部，如图18和图41所示，平面终止是宽氧化沟槽的一个可选实施例。在平面终止结构中，终止区199’包含类似于有源区的台面结构110’，台面结构110’位于氧化层120’之间，用侧壁填充在沟槽中，并由N掺杂外延层115’覆盖着。终止单元不具有有源单元198’的源极/本体区135、140和145。相反，如图42至图44所示，P-台面结构和N-外延层由金属层150-1至150-5连接，以使每个终止单元闭锁一个特定的夹断电压VPT。钝化层195’可以覆盖金属层150-1至150-5。
最后一个有源单元(如图中左侧所示)，在源极电压为0伏时，通过金属层150-1，短接至第一终止单元的P-台面结构(以及在中间的多晶硅块130’)。更确切地说，金属层150-1连接了P区135′内的P+区140’。P-台面结构110’和周围的N-外延层115’耗尽，将N-外延层的电压升高至夹断电压VPT1，即N-外延层和P-台面结构耗尽时的电压。N-外延层115’连接到包围着第一终止单元的N+区140”的N区135”上，第一终止单元的N+区140”通过金属层150-2短接至下一个终止单元(右侧的下一个单元)的P-台面结构上，由于在该单元中发生耗尽，使电压又升高了一个VPT1，从而使此时的总电压为VPT2≈2*VPT1。直到达到器件的工作电压(漏极电压)时，这种情况才会停止。参见图45，首先将源极电势作为参考电压，例如金属层150-1的V＝0，电压以夹断步阶155的渐进式的方式逐渐增加，使得金属层150-2处的电压为VPT1。电压递增至VPT1，然后达到金属层150-3处的VPT2，最终升高到器件电压，即在最后一个金属层150-n处的600伏预设电压，如图45中最靠近半导体芯片边缘处的划线所示。
在氧化沟槽120’内形成多晶硅块130’，以防止电荷和污物进入氧化沟槽中的氧化物，从而提高了器件的可靠性。由于平面终止结构与宽氧化沟槽相比，需要更大的横向距离，以阻隔工作电压，因此该平面终止结构不如图18所示的宽氧化沟槽终止结构紧凑。还应注意的是，与上述有源单元区中的沟槽类似，在终止区中打开用氧化硅填充的沟槽，也带有稍稍倾斜的侧壁。
图46表示一种类似于图7所示的IGBT器件101’的剖面图，该IGBT器件101’与类似于图4所示的肖特基器件162’相集成。带有又深又宽氧化填充物121的宽沟槽，将器件分开。在这种情况下，将半导体衬底背部研磨到又深又宽的氧化填充物121的底部。在半导体材料的底部，植入N型层108’和P型层105-1’。由于IGBT不像MOSFET那样具有嵌入式二极管，因此该实施例十分有用。应明确的是，如同美国专利申请号为12/484,166中所述的那样，对不带有初始外延层的单一P-衬底进行背部研磨和植入后，可以用这种单一P-衬底构成器件。如图47所示，制备该结构也可以无需背部研磨，以便将P型层150-1”植入到一部分N-型半导体衬底108”中。
尽管本发明已经详细说明了现有的较佳实施例，但不应作为本发明的局限。例如，尽管以上说明所述的是n-通道器件，但是本发明通过将掺杂区域的导电类型反转，也可用于p-通道器件。可以制备各种不同的器件，包含那些带有平面栅极的器件。本领域的技术人员阅读上述详细说明后，各种变化和修正无疑将显而易见。因此，所附的权利要求书应涵盖本发明的真实意图和范围内的全部变化和修正。
尽管本发明的内容已经通过上述优选实施例作了详细介绍，但应当认识到上述的描述不应被认为是对本发明的限制。在本领域技术人员阅读了上述内容后，对于本发明的多种修改和替代都将是显而易见的。因此，本发明的保护范围应由所附的权利要求来限定。

Claims (20)

1.一种带有沟槽-氧化物-纳米管超级结的器件结构，其特征在于，包含：
一个第一导电类型的第一半导体层以及一个第二导电类型的第二半导体层，所述的第二半导体层沉积在第一半导体层上方；
在所述的第二半导体层中打开的沟槽，垂直延伸到所述的第一半导体层；
一个形成在所述的沟槽的侧壁上的第一导电类型的第一外延层；以及
一个形成在所述的第一外延层上的第二外延层；
其中所述的第一外延层与相邻的半导体区域之间达到充分的电荷平衡；所述的第二半导体层具有分级的掺杂结构，其掺杂浓度从上到下逐渐降低。
2.如权利要求1所述的器件结构，其特征在于，在至少某些沟槽中，所述第二外延层充分填充了未被第一外延层占据的缝隙的底部。
3.如权利要求2所述的器件结构，其特征在于，所述第二外延层的侧壁朝着沟槽的底部合并在一起。
4.如权利要求1所述的器件结构，其特征在于，所述沟槽的侧壁具有一定的角度，以形成锥形沟槽，并朝着沟槽的底面会聚。
5.如权利要求1所述的器件结构，其特征在于，所述第二外延层为第一导电类型。
6.如权利要求1所述的器件结构，其特征在于，所述第二外延层为第二导电类型或本征半导体材料。
7.如权利要求1所述的器件结构，其特征在于，还包含：在中心缝隙中的第一电介质填充物，所述中心缝隙在沟槽的中心，未被所述第二外延层占据。
8.如权利要求1所述的器件结构，其特征在于，还包含：一个栅极电极，其沉积在至少某些沟槽顶部中。
9.如权利要求8所述的器件结构，其特征在于，还包含：一个位于栅极电极下方的介质层填充沟槽剩余的中心部分。
10.如权利要求1所述的器件结构，其特征在于，还包含：形成在相邻沟槽之间的肖特基二极管和PN结二极管。
11.如权利要求10所述的器件结构，其特征在于，所述PN结二极管是一种电荷注入可控二极管，其与一个电荷注入可控电阻器串联，并与肖特基二极管并联。
12.如权利要求1所述的器件结构，其特征在于，所述的第二半导体层在两个相邻沟槽之间的宽度，至少是所述的第一外延层宽度的三倍。
13.如权利要求1所述的器件结构，其特征在于，所述器件结构还包含一个金属氧化物半导体场效应管MOSFET。
14.如权利要求1所述的器件结构，其特征在于，所述器件结构还包含一个绝缘栅双极晶体管IGBT。
15.如权利要求1所述的器件结构，其特征在于，所述器件结构还包含一个与二极管集成的绝缘栅双极晶体管IGBT。
16.如权利要求7所述的器件结构，其特征在于，还包含：
一个具有介质沟槽的终止结构，它包含一个由所述的第一电介质填充物形成的介质立柱的网络，和形成在网络内所述的介质立柱之间的第二电介质填充物。
17.如权利要求7所述的器件结构，其特征在于，至少一个第二器件沉积在半导体衬底上，其中沉积在相邻器件之间的沟槽比其他沟槽的沟槽宽度大。
18.如权利要求1所述的器件结构，其特征在于，所述器件结构还包含具有条纹结构的晶体管单元。
19.如权利要求1所述的器件结构，其特征在于，所述器件结构还包含具有封闭式单元布局的晶体管单元。
20.如权利要求1所述的器件结构，其特征在于，还包含：
一个由终止单元的阵列构成的终止区，在有源单元的界面处带有一个第一终止单元，其中每个终止单元还包含：
一个第二半导体层的台面结构，并且第一外延层形成在它的侧壁上，第二外延层形成在第一外延层上，所述台面结构靠近带有介质填充物的沟槽；
一个第一导电类型的第一区域，形成在所述台面结构的顶面中；以及
一个第二导电类型的第二区域，形成在所述台面结构的顶面中，与所述台面结构中的第一区域分开，
其中每个终止单元的第二区域都电连接到相邻的下一个终止单元的第一区域上。
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