TW201131774A - Configurations and methods for manufacturing devices with trench-oxide-nano-tube super-junctions - Google Patents

Configurations and methods for manufacturing devices with trench-oxide-nano-tube super-junctions Download PDF

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TW201131774A
TW201131774A TW100106597A TW100106597A TW201131774A TW 201131774 A TW201131774 A TW 201131774A TW 100106597 A TW100106597 A TW 100106597A TW 100106597 A TW100106597 A TW 100106597A TW 201131774 A TW201131774 A TW 201131774A
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Taiwan
Prior art keywords
trench
epitaxial layer
layer
dielectric
region
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TW100106597A
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Chinese (zh)
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TWI469347B (en
Inventor
Hamza Yilmaz
Madhur Bobde
Yee-Heng Lee
Ling-Peng Guan
xiao-bin Wang
John Chen
Anup Bhalla
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Alpha & Omega Semiconductor
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Priority claimed from US12/661,004 external-priority patent/US8390058B2/en
Application filed by Alpha & Omega Semiconductor filed Critical Alpha & Omega Semiconductor
Publication of TW201131774A publication Critical patent/TW201131774A/en
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Publication of TWI469347B publication Critical patent/TWI469347B/en

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Abstract

This invention discloses a semiconductor power device disposed on a semiconductor substrate of a first conductivity type. The semiconductor substrate supports an epitaxial layer of a second conductivity type thereon wherein the semiconductor power device is supported on a super-junction structure. The super-junction structure comprises a plurality of trenches opened from a top surface in the epitaxial layer; wherein each of the trenches having trench sidewalls covered with a first epitaxial layer of the first conductivity type to counter charge the epitaxial layer of the second conductivity type. A second epitaxial layer may be grown over the first epitaixial layer. Each of the trenches is filled with a non-doped dielectric material in a remaining trench gap space. Each of the trench sidewalls is opened with a tilted angle to form converging U-shaped trenches.

Description

201131774 六、發明說明： ^ 【發明所屬之技術領域】 [00013 本發明主要關於一種半導體功率元件，更確切地說，本 發明關於帶有溝槽側壁之溝槽奈米管之結構和製備方法 ，其中用摻雜的外延層覆蓋溝槽側壁，然後用絕緣材料 填充溝槽側壁，以便用簡化的製備技術靈活地製備可測 量的電荷平衡的半導體功率元件，同時獲得高擊穿電壓 以及很低的電阻。 【先前技#ί】 [0002] 儘管關於帶有垂直超級接面結構的半導體元件，為了改 善其電學特性，已有許多專利資訊以及公開的技術檔案 ，但是在超級接面半導體元件的設計和製備的相關領域 ，仍然存在許多技術難題與製備侷限。更確切地說，最 常見的超級接面元件包含金屬氧化物半導體場效電晶體 (MOSFET)和絕緣閘雙極電晶體，關於這些元件，已有 許多已公開的專利資訊，包含美國專利5,438, 215、 5, 216, 275、4, 754, 31 0、6, 828, 63卜藤平（Fuji-hira)在《半導體超級接面元件理論》（日本應用物理 快報，36卷，1997年10月，6254-62 62頁）一書中，提 出了垂直超級接面元件的結構。更確切地說，藤平發表 的論文中的第2圖表示了 一種垂直溝槽MOSFET超級接面元 件，在此引用為第1圖（1A)。藤平還在美國專利 6, 097, 063中提出了 一種具有漂流區的垂直半導體元件 ，當元件處於閉合模式時，漂流區中有漂流電流流過， 當元件處於斷開模式時，漂流區中的漂流電流耗盡。所 形成的漂流區結構是具有多個第一導電類型的分立的漂 100106597 表單編號 A0101 第 4 頁/共 65 頁 1003106142-0 201131774 ,, 流區，以及多個第二導電類型的分隔區，其中每一分隔 區都位於分別相鄰的漂流區中，並聯形成接面。美國 專利6,608,350提出了一種垂直超級接面元件帶有介 質材料層填充在溝槽中，美國專利5,981，996如第㈣（ 1B)所示，提出了 一種垂直溝槽MISFET元件。 圃然而，在這些專利技術和公開内容中所述的超級接面元 件的結構和工作性能中，仍然存在諸多技術侷限，從而 限制了這些元件在實際應財的有效性。傳統超級接面 〇 元件的難題與侷限包含深溝槽的填充、形成在溝槽中的 T米S的尺寸限制、保持終止區附近的臺面區域處電荷 平衡、超級接面元件的非箝位元感應開關OJIS)能力不 足、超級接面功率元件的振㈣題：由於外延生長速度 缓慢造成超級接面元件的絲造成本、超級接面結構中 的Ν和Ρ雜質在高溫下相互擴散、在同一晶片上難以整合 不同的7G件、以及高壓應用時的終止區域很大等相關技 術問題。 〇 闺目此’在料半導體謂的設朴製觸財，有必要 提出形成功率π件的新賴的元件結構和製備方法 ，從而 解決上述困難與侷限。 【發明内容】 闕因此树明的—個方面是提出—種新型的、改良的元 件L構和t備方法，藉由在溝槽㈣和底部，生長—薄 的N 3L摻雜外延層（例如坤外延層），沒有完全填充或 4刀填充槽’然後在第_外延層上方生長第二外延層 並用非格雜的介質材料填充剩餘的構成縫隙，從而解 100106597 表單編號Α010】 第5頁/共65頁 1003106142-0 201131774 決用外延層填充深溝槽時，傳統的製備方法中經常遇到 的問題。第二外延層可以充分填充其餘溝槽縫隙的底部 ，從而可以在縫隙中更加方便地沉積介質材料。 [0006] 本發明的另一方面在於，提出了一種帶有超級接面結構 的新型的、改良的元件結構和製備方法，利用電荷平衡 原理，藉由奈米管結構，降低Rds，並且元件間距很小， 以獲得6微米間距的600 V MOSFET，其導通電阻率小於9 毫歐/cm2。這就解決了用於高壓元件時對於高Rds的限制 〇 [0007] 本發明的另一方面在於，提出了一種帶有超級接面結構 的新型的、改良的元件結構和製備方法，該結構利用較 大的間距以及狹窄的N-外延層，並利用在每個主動元件 叉指末端具有較大半徑的單一元件，在主動區域臺面結 構的末端保持電荷平衡。 [0008] 本發明的另一方面在於，提出了一種帶有超級接面結構 的新型的、改良的元件結構和製備方法，在一個帶有摻 雜濃度分級的外延層中製備超級接面結構，例如在一個 N +基體上用三個步驟形成P外延層，迫使擊穿發生在漂流 區較低的部分中，從而改善超級接面MOSEFT元件的UIS 性能。 [0009] 本發明的另一方面在於，提出了一種帶有超級接面結構 的新型的、改良的元件結構和製備方法，厚介質區位於 閘電極以下，以降低閘-汲電容Crss，從而解決超級接面 功率元件的振盪問題。 100106597 表單編號A0101 第6頁/共65頁 1003106142-0 201131774 ’ ，本發明的另—方面在於，提出了-種帶有超級接面社構 的新塑的、改良的元件結構和製備方法，藉由生長_個 薄的單一層N-外延層（0.卜u微米的厚度範圍），部 分填充溝槽’並用電介質/氡化物填充剩餘的深溝槽從 而解決由於料槽中外延生錢慢，而造成的超級接面 元件的高製造成本問題。此外，輕摻雜的n_型外延層可 以在"卜延層之後生長’在用電介質/氧化物填充剩：的 深溝槽之前’充分填充溝槽，這有利於更加方便地用氧 化物填充溝槽。 〇 _]本發明的另一方面在於’提出了—種帶有超級接面結構 的新型的、改良的元件結構和製備方法，在較寬的卜型 區域附近形成一個非常薄的N-型奈米管層，並與較寬的 卜型區域電荷平衡；作為示例，N_型奈米管層比較寬的 P-型區域寬三倍’導致蝴的摻雜濃度比.型奈来管區域 中的N-型摻雜/農度低二倍《因此，只能允_受限的硼擴 散進入N_型奈米管區，從而補償多餘的砷電荷。N_型奈 Q 米管區域的重N-型摻雜（例如砷或銻），不會過分移動 ，從而不會大量擴散到P-型區。這就解決了在高溫下， N-和P-雜質相互擴散所帶來的問題。 [0012]本發明的另一方面在於，提出了一種帶有超級接面結構 的新型的、改良的元件結構和製備方法，增大第一元件 分界線處的溝槽區域寬度，例如對於一個娜F£T元件以 及-個第二元件（例如肖特基二極禮），是用介質#料 充分填充大溝槽區域〜與主動元件不同，主動元件是 用梦充分填充，再用氧切（氧化物或SiV填充剩餘 100106597 表單編號40〗第7 5 1003106142-0 頁/共65頁 201131774 部分。因此，不同的元件可以更加方便地整合在同一個 矽晶片上。 [0013] 本發明的另一方面在於，提出了一種帶有超級接面結構 的新型的、改良的元件結構和製備方法，將一個肖特基 二極體與一個受控的注入P-N二極體整合在一起，從而降 低了二極體的恢復電荷，減少高壓元件的汲電流。 [0014] 本發明的另一方面在於，提出了一種帶有超級接面結構 的新型的、改良的元件結構和製備方法，將一個高壓（ HV)肖特基二極體與一個受控的注入P-N二極體整合在同 一個矽晶片上，作為一個絕緣閘雙極電晶體（IGBT)， 其中IGBT的背面帶有發射極（對於N-通道元件而言為P-型）植入。從而解決了 IGBT結構缺少嵌入式二極體的難 題。 [0015] 本發明的另一方面在於，提出了一種新型的、改良的終 止結構，製備寬介質溝槽的方法是首先藉由形成一個 Si〇2網路，然後刻蝕掉Si〇2網路内的矽臺面結構，並用 自旋式玻璃、HDP或聚醯亞胺，填充剛刻蝕掉的區域，在 金屬化之前還是之後進行，取決於所選的介質材料的類 型。由於製備所受的限制，用傳統的刻蝕和填充方法很 難製備又寬又深的介質溝槽，但是本發明的兩步方法可 以利用標準的製備技術，形成一個高品質的又寬又深的 介質填充溝槽。對於一個6 0 0 V元件的每一側面而言，利 用終止區的這種寬氧化物溝槽，一個普通的6-10密耳寬 的HV終止區，可以減至2密耳。對於低電流產品，這種HV 終止區增大了晶片尺寸，對大晶片增大15%左右（在一個 100106597 表單編號A0101 第8頁/共65頁 1003106142-0 201131774 TO-220填充的能力中），對較小的晶片增大5〇%左右（ 對於HV終止，為53x53密耳Λ2晶片，8密耳)。因此 ，由於減小了適合高壓應用元件的終止區，從而解決了 高壓M0SFET功率元件，需要大終止區的難題。 [0016]閱讀以下詳細說明並參照圖式之後，本發明的這些和其 他的特點和優勢，對於本領域的技術人員而言，無疑將 顯而易見。 【實施方式】 [0017]201131774 VI. Description of the invention: ^ [Technical field to which the invention pertains] [00013] The present invention relates generally to a semiconductor power device, and more particularly to a structure and a method for fabricating a trench nanotube having a trench sidewall, The trench sidewall is covered with a doped epitaxial layer, and then the trench sidewall is filled with an insulating material to flexibly prepare a measurable charge-balanced semiconductor power device with a simplified fabrication technique while achieving high breakdown voltage and low resistance. [Previous Technology #ί] [0002] Although there are many patent information and published technical files for improving the electrical characteristics of semiconductor components with a vertical super junction structure, the design and fabrication of super junction semiconductor components There are still many technical difficulties and preparation limitations in the related fields. More specifically, the most common superjunction components include metal oxide semiconductor field effect transistors (MOSFETs) and insulated gate bipolar transistors. There are many published patent information on these components, including U.S. Patent 5,438. 215, 5, 216, 275, 4, 754, 31 0, 6, 828, 63 Fuji-hira in "The Theory of Semiconductor Super Junction Components" (Japan Applied Physics Letters, Vol. 36, October 1997, In the book 6254-62, page 62, the structure of the vertical super junction element is proposed. More specifically, Figure 2 of the paper published by Fujiwara shows a vertical trench MOSFET super junction component, which is referred to herein as Figure 1 (1A). In the U.S. Patent No. 6,097,063, the patent discloses a vertical semiconductor component having a drifting region. When the component is in the closed mode, drift current flows in the drift region, and when the component is in the off mode, the drift region The drift current is exhausted. The resulting drift zone structure is a discrete drift 100106597 having a plurality of first conductivity types, Form No. A0101, Page 4 of 65, 1003106142-0 201131774, a flow zone, and a plurality of separation zones of the second conductivity type, wherein Each of the separation zones is located in a respective adjacent drift zone and is connected in parallel to form a junction. U.S. Patent No. 6,608,350, the disclosure of which is incorporated herein incorporated by reference in its entirety in the entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all However, in the structure and performance of the super junction elements described in these patents and disclosures, there are still many technical limitations that limit the effectiveness of these components in actual financial resources. The problems and limitations of conventional super junction 包含 components include the filling of deep trenches, the size limitation of T meters formed in the trenches, the charge balance at the mesa regions near the termination regions, and the non-clamping inductance of the super junction elements. Insufficient capacity of switch OJIS), vibration of super junction power components (4): Due to the slow growth rate of epitaxial growth, the wires of super junction components cause the enthalpy and erbium impurities in the super junction structure to diffuse at high temperature on the same wafer. It is difficult to integrate different 7G parts, as well as a large termination area in high-voltage applications.闺 闺 此 ’ ’ ’ ’ 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在SUMMARY OF THE INVENTION Therefore, one aspect of the invention is to propose a novel, improved device L-structure and a method of preparing a thin-type N 3L doped epitaxial layer (for example, at the trench (four) and the bottom) (for example) Kun epitaxial layer), there is no complete filling or 4 knife filling trenches' then grow a second epitaxial layer over the first epitaxial layer and fill the remaining constituent gaps with non-lattice dielectric material, thus solving 100106597 Form No. Α 010] Page 5 / A total of 65 pages 1003106142-0 201131774 When using the epitaxial layer to fill deep trenches, the problems often encountered in conventional preparation methods. The second epitaxial layer can sufficiently fill the bottom of the remaining trench gaps so that the dielectric material can be deposited more conveniently in the gap. Another aspect of the present invention is to provide a novel and improved component structure and preparation method with a super junction structure, which utilizes the principle of charge balance, reduces the Rds by the nanotube structure, and has a very high component spacing. Small, to get a 6 V pitch 600 V MOSFET with an on-resistance of less than 9 mΩ/cm2. This solves the limitation of high Rds for high voltage components. [0007] Another aspect of the present invention is to provide a novel, improved component structure and preparation method with a super junction structure, which utilizes Larger pitches and narrow N- epitaxial layers, with a single element having a larger radius at the end of each active element finger, maintain charge balance at the end of the active area mesa structure. [0008] Another aspect of the present invention is to provide a novel, improved device structure and method of fabrication with a super junction structure for preparing a super junction structure in an epitaxial layer with doping concentration grading, For example, a P epitaxial layer is formed in three steps on an N+ substrate, forcing breakdown to occur in the lower portion of the drift region, thereby improving the UIS performance of the super junction MOSEFT device. Another aspect of the present invention is to provide a novel and improved device structure and a preparation method with a super junction structure, the thick dielectric region being located below the gate electrode to reduce the gate-tantalum capacitance Crss, thereby solving The problem of oscillation of the super junction power component. 100106597 Form No. A0101 Page 6 / Total 65 pages 1003106142-0 201131774 ', another aspect of the present invention is to propose a new plastic, improved component structure and preparation method with a super junction structure, From the growth of a thin single-layer N- epitaxial layer (0. ub u micron thickness range), partially fill the trench 'and fill the remaining deep trench with dielectric / germanide to solve the problem of slow extension of the epitaxial money in the trough The high manufacturing cost of the super junction component. In addition, the lightly doped n-type epitaxial layer can be grown after the "diffuse layer' to fully fill the trench before filling the deep trench with dielectric/oxide, which facilitates more convenient filling with oxide Groove. 〇_] Another aspect of the present invention is to propose a novel, improved element structure and preparation method with a super junction structure to form a very thin N-type nai near a wider pad-shaped region. The rice tube layer is balanced with the charge of the wider pad type; as an example, the N-type nanotube layer is three times wider than the wider P-type region, resulting in a doping concentration ratio of the butterfly. The N-type doping/agronomy is twice as low. Therefore, only limited _ restricted boron diffuses into the N_-type nanotube region, thereby compensating for excess arsenic charge. The heavy N-type doping (such as arsenic or antimony) in the N-type Q-tube region does not move excessively and thus does not diffuse into the P-type region in a large amount. This solves the problem caused by the mutual diffusion of N- and P- impurities at high temperatures. [0012] Another aspect of the present invention is to provide a novel, improved component structure and method of fabrication with a super junction structure that increases the width of the trench region at the boundary of the first component, such as for a The F£T component and the second component (such as Schottky II) are filled with large grooves in the medium. ~ Unlike the active components, the active components are fully filled with dreams and then oxygenated (oxidized). The object or SiV fills the remaining 100106597 Form No. 40, Section 7 5 1003106142-0, page 65, 201131774. Thus, different components can be more conveniently integrated on the same silicon wafer. [0013] Another aspect of the invention Therefore, a novel and improved component structure and preparation method with a super junction structure is proposed, which integrates a Schottky diode with a controlled injection PN diode, thereby reducing the dipole The charge recovery of the body reduces the enthalpy current of the high voltage component. [0014] Another aspect of the present invention is to provide a novel and improved component structure and system with a super junction structure. A method of integrating a high voltage (HV) Schottky diode with a controlled implanted PN diode on the same germanium wafer as an insulated gate bipolar transistor (IGBT), wherein the back side of the IGBT There is an emitter (P-type for N-channel components) implantation, thereby solving the problem that the IGBT structure lacks an embedded diode. [0015] Another aspect of the present invention is to propose a novel, The improved termination structure, the method of preparing the wide dielectric trench is first by forming a Si〇2 network, and then etching away the mesa structure in the Si〇2 network, and using spin glass, HDP or poly Amine, filling the area just after etching, before or after metallization, depending on the type of dielectric material selected. Due to limitations in preparation, it is difficult to prepare wide and deep by conventional etching and filling methods. The dielectric trench, but the two-step method of the present invention can utilize a standard fabrication technique to form a high quality, wide and deep dielectric filled trench. For each side of a 600 V component, the termination is utilized. District of this Wide oxide trench, a common 6-10 mil wide HV termination region, can be reduced to 2 mils. For low current products, this HV termination region increases wafer size and increases the size of large wafers by 15%. Left and right (in a 100106597 form number A0101 page 8 / total 65 pages 1003106142-0 201131774 TO-220 fill capacity), increase the size of the smaller wafer by about 5% (for HV termination, 53x53 mil 2 wafer) 8 mils. Therefore, the problem of requiring a large termination region is solved by reducing the termination region suitable for high voltage application components, thereby solving the problem of high termination MOSFET power devices. [0016] After reading the following detailed description and referring to the drawings, the present invention These and other features and advantages will no doubt become apparent to those skilled in the art. Embodiments [0017]

參閱第3圖表示本發明所述之溝槽奈米營金屬氧化物半導 體場效電晶體（M0SFET)元件1〇〇之剖面圖。M0SFET元 r 〜 -%' 件形成在一個Ρ-型外延層11〇中，ρ-型外延層11〇位於Ν + 基體105上。多個溝槽奈米管i 15和多個溝槽形成在外延 層110中。溝槽側壁帶有微小的傾斜角，以形成—個錐形 溝槽。作為示例，側壁可以略微傾斜Μ—89度。每個溝槽 侧壁都被N+外延層115覆蓋。另τ個輕摻雜的p-外延層 116生長在N +外延層115上方《由於剩餘的溝槽寬度和溝 槽的傾斜角’ P-外延層11 6的側壁朝著底部會合，並充分 填充溝槽的底部。用氧化矽120等電介質填充溝槽剩餘的 中心部分。MGSFET元件1GG更包含形成在溝槽頂部的溝 槽閘極130，溝槽閘極130被閘極氧化層125填充包圍著 ，並藉由氧化矽層12〇與下面的N+側壁層u 5絕緣。 M0SFET元件1〇〇更包含包圍著溝槽閘極13〇的本體區。每 個本體區都含有-個P_本體區135和—個重摻雜納: 接觸區140。M0SFET元件100更包含N +源極區 1喂ο ，N +源 極區145沉積在M0SFET元件100之頂面附近，被卜本體區 100106597 表單編號A0101 第9頁/共65頁 1003106142-0 201131774 140和135包圍著eM0SFET元件1〇〇更包含一個阻擋金屬 層150 ’以接觸源極區145和P +本體接觸區14〇，m〇sfet 元件loo也可以連接到源極電極155上。閘極電極16〇也 用於在溝槽閘極13G上載人閘極電壓。當打開咖阳元 件1〇〇時，會在本體區135中鄰近溝槽閘極13〇的地方形 成一個通道（圖中沒有表示出）。 [0018] P-外延層110和帶有側壁 '被N_外延層115和輕摻雜的n_ 外延層116覆蓋的溝槽，構成奈米管結構，以侧 元件獲得電荷平衡。本發明提出了—種電荷平衡的高壓 元件，就件可以高效地製備。卜側壁層115，即奈米管 ’同p-外延層11〇的鄰近部分達到電荷平衡，使得n_側壁 層115構成M0SFET的漂流區，該漂流區在斷開模式下耗 盡。p-外延層m更包含-個位於本體區135下面的N—型 植入區1Π，以便將通道連接到N_側壁層m中的漂流區 上。藉由從另-側耗《-外延層，以及允許更高的電荷 儲存終外延層115中，P-外延層116可以提供進一步的 =平衡’並改_議。例如’如果再增加挪的p_型 p儲存在P-外延層116中，那麼就可以再增加⑽的n_ p電荷儲存在N—外延層115中，從而侧贿降低25%。 餘^層116也充分填充轉槽的底部。這會使溝槽中剩 餘縫隙的縱橫比較小，可以輕_氧化填充_填充 Γ縫隙，從而避免了形成空洞等製備問題。氧化填充 =0使溝槽閘極13G與汲極電位絕緣，並降低了閘_没電 谷。 [0019] 100106597 丨~外延層115大約1微米寬， 表單編號A0101 在相鄰的N-外延層115之間 第10頁/共65頁 1003106142-0 201131774 的p、外延層no大約6微米寬，這僅作為 為p'外延層no具有兩半，4 3微米，並與外延層115保姓命_ ’ 〇 [0020] 〇 這僅作為示例，不作為侷 丨兩半，每一半的寬度都為Referring to Fig. 3, there is shown a cross-sectional view of a trench nanotube metal oxide semiconductor field effect transistor (M0SFET) device according to the present invention. The MOSFETs r to -%' are formed in a Ρ-type epitaxial layer 11 ,, and the ρ-type epitaxial layer 11 〇 is located on the Ν + substrate 105. A plurality of trench nanotubes i 15 and a plurality of trenches are formed in the epitaxial layer 110. The sidewalls of the trench are provided with a slight tilt angle to form a tapered trench. As an example, the side walls may be slightly inclined Μ-89 degrees. Each trench sidewall is covered by an N+ epitaxial layer 115. Another τ lightly doped p- epitaxial layer 116 is grown over the N + epitaxial layer 115 "Because the remaining trench width and the tilt angle of the trenches" P - the sidewalls of the epitaxial layer 116 meet toward the bottom and are sufficiently filled The bottom of the groove. The remaining central portion of the trench is filled with a dielectric such as yttrium oxide 120. The MGSFET device 1GG further includes a trench gate 130 formed at the top of the trench, the trench gate 130 being surrounded by the gate oxide layer 125 and insulated from the underlying N+ sidewall layer u 5 by the yttrium oxide layer 12 。. The MOSFET element 1 further includes a body region surrounding the trench gate 13A. Each body region contains a P_body region 135 and a heavily doped: contact region 140. The MOSFET component 100 further includes an N + source region 1 , and an N + source region 145 is deposited near the top surface of the MOSFET element 100. The body region is 100106597. Form number A0101 Page 9 / Total 65 pages 1003106142-0 201131774 140 The 135 surrounds the EMFET element 1 and further includes a barrier metal layer 150' to contact the source region 145 and the P + body contact region 14A. The m〇sfet device loo can also be connected to the source electrode 155. The gate electrode 16A is also used to upload a human gate voltage at the trench gate 13G. When the cayang element 1 is turned on, a channel (not shown) is formed in the body region 135 adjacent to the trench gate 13A. [0018] The P- epitaxial layer 110 and the trenches with the sidewalls 'covered by the N- epitaxial layer 115 and the lightly doped n- epitaxial layer 116 form a nanotube structure to obtain charge balance with the side elements. The present invention proposes a charge-balanced high-voltage component that can be efficiently produced. The sidewall layer 115, i.e., the nanotubes' and the adjacent portions of the p- epitaxial layer 11 are charge balanced such that the n-sidewall layer 115 constitutes a drift region of the MOSFET, which is depleted in the off mode. The p- epitaxial layer m further includes an N-type implant region 1 位于 under the body region 135 to connect the channel to the drift region in the N_ sidewall layer m. By consuming the "- epitaxial layer from the other side, and allowing higher charge storage in the final epitaxial layer 115, the P- epitaxial layer 116 can provide further = equilibrium" and change. For example, if the additional p_ type p is stored in the P- epitaxial layer 116, then the n_p charge of (10) can be further stored in the N- epitaxial layer 115, thereby reducing the bribe by 25%. The remaining layer 116 also fully fills the bottom of the turn. This makes the gaps in the trenches smaller and smaller, and can be lightly oxidized to fill the gaps, thereby avoiding the problem of preparation of voids. Oxidation fill =0 insulates the trench gate 13G from the drain potential and reduces the gate _ no valley. 100106597 外延~ epitaxial layer 115 is about 1 micron wide, form number A0101 between adjacent N- epitaxial layers 115, page 10 / total 65 pages 1003106142-0 201131774 p, epitaxial layer no is about 6 microns wide, This is only as the p' epitaxial layer no has two halves, 4 3 microns, and the epitaxial layer 115 protects the surname _ ' 〇 [0020] 〇 This is only an example, not as a two-half, each half of the width is

參閱第4圖表示本發明:所述之溝槽奈米管（腿m)元件 Hi之-個可選實施例，SFET元件了輕摻 雜的N--外延層hh (而不是第3圖所示之p_外延層ιΐ6 )生長在N +外延層115上以外，其他都與第3圖所示之 MOSFET元件1〇〇類似。因此，M0SFET元件1〇〇q中並不 需要N-型植入區117〇輕摻雜的N__外延層116_丨也充分 填充溝槽之底部’以便於接下來形成氧化填充物12〇。由 於形成N-外延層115之後，可以利用同—個外延生長室製 備N--外延層im，而要生長p_外延層116的話，就需 要將晶片移至另一個生長室，因此使用N__外延層 比P-外延層116更易於製備《這也提高了元件的產量。在 一個可選實施例中，N-外延層116-1可以用一個本質或輕 換雜的層代替。 參閱第5圖表示本發明所述之溝槽奈米管（m〇sfet)元件 100-2的一個可選實施例。M0SFET元件1〇()_2與第3圖所 示之MOSFET元件1〇〇基本類似，只是溝槽較寬，使得形 100106597 表單編號A0101 第11頁/共65頁 1003106142-0 [0021] 201131774 成在N+外延層11 5上方的P-外延層11 6-2僅僅襯在溝槽内 ，並不能充分填充溝槽底部。相反，氧化填充物120-2填 充了溝槽底部的絕大部分。 [0022] 參閱第6圖表示本發明所述之溝槽奈米管（MOSFET)元件 100-3的一個可選實施例。MOSFET元件100-3與第3圖所 示之MOSFET元件100基本類似，只是P-外延層116-3除 了在氧化填充物120-3下方的底部較厚以外，在大多數區 域中P-外延層116-3都很薄，以至於在這些區域中N +外 延層115-3都與它反向摻雜。可以選擇的是，如果在生長 P-外延層116-3之後實施各向同性的輕刻蝕，那麼就可以 形成這種結構。各向同性的刻蝕可以除去P-外延層116-3 的邊緣部分，留下P-外延層116-3的底部。 [0023] 參閱第7圖表示本發明所述之帶有溝槽奈米管結構之N-通 道絕緣閘雙極電晶體（IGBT)元件101之剖面圖。該 IGBT元件101形成在P-型外延層110中，P-型外延層110 位於P-基體層105-1上，作為IGBT的集電極，N-通道截 止層108沉積在P-外延層110和P+IGBT發射層105-1之間 。IGBT元件101與第3圖所示之MOSFET元件之結構類似， 也包含形成在外延層110中的多個溝槽奈米管，溝槽奈米 管中含有多個溝槽。所形成的溝槽帶有侧壁，側壁具有 微小的傾斜角，並且每個溝槽側壁都覆蓋有一個N-奈米 管層115、一個P-外延層116以及用氧化矽120填充的溝 槽中心部分。IGBT元件101更包含溝槽閘極130，溝槽閘 極130形成在溝槽頂部，被閘極氧化層125填充包圍著， 並藉由氧化矽層120與N +側壁層11 5絕緣。IGBT元件101 100106597 表單編號A0101 第12頁/共65頁 1003106142-0 201131774 .. 更包含溝槽間極周圍的本體區。每個本體區都含有—個 沉積在重接雜州本體接觸區14〇下面的卜本體區咖。 IGBTtl件1G1更包含N+源極區145，源極區⑷沉積在 頂面附近’並被卜本體區135和140包圍著。IGBT元件 ⑻更包含-個阻擋金屬層15〇，阻擋金屬層15〇將源極 區145和本體區140連接到發射極電極155上。再形成— ㈣極電極16Q，以便在溝槽閘極13()上載入閑極電壓。 [_ P_外延層110和所形成的帶有被N-外延層11 5覆蓋的側壁 〇 的溝槽構成奈米管結構.，以形成IG..BT元件中電荷平衡 的漂流區。 [0025]參閱第8圖表示本發明所述之帶有溝槽奈米管結構的電荷 注入控制二極體之剖面圖。第9圓用第8圖中的肖特基二 極體162以及P-N接面二極體161，表示意荷注入可調電 阻器R1 163的等效電路之電路圖。電荷注入可調電阻器 R1 163與P-N接面二極體1月1串聯？ P-N接面二極體161 與肖特基二極體162並聯。電阻器163可以整合到元件中 〇 ，例如作為一傭金屬和多晶夕電阻器，或者也可以外接 到元件中，使用戶可以選擇所需的電阻值。P-型外延層 110位於N-/N +基體層105上，作為P-N接面二極體和宵特 基二極體的陰極。到P-外延層110的歐姆接觸形成在第三 維中，一直到P+區176。肖特基二極體和P-N接面二極體 都位於P-外延層11〇上，所形成的P-外延層110帶有多個 溝槽奈米管，溝槽奈米管含有多個溝槽。所形成的溝槽 帶有侧壁，側壁具有微小的傾斜角，並且每個溝槽侧壁 都覆蓋有N -奈米管層115、P -外延層116以及用氡化石夕 100106597 表單編號A0101 第13萸/共65頁 1003106142-0 201131774 m填充的溝槽中心部分。較寬的溝槽可以形成在比其他 的氧化填充物120更寬更深的氧化填充物121上。當它們 升/成在同—半導體晶片上時，這樣有助於分離不同的元 件。肖特基二極體含有—個^區165，肖特基接觸金屬 Π0覆蓋著N-區165的頂面β N_區165沉積在奈米管115 上方，罪近氧化層120，並與p-外延層11〇和^摻雜區 U5相接觸。P — N接面二極體含有一個P-/P+區175/176 ，歐姆接觸金屬層180作為一個調製閘極，覆蓋在p_/p + 區175/176的頂面上。？-區175與？_外延層11〇和奈米管 層115相接觸。電阻器们163控制p_w接面二極體中的注 入能階，是藉由降低整個p_N接面二極體上的電壓（藉由 電壓VR1 = I二極體*R1)，致使p_N接面二極體上儲存的 電荷量減少’反向恢復得到增強。電阻器R1的值較大， 會使反向恢復增強，並且傳導率調製降低帶來更少的正 向傳導。電阻器R1的值較小會帶來相反的效果。將肖特 基二極體與P-N接面二極體並聯，會進一步減少p_N接面 二極體中儲存的電荷量。改變電阻器R1 163的大小，可 以控制P-N接面二極體161中儲存的電荷量以及二極體的 性能。P-N接面二極體降低了高壓（Hv)肖特基二極體的 汲電流，優化了複合元件的正向電壓降Vf。 [0026] 參閱第10圖以及第11圖之剖面圖所示，肖特基二極體（ 用N-區165表示）以及P-N接面二極體（用P-/P+區 175/176表不）位於外延層110的同一條紋上。 [0027] 參閱第12圖表示類似於第3圖所示之MOSFET元件，帶有 溝槽奈米管結構之MOSFET元件102之侧面剖面圖。P-外 100106597 表單編號A0101 第14頁/共65頁 1003106142-0 201131774 作為一個分級的外延層110,，更帶有藉由三種不 雜岷度的二步外延生長形成三個p_摻雜層— J、 ❹ [0028] Ο 就=2和110_3。外延摻雜濃度隨高度的增加而增大，也 雜疋說底部P-摻雜層11〇_W摻雜濃度最低，頂部卜摻 墼1/0-3的摻雜濃度最高。分級的外延層11〇，藉由將 ，从區從外延層的頂部往下移，提高了元件的㈣。而且 猎由將擊穿場T移到P—外延層110中，使注入到P—外延 品的電荷多於N-區115,也可以提高⑽。儘管，此 例令用於製備分級外延層的是三步外延層，但是也可以 使用更多步的外延層。還可選擇使用單__ 延層，其摻雜濃度從上到下逐漸降低… 參閱第13圖和第14圖表示作為條紋元件之兩種不同元件 2面透視圖。為了解釋說明’此處沒有表示出源極和 本體區一僅表示出和外延層。第Μ圖表示的元件 類似於第4圖所示的元件1〇(M，川圖表示的元件類似 於第3圖所示的元件100。第15圖表示扣圖所示元件之 俯視圖’不連續區122位於閘極13〇令’靠近部分卜外延 層U6掩膜使氧化填充物120在製備過程中，不在區域 122中被刻钱。同一掩膜也使靠近不連續區122的^卜延 層116中不被植入P_型植入物117，卜型植入物⑴在其 他地方沿溝槽植入。在帶有裸露P_外延層116的地方 了保持電荷平衡’可以建立從源極電壓到卜外延層⑴的 連接。也可選擇，不在問極130中形成不連續區122，形 成p-型植入物117的植入過程並非表層植入，而是帶有掩 膜的’從而允許P—外延層116的區域非反向摻雜，並連接 100106597 表單編號A0101 第15頁/共65頁 1003106142-0 201131774 到源極電Μ上。也可以選擇的是，這種效果也可以藉由 帶有掩膜的Ρ-型植人步驟達到，從而形成卜型植入物117 來創造Ρ-外延層11 6被暴露的區域。 [0029] [0030] 參閱第16圖和第π圖表示帶有封閉元件之娜m元件之 俯視圖。如第_和第π圖所示之封閉元件與條紋結構 相比，在一個6x6的帶有3微米之矽臺面結構之封站元件 (即2. 5微米的P-區、〇.25微米的N_環以及3微米的溝槽 開口）中，如第16圖和第17圖所示之封閉元件能夠降低 約30%的Rds電阻。第16圖表示不帶主動極或本體區之奈 米官結構之封閉元件佈局。P—外延層11〇位於每個封閉元 件的中心，並被M-型奈米管115和卜，外延層116包圍著 。溝槽閘極13 0和閘極氧化物12 5圍繞著封閉元件。第17 圖中所表示的是源極和本體區，p+本體接觸14〇位於每個 封閉元件的中心，被N +源極區145包圍著。為了簡化，圖 中沒有表示出P-植入區117。也可選擇，在溝槽閘極和半 導體的位置互換時’使用帶有不連續閘極的封閉元件， 使半導體基體（包含源極和本體）包圍溝槽閘極，溝槽 閘極位於封閉元件的中心。 參閱第18圖表示類似於第12圖所示之MOSFET元件102， 帶有溝槽奈米管結構之MOSFET元件之側面剖面圖。ρ-外 延層110作為三個P-摻雜層110-1、Π0-2和110-3，是 藉由從上到下依次遞減的三種不同摻雜濃度的外延生長 過程形成的。MOSFET元件更包含一個高壓終止區，帶有 —個又寬又深的終止溝槽189 (例如30微米），並用介質 材料190和氧化物120填充終止溝槽189。所形成的終止 100106597 表單編號A0101 第16頁/共65頁 1003106142-0 201131774 . 溝槽189帶有一個用氧化物120填充的溝槽的初始網路， 匕可以與主動溝槽的氧化物120同時形成。半導體臺面結 構（圖中;又有表示出）位於氧化物12 0的網路之間；然後 刻蝕掉半導體臺面結構，將介質材料190填充到所產生的 縫隙中。終止區的終點為沉積在晶片週邊邊緣上的鋸齒 街區19 5。 [0031]參閲第1 9圖至第31圖為一系列側面剖面圖，表示帶有類 似於第3圖所示奈米管之自對準的高壓（HV)半導體功率 〇 70件之製備過程。第19圖表示起始N+半導體基體205，即 重摻雜的N +矽基體，承載著生長在基體2 0 5上方的p _型外 延層210 ^ p-型外延層21〇也可以看出是上層半導體基體 ，N +半導體基體205可看作是下層半導體基體。可以選擇 生長P-型外延層210，具有三種或更多種不同的p摻雜濃 度，或者具有逐漸分級的摻雜濃度，其摻雜濃度從上到 下逐漸降低。然後’形成氧化層211和氮化矽（si N ) 3 4 y 層212，作為硬掩膜。在第20圖中，利用溝槽掩膜（圖中 Q 沒有表示出）首先刻铀硬掩膜，包含氧化層211和氮化矽 層212。然後進行矽刻蝕，在外延層210中打開溝槽213 。打開溝槽213的溝槽寬度約為3. 5微米，溝槽深度約為 36至40微米，侧壁角約為88度。^^奈米管層215外延生長 在N奈米管層215上方，厚度約為〇.25至0. 5微米，用砷 摻雜物摻雜，如第21圖所示。p_外延層216可以生長在N 奈米管層215上方。如第22圖所示，由於溝槽213的尺寸 和傾斜的侧壁，N--外延層21 6充分填充了溝槽的底部。 然後，如第24圖所示，將报薄的高密度等離子（HDp)氧 100106597 表單編號A0101 第17頁/共65頁 1003106142-0 201131774 並填充溝槽。 化層220沉積在溝槽内， [0032] [0033] [0034] =4圖中，利用背部韻過程和/或化 化 (C則技術，除去頂面上的氧切（ 氣化石夕層212裸露出來。使«槽叫掩膜（圖中沒有表 不出），將氧化層m刻姓到大約15至2〇微米的深度 〇如第25圖所示，利用n —型植入， 又 露側壁上形成N-型植入物217。 夕卜延層216的裸 參閱第26圖中，形成厚度約為35(M2_的閘極氧化声 225,沿P-外延層216覆蓋在侧壁上。沉積閘極多 230，最好選膝原位摻雜多晶外1部職多晶石夕 ，利用⑽技術平整其頂面’並除去硬掩膜氧化声Referring to Figure 4, there is shown an alternative embodiment of the invention of the trench nanotube (leg m) element Hi, the SFET element having a lightly doped N- epitaxial layer hh (instead of Figure 3) The p_epitaxial layer ι6) is grown on the N + epitaxial layer 115, and the others are similar to the MOSFET device 1A shown in FIG. Therefore, the N-type implant region 117 is not required in the MOSFET element 1 〇〇 q, and the lightly doped N_- epitaxial layer 116_丨 also sufficiently fills the bottom of the trenches to facilitate the subsequent formation of the oxidized filler 12 〇. Since the N- epitaxial layer im can be formed by the same epitaxial growth chamber after the N- epitaxial layer 115 is formed, and the p- epitaxial layer 116 is to be grown, the wafer needs to be moved to another growth chamber, so N__ is used. The epitaxial layer is easier to prepare than the P- epitaxial layer 116. This also increases the yield of the component. In an alternate embodiment, the N- epitaxial layer 116-1 can be replaced with an essential or lightly modified layer. Referring to Figure 5, an alternative embodiment of a trench nanotube element 100-2 of the present invention is shown. The MOSFET element 1〇()_2 is basically similar to the MOSFET element 1〇〇 shown in FIG. 3, except that the trench is wider, so that the shape 100106597 form number A0101 page 11/65 page 1003106142-0 [0021] 201131774 The P- epitaxial layer 11 6-2 over the N+ epitaxial layer 11 5 is only lined in the trench and does not sufficiently fill the bottom of the trench. In contrast, the oxidized filler 120-2 fills most of the bottom of the trench. [0022] Referring to Fig. 6, an alternative embodiment of a trench nanotube (MOSFET) device 100-3 of the present invention is shown. The MOSFET device 100-3 is substantially similar to the MOSFET device 100 shown in FIG. 3 except that the P- epitaxial layer 116-3 has a thicker bottom portion below the oxidized filler 120-3, and the P- epitaxial layer is in most regions. 116-3 is so thin that the N + epitaxial layer 115-3 is counter-doped with it in these regions. Alternatively, if an isotropic light etch is performed after the growth of the P- epitaxial layer 116-3, such a structure can be formed. An isotropic etch can remove the edge portion of the P- epitaxial layer 116-3 leaving the bottom of the P- epitaxial layer 116-3. [0023] Referring to Fig. 7, there is shown a cross-sectional view of an N-channel insulated gate bipolar transistor (IGBT) device 101 having a trenched nanotube structure according to the present invention. The IGBT element 101 is formed in a P-type epitaxial layer 110, and the P-type epitaxial layer 110 is located on the P-substrate layer 105-1. As a collector of the IGBT, an N-channel cut-off layer 108 is deposited on the P- epitaxial layer 110 and P + IGBT between the emission layers 105-1. The IGBT element 101 is similar in structure to the MOSFET element shown in Fig. 3, and also includes a plurality of trench nanotubes formed in the epitaxial layer 110, and the trench nanotubes contain a plurality of trenches. The trench is formed with sidewalls, the sidewalls have a slight tilt angle, and each trench sidewall is covered with an N-nanotube layer 115, a P- epitaxial layer 116, and a trench filled with yttrium oxide 120. Central part. The IGBT device 101 further includes a trench gate 130 formed on top of the trench, surrounded by the gate oxide layer 125, and insulated from the N + sidewall layer 11 5 by the hafnium oxide layer 120. IGBT component 101 100106597 Form No. A0101 Page 12 of 65 1003106142-0 201131774 .. More includes the body area around the inter-groove pole. Each body region contains a body of the body that is deposited under the contact area of the body of the mixed state. The IGBT tl device 1G1 further includes an N+ source region 145, and the source region (4) is deposited near the top surface ′ and surrounded by the body regions 135 and 140. The IGBT element (8) further includes a barrier metal layer 15A which connects the source region 145 and the body region 140 to the emitter electrode 155. The fourth electrode 16Q is formed again to load the idle voltage on the trench gate 13(). The [_P_ epitaxial layer 110 and the formed trenches with the sidewalls 覆盖 covered by the N- epitaxial layer 11 5 constitute a nanotube structure to form a charge-balanced drift region in the IG.. BT device. Referring to Fig. 8, there is shown a cross-sectional view of a charge injection control diode having a trench nanotube structure according to the present invention. The ninth circle uses the Schottky diode 162 and the P-N junction diode 161 in Fig. 8 to show a circuit diagram of an equivalent circuit of the charge-injecting tunable resistor R1 163. Charge injection adjustable resistor R1 163 and P-N junction diode in January 1 series? The P-N junction diode 161 is connected in parallel with the Schottky diode 162. Resistor 163 can be integrated into the component, for example as a commission metal and polysilicon resistor, or it can be externally connected to the component, allowing the user to select the desired resistance value. The P-type epitaxial layer 110 is located on the N-/N + base layer 105 as a cathode of the P-N junction diode and the bismuth diode. The ohmic contact to the P- epitaxial layer 110 is formed in the third dimension up to the P+ region 176. The Schottky diode and the PN junction diode are both located on the P- epitaxial layer 11〇, and the formed P- epitaxial layer 110 has a plurality of trench nanotubes, and the trench nanotubes contain a plurality of trenches. groove. The trench is formed with sidewalls, the sidewalls have a slight tilt angle, and each trench sidewall is covered with an N-nanotube layer 115, a P- epitaxial layer 116, and a fossilized fossil 100106597 Form No. A0101 13萸/ Total 65 pages 1003106142-0 201131774 m filled groove center part. The wider trenches may be formed on the oxidized fill 121 wider and deeper than the other oxidized fills 120. This helps to separate the different components as they rise/become on the same semiconductor wafer. The Schottky diode contains a region 165, and the Schottky contact metal Π0 covers the top surface of the N-region 165. The β N_ region 165 is deposited over the nanotube 115, sinning the near oxide layer 120, and with p The epitaxial layer 11 is in contact with the doped region U5. The P-N junction diode contains a P-/P+ region 175/176, and the ohmic contact metal layer 180 acts as a modulation gate covering the top surface of the p_/p+ region 175/176. ? - District 175 with? The epitaxial layer 11 is in contact with the nanotube layer 115. The resistors 163 control the injection level in the p_w junction diode by lowering the voltage across the p_N junction diode (by voltage VR1 = I diode *R1), resulting in a p_N junction The amount of charge stored on the polar body is reduced 'reverse recovery is enhanced. A larger value of resistor R1 will increase the reverse recovery and a lower conduction modulation will result in less forward conduction. A smaller value of the resistor R1 has the opposite effect. Parallel connection of the Schottky diode to the P-N junction diode further reduces the amount of charge stored in the p_N junction diode. By changing the size of the resistor R1 163, the amount of charge stored in the P-N junction diode 161 and the performance of the diode can be controlled. The P-N junction diode reduces the erbium current of the high voltage (Hv) Schottky diode and optimizes the forward voltage drop Vf of the composite component. Referring to the cross-sectional views of FIGS. 10 and 11, Schottky diodes (represented by N-region 165) and PN junction diodes (using P-/P+ regions 175/176) ) is located on the same stripe of the epitaxial layer 110. [0027] Referring to Fig. 12, there is shown a side cross-sectional view of a MOSFET device 102 having a trench nanotube structure similar to the MOSFET device shown in Fig. 3. P-External 100106597 Form No. A0101 Page 14 of 65 1003106142-0 201131774 As a graded epitaxial layer 110, there are three p-doped layers formed by two-step epitaxial growth with three kinds of non-doping — J, ❹ [0028] Ο For = 2 and 110_3. The epitaxial doping concentration increases with the increase of the height. It is also said that the bottom P-doped layer 11〇_W has the lowest doping concentration, and the top doped 墼1/0-3 has the highest doping concentration. The graded epitaxial layer 11〇, by moving the region from the top of the epitaxial layer downward, improves the component (4). Moreover, the hunting is performed by moving the breakdown field T into the P-epitaxial layer 110 so that the charge injected into the P-epitaxial product is more than the N-region 115, and it is also possible to increase (10). Although this example is used to fabricate a graded epitaxial layer in a three-step epitaxial layer, more steps of the epitaxial layer can be used. It is also possible to use a single __stretch layer whose doping concentration gradually decreases from top to bottom... Referring to Figures 13 and 14, there are shown two different views of the two different elements as a stripe element. For the purpose of explanation, the source and body regions are not shown here, and only the epitaxial layer is shown. The elements shown in the second diagram are similar to the elements 1 〇 (M shown in Fig. 4, and the elements shown in the middle diagram are similar to the elements 100 shown in Fig. 3. Fig. 15 shows the top view of the elements shown in the buckle diagram. The region 122 is located at the gate 13 and is close to the portion of the epitaxial layer U6 mask so that the oxidized filler 120 is not engraved in the region 122 during the preparation process. The same mask also causes the retardation near the discontinuous region 122. The P_type implant 117 is not implanted in the 116, and the implant (1) is implanted along the trench elsewhere. In the place where the exposed P_ epitaxial layer 116 is held, the charge balance can be established from the source. The connection of the voltage to the epitaxial layer (1). Alternatively, the discontinuous region 122 is not formed in the interrogation pole 130, and the implantation process for forming the p-type implant 117 is not a surface implantation but a mask. Allowing the region of the P- epitaxial layer 116 to be non-inverted doped, and connecting 100106597 form number A0101 page 15 / page 65 1003106142-0 201131774 to the source cell. Alternatively, this effect can also be borrowed This is achieved by a sputum-type implant step with a mask to form a implant 117 To create a region in which the epitaxial layer 116 is exposed. [0030] Referring to Figure 16 and Figure π, there is shown a top view of the element m with a closed element. The closure as shown in the _ and πth figures The component is compared to the stripe structure in a 6x6 closed-end structure with a 3 micron mesa structure (ie, a 2.5 micron P-region, a .25 micron N_ring, and a 3 micron trench opening). The closing element as shown in Figures 16 and 17 is capable of reducing the Rds resistance by about 30%. Figure 16 shows the closed element layout of the nano-structure without the active pole or body region. P- Epitaxial layer 11 The crucible is located at the center of each of the closure elements and is surrounded by an M-type nanotube 115 and a epitaxial layer 116. The trench gate 13 0 and the gate oxide 12 5 surround the closure element. Illustrated is the source and body regions, the p+ body contacts 14 〇 are located at the center of each of the closed elements, surrounded by the N + source regions 145. For simplicity, the P-embedded regions 117 are not shown. When the position of the trench gate and the semiconductor are interchanged, 'use a closed element with a discontinuous gate to make the semiconductor substrate The source and the body are included to surround the trench gate, and the trench gate is located at the center of the closed element. Referring to Fig. 18, a MOSFET element 102 similar to the MOSFET element 102 shown in Fig. 12, having a trench nanotube structure A side cross-sectional view of the p-epitaxial layer 110 as three P-doped layers 110-1, Π0-2 and 110-3, formed by epitaxial growth processes of three different doping concentrations which are successively decreasing from top to bottom The MOSFET device further includes a high voltage termination region with a wide and deep termination trench 189 (e.g., 30 microns) and fills the termination trench 189 with dielectric material 190 and oxide 120. The resulting termination 100106597 Form No. A0101 Page 16 of 65 1003106142-0 201131774. The trench 189 has an initial network of trenches filled with oxide 120, which can be simultaneously with the oxide 120 of the active trench form. The semiconductor mesa structure (shown in the figure) is located between the networks of oxides 120; the semiconductor mesa structure is then etched away and the dielectric material 190 is filled into the resulting gaps. The end point of the termination zone is a sawtooth block 195 deposited on the peripheral edge of the wafer. [0031] Referring to Figures 19 through 31, a series of side cross-sectional views showing the preparation of a high voltage (HV) semiconductor power 〇 70 piece with a self-alignment similar to the nanotube shown in Fig. 3. . Figure 19 shows the starting N+ semiconductor substrate 205, i.e., the heavily doped N + 矽 substrate, carrying the p _ type epitaxial layer 210 ^ p-type epitaxial layer 21 grown above the substrate 205. The upper semiconductor substrate, N + semiconductor substrate 205 can be considered as a lower semiconductor substrate. The P-type epitaxial layer 210 may be grown to have three or more different p-doping concentrations, or have a gradually graded doping concentration whose doping concentration gradually decreases from top to bottom. Then, an oxide layer 211 and a tantalum nitride (si N ) 3 4 y layer 212 are formed as a hard mask. In Fig. 20, a uranium hard mask is first engraved using a trench mask (not shown by Q in the figure), including an oxide layer 211 and a tantalum nitride layer 212. A germanium etch is then performed to open trench 213 in epitaxial layer 210. The groove width of the opening trench 213 is about 3.5 μm, the groove depth is about 36 to 40 μm, and the sidewall angle is about 88 degrees. ^^ The nanotube layer 215 is epitaxially grown over the N-nanotube layer 215, having a thickness of about 2525 to 0.5 μm, doped with an arsenic dopant, as shown in Fig. 21. The p- epitaxial layer 216 can be grown over the N nanotube layer 215. As shown in Fig. 22, the N-- epitaxial layer 216 sufficiently fills the bottom of the trench due to the size of the trench 213 and the inclined sidewalls. Then, as shown in Fig. 24, the thin high-density plasma (HDp) oxygen 100106597 form number A0101 page 17 / page 65 1003106142-0 201131774 will be reported and filled. The layer 220 is deposited in the trench, [0034] in the figure of Fig. 4, using the back rhyme process and/or chemicalization (C technique, removing the oxygen cut on the top surface (gasification layer 202) Exposed to the naked. Make the «slot mask (not shown in the figure), the oxide layer m to the depth of about 15 to 2 microns, as shown in Figure 25, using n-type implant, and exposed An N-type implant 217 is formed on the sidewall. Referring to Figure 26, a gate oxidized sound 225 having a thickness of about 35 (M2_) is formed, which is covered on the sidewall along the P- epitaxial layer 216. The deposition gate is more than 230, preferably the knee is in-situ doped polycrystalline outside the first polycrystalline stone, using (10) technology to flatten its top surface 'and remove the hard mask oxidation sound

211和氮㈣（W層212。進—步職W ’形成-個輕微凹陷的閑極23〇，間極多晶石夕23〇的頂面 比臺面結構表面大純〇.3微米1後在頂面上方生長一 個襯墊氧化層232。 、 參閱第27圖中’利用高能量㈣p〜本體摻雜植入，形成 本體區235。進行高能本體摻雜植人時，要帶有—定的傾 斜角，以阻止由於溝槽侧壁的負臺面結構角，而在溝槽 側壁附近的《巾產生紐。升高溫度後，進行本體換 雜驅動，將本體區饥擴散到卜外延層21〇、N —奈米管層 215和N--外延層216中。然後，在接近零度時進行重 硼植入，以便在本體區235上方的頂面附近形成p +本體接 觸區240。在第28圖中，利用源極掩膜（圖中沒有表示出 )進行低能含鱗的N +植入，以形成包圍在p_本體區235和 P+區240中的N +源極區245。在900攝氏度下，利用退火 100106597 表單編號A0101 第18頁/共65頁 1003106142-0 201131774 技術進行植入啟動30分鐘。在一個可選實施例中，在一 個更面的溫度下進行Ν-型植入，以便在Ρ-本體區235下方 產生埋入的Ν-型區，同樣用於將MOSFET通道區連接到作 為Ν-型植入物217的Ν外延層215。 [0035] Ο 然後，在頂面上形成一個氮化石夕（S i 3 Ν 4 )硬掩膜層（圖 中沒有表示出）。利用終止掩膜（圖中沒有表示出）在 終止區中進行各向同性的矽刻蝕，以便在氧化矽層之間 的終止區中的臺面結構區域中打開溝槽（圖中沒有表示 出）’然後用電介質或Si〇2填充刻蝕後的臺面結構溝槽 (例如第18圖所示的介倉眷1 #0 )。背部刻蝕介質層19 0 ，直到硬掩膜層裸露出來，然後刻蝕並除去硬掩膜（圖 中沒有表示出）。在終止區中的這些技術如第11圖所示 。如第29圖所示的那樣，沉積含有硼酸的矽玻璃（BPSG )鈍化層250。在第30圖中，利用接觸掩膜（圖中沒有表 示出），打開穿過BPSG層250的接觸開口！在第31圖中 ，在頂面上沉積一個金屬層，然後利用金屬掩膜（圖中 (.. .211 and nitrogen (four) (W layer 212. Into-step W' formed - a slightly depressed idle pole 23 〇, the top surface of the intergranular polycrystalline 夕 23 大 is larger than the surface of the mesa structure. 3 micron 1 after A pad oxide layer 232 is grown on top of the top surface. Referring to Figure 27, the implantation of high energy (tetra)p~ bulk doping forms a body region 235. When high energy body doping is implanted, a tilt is required. The angle is to prevent the angle of the negative mesa structure of the sidewall of the groove, and the towel is generated near the sidewall of the groove. After the temperature is raised, the body is replaced by the body, and the body region is diffused to the epitaxial layer 21〇. N - nanotube layer 215 and N - epitaxial layer 216. Then, heavy boron implantation is performed near zero to form p + body contact region 240 near the top surface above body region 235. Figure 28 The low energy scaled N+ implant is performed using a source mask (not shown) to form an N+ source region 245 enclosed in the p_body region 235 and the P+ region 240. At 900 degrees Celsius , using annealing 100106597 Form No. A0101 Page 18 / Total 65 Page 1003106142-0 201131774 Technology for implantation For 30 minutes. In an alternative embodiment, a Ν-type implant is performed at a more gradual temperature to create a buried Ν-type region below the Ρ-body region 235, also for MOSFET channel regions. It is connected to a germanium epitaxial layer 215 which is a Ν-type implant 217. [0035] Then, a hard mask layer of nitridite (S i 3 Ν 4 ) is formed on the top surface (not shown). An isotropic germanium etch is performed in the termination region using a termination mask (not shown) to open the trench in the mesa region of the termination region between the hafnium oxide layers (not shown) 'The dielectric mesa or Si〇2 is then used to fill the etched mesa structure trench (such as the dielectric 眷1 #0 shown in Figure 18). The back etch the dielectric layer 19 0 until the hard mask layer is exposed, then The hard mask is etched and removed (not shown). These techniques in the termination region are shown in Figure 11. As shown in Figure 29, a beryllium glass (BPSG) passivation layer 250 containing boric acid is deposited. In Figure 30, using a contact mask (not shown), open through the BPSG Contact opening of layer 250! In Figure 31, a metal layer is deposited on the top surface and then a metal mask is used (in the figure (..

沒有表示出），在金屬層上形成源極金屬260_8和閘極墊 (圖中沒有表示出）的圖案。在基體205的底部也形成一 個金屬層，以製備汲:極金屬205-D，從而完成了整個超級 結奈米管MOSFET 200。 [0036] 參見第32圖至第41圖為一系列侧面剖面圖’表示一種帶 有如第3圖所示之奈米管的自對準高壓（HV)半導體功率 元件的終止區之製備過程。第32圖表示初始N +半導體基 體205(例如重N +摻雜矽基體），承載著卜型外延層210 ’ P-型外延層210作為層210-1、一2和21 0-3，用三 100106597 表單編號A0101 第19頁/共65頁 1003106142-0 201131774 種不同的摻雜濃度，在基體205的上方生長。所生長的p_ 型外延層21〇也可以具有逐漸分級的摻雜濃度，其摻雜濃 度從上到下逐漸降低 。然後，形成氧化層和氮化石夕（ Si/4)層2i2 ’作為硬掩膜。在第33圖中，利用溝槽掩 膜（圖中沒有表示出），首先刻蝕硬掩膜212，包含一個 氧化層和一個氮化矽層。然後，利用矽刻蝕打開主動溝 槽213b和終止溝槽213a，進入外延層210中。打開的溝 槽深度約為36至40微米，側壁角約為88度。終止溝槽 213a的寬度可能大於主動區溝槽213b，以保證如圖所示 的那樣’填充在這些溝槽中的氧化物到達溝槽底部。然 後’在溝槽213a和213b的侧壁上外延生長一個N-外延奈 米管層215 ’其厚度約為〇. 25至〇. 5微米，並用砷摻雜物 換雜’隨後在N-奈米管215上方外延生長一個P-外延層 216。如第34圖所示，在溝槽中沉積並填充有薄hdp氧化 層220。要注意的是’由於終止漢槽213a的寬度較大，雖 然P-外延層216充分了填充主動區域溝槽討3b的底部， 卻僅能填充終止溝槽2i3a的一薄層襯裏。因此，氧化層 220在終止溝槽2i3a中填充的深度遠小於在主動溝槽 213b中的深度。可在邊界區域使用又深又寬的氧化物填 充較寬溝槽，以便在同一半導體晶片上製備不同元件時 ，區分這些不同的元件。 [0037] 然後，利用背部刻蝕技術和/或化學機械平整化（c肝） 技術，除去頂面上的氧化層22G，直職切層212裸露 出來。這時’會在終止區中形成—個氧化立柱⑵的網路 ，在該網路中含有半導體臺面結構224。終止區覆蓋著寬 100106597 表單編號A0101 第20頁/共65頁 1003106142-0 201131774 Ο ο 溝槽213a，利用覆蓋著終止區的溝槽閘極掩膜218，刻蝕 主動區溝槽213b中的氧化層220。然後，如第35圖所示 ’沿P-外延層216的裸露側壁進行恥型植入，製備n —型 植入區217。如第36圖所示，藉由閘極氧化層225的襯墊 ，製備多晶矽閘極230。此時，可以除去主動區上的硬掩 膜212。然後’如上所述，形成p_本體基極區235和重p+ 區240利用源極掩膜（圖中沒有表示出），如上所述， 在主動單元區中，植入並形成N +源極區245，如第37圖所 示。在第38圖中，利用終止硬掩膜249，將溝槽閘極掩膜 218和剩餘的硬掩臈212一起除去。在第39圖中利用矽 刻#’刻敍半導體臺面結構224，即外延層210-1、 210-2和210-3，在終止區的氧化層220之間，留下臨時 刻蝕溝槽222。在第40圖中’用介質材料290填充在終止 區中的氧化層220之間的刻蝕溝槽222，以便填充終止區 中的刻蝕臺面結構，形成又深又寬的終止氧化溝槽289。 在第41圖中，除去終止硬掩膜249 ’進行如第29圖至第 31圖所示的後續處理技術，完;成帶有如第18圖所示之特 製終止區之MOSFET元件的製備。 [0038] 參閱第42圖為俯視圖，第43圖和第44圖分別為帶有平面 終止結構的如第42圖所示之MOSFET元件之沿A-A，線和B-B’線之剖面圖。為了清晰起見，雖然大體表示出了由金 屬層形成的電連接，但是俯視圖並沒有表示出金屬、氧 化物和純化層之頂部，如第18圖和第41圖所示，平面終 止是寬氧化溝槽的一個可選實施例。在平面終止結構中 ，終止區199’包含類似於主動區之臺面結構110’，臺面 100106597 表單編號A0101 第21頁/共65頁 1003106142-0 201131774 結構110’位於氧化層120’之間，用側壁填充在溝槽中， 並由N摻雜外延層115’覆蓋著。終止單元不具有主動單元 198’的源極/本體區135、140和145。相反，如第42圖 至第44圖所示，P -臺面結構和N -外延層由金屬層150-1 至150-5連接，以使每個終止單元閉鎖一個特定的夾斷電 壓VPT。鈍化層195’可以覆蓋金屬層150-1至15 0-5。 [0039] 最後一個主動單元（如圖中左側所示），在源極電壓為0 伏時，藉由金屬層150-1，短接至第一終止單元的P-臺面 結構（以及在中間的多晶矽塊130’）。更確切地說，金 屬層150-1連接了 P-區135’内的P+區140’。P-臺面結構 110’和周圍的N-外延層115’耗盡，將N-外延層的電壓升 高至夾斷電壓VPT1，即N-外延層和P-臺面結構耗盡時的 電壓。N-外延層115’連接到包圍著第一終止單元的N+區 140’’的N-區135’’上，第一終止單元的N+區140’’藉由 金屬層150-2短接至下一個終止單元（右侧的下一個單元 )的P-臺面結構上，由於在該單元中發生耗盡，使電壓 又升高了一個VPT1，從而使此時的總電壓為VPT2 2*VPT1。直到達到元件的工作電壓（汲極電壓）時，這 種情況才會停止。參見第45圖，首先將源極電位作為參 考電壓，例如金屬層150-1的V = 0，電壓以夾斷步階155 的漸進式的方式逐漸增加，使得金屬層150-2處的電壓為 VPT1。電壓遞增至VPT1，然後達到金屬層150-3處的 VPT2，最終升高到元件電壓，即在最後一個金屬層 150-η處的600伏預設電壓，如第45圖中最靠近半導體晶 片邊緣處的劃線所示。 100106597 表單編號Α0101 第22頁/共65頁 1003106142-0 201131774 [0040] [0041] Ο ο 在氧化溝槽120,内形成多㈣仙『，以防止電荷和于 物進入氧化溝槽中的氧化物，從而提高了Μ的可靠性 。由於平祕止結構與寬氧化料相比，需要更大的橫 向距離，以阻h作電壓，因此該平面終止結構不如第 18圖所示之寬氧化溝槽終止結構緊凑。更應注意的是， 與上述主動單元區中的溝槽類似，在終止區中打開用氣 化矽填充的溝槽，也帶有稍稍傾斜的侧壁。 參閱第46圖表示-種類似於第？圖所示之咖元件叫， 之剖面圖，該卿元件m，與類似於第㈣所示之 基元件162 ’相整合。帶有又深又寬氧化填充物i2i的寬 槽’將元件分開。在這種情況下，將㈣餘體背部研 磨到又深又寬的氧化填施21的底部。在半導體材料的 底部，植入N-型層108，和p一型層1〇5十。由於咖不 像嶋ET那樣具有嵌人式二極體，因此該實施例十分有 用應月痛的疋，如同美國專利申請號為12/似，⑽中 所述的那樣’料帶杨始外延層的單-P-基體進行背 部研磨和植錢K料種單— P-Μ似元件。如 第47圖所不’製備該結構也可以無需背部研磨，以便將 P型層150-1植入到一部分N_型半導體基體1〇8，，中 〇 [0042] 儘管本發明已經詳細⑽了現㈣較佳實施例 ，但不應 作為本發明的舰n儘管以上㈣所述的是Π-通 u元件仁疋本發明藉由將接雜區域的導電類型反轉， 也可用於P-通道元件。可以製備各種不同的元件，包含 那些帶有平面_的元件。本領域的技術人員閱 讀上述 100106597 表單編號A0101 $ 23頁/共65頁 1003106142-0 201131774 詳細說明後，各種變化和修正無疑將顯而易見。因此， 所附的申請專利範圍應涵蓋本發明的真實意圖和範圍内 的全部變化和修正。 [0043] 儘管本發明的内容已經藉由上述較佳實施例作了詳細介 紹，但應當認識到上述的描述不應被認為是對本發明的 限制。在本領域技術人員閱讀了上述内容後，對於本發 明的多種修改和替代都將是顯而易見的。因此，本發明 的保護範圍應由所附的申請專利範圍來限定。 【圖式簡單說明】 [0044] 第1圖表示現有一種垂直超級接面功率元件之傳統結構之 剖面透視圖。 第2圖表示現有一種垂直超級接面功率元件之傳統結構之 剖面圖。 第3圖表示本發明所述之帶有溝槽奈米管超級接面結構之 MOSFET元件之剖面圖。 第4圖至第6圖表示本發明所述之帶有交替溝槽奈米管超 級接面結構之MOSFET元件之剖.面圖。 第7圖表示本發明所述之帶有溝槽奈米管超級接面結構之 N-通道絕緣閘雙極電晶體（IGBT)元件之剖面圖。 第8圖和第9圖分別表示本發明所述之帶有溝槽奈米管超 級接面結構之電荷注入控制電阻器之剖面圖以及等效電 路圖。 第10圖為第8圖所示結構之俯視圖。 第11圖為第8圖所示結構之另一個剖面圖。 第12圖表示第3圖所示之MOSFET元件之另一個實施例之 100106597 表單編號A0101 第24頁/共65頁 1003106142-0 201131774 Ο G 剖面圖，該MOSFET元件帶有溝槽奈米管超級接面結構以 及三個不同掺雜濃度之外延層。 第13圖和第14圖表示兩種MOSFET元件之兩個局部透視圖 ，這兩種MOSFET元件都帶有本發明所述之溝槽奈米管超 級接面結構。 第15圖表示類似於第14圖所示之MOSFET元件之俯視圖。 第16圖和第17圖表示本發明所述之功率元件之封閉元件 結構之俯視圖。 第18圖表示本發明所述之MOSFET元件之剖面圖，該 MOSFET元件帶有溝槽奈米管超級接面結構以及專門配置 之終止區。 第19圖至第31圖為一系列表示第3圖所示之MOSFET元件 之製備過程之剖面圖。 第32圖至第41圖為一系列表示配置本發明所述之終止區 之製備過程之刳面圖。 第42圖為本發明所述之平面終止區之俯視圖； 第43圖和第44圖為其剖面圖； 第45圖表示整個終止區上夾斷步驟之電壓分佈。 第46圖和第47圖表示帶有肖特基元件之IGBT元件之剖面 圖。 [0045] 【主要元件符號說明】 100、 100-1、102、100-2、100-3 : MOSFET元件； 101、 101’ ： IGBT元件； 105 : N +基體； 105-1 : P-基體層； 100106597 105-1’、150-1’ ’ ： P-型層； 表單編號A0101 第25頁/共65頁 1003106142-0 201131774 108 : N-通道截止層； 108’ ： N-型層； 108’ ’ ： N-型半導體基體； 110’ ： P-臺面結構； 110 :外延層； 110-1、110-2、110-3 : P-摻雜層； 115 :溝槽奈米管； 115- 3 : N +外延層； 115’ ： N -外延層； 116、116-2、116-3、216 : P-外延層； 116- 1 : N--外延層； 117 ' 217 : N-型植入區； 120、121、120-2、120-3 :氧化填充物； 120’ ：氧化溝槽； 12 2 :不連續區； 125 :閘極氧化層； 130 :溝槽閘極； 130’ ：多晶矽塊； 135 :本體區； 135’、175 : P-區； 135’ ’、165 : N-區； 140、240 : P +本體接觸區； 140’、176 : P+區； 140, ’ ： N+區； 145、245 : N +源極區； 150 :阻擋金屬層； 100106597 表單編號A0101 第26頁/共65頁 1003106142-0 201131774 150-1、150-2、150-3、150-4、150-5、150-n :金屬 層； 1 5 5 .源極電極， 160 :閘極電極； 161 : P-N接面二極體； 162 :肖特基二極體； 162’ ：肖特基元件； 163 :可調電阻器R1 ; 170 :肖特基接觸金屬； 189 :終止溝槽； 190 :介質層； 19 5 :鑛齒街區； 1 9 5 ’ ··鈍化層； 198’ ：主動單元； 199’ ：終止區； 205 : N +半導體基體； 215 : N-奈米管層； 210 : P-型外延層； 200 :超級結奈米管MOSFET ; 205-D :汲極金屬； 210-1、210-2、210-3 :外延層； 211 :氧化層； 212 :氮化石夕（Si3N4)層； 213 :溝槽； 213a :終止溝槽； 213b :主動溝槽； 100106597 表單編號A0101 第27頁/共65頁 1003106142-0 201131774 218 :溝槽閘極掩膜； 220 :氧化層； 222 :刻蝕溝槽； 223 :氧化立柱； 224 :半導體臺面結構； 225 :閘極氧化層； 2 3 0 :閘極多晶石夕層； 235 :本體區； 249 :終止硬掩膜； 250 :鈍化層； 260-S :源極金屬； 289 :終止氧化溝槽； 290 :介質材料；以及 A_A，' B- B :線0 100106597 表單編號A0101 第28頁/共65頁 1003106142-0Not shown), a pattern of source metal 260_8 and gate pad (not shown) is formed on the metal layer. A metal layer is also formed at the bottom of the substrate 205 to prepare a germanium: polar metal 205-D, thereby completing the entire super junction nanotube MOSFET 200. [0036] Referring to Figures 32 through 41, a series of side cross-sectional views 'representing a process for preparing a termination region of a self-aligned high voltage (HV) semiconductor power device having a nanotube as shown in Fig. 3. Figure 32 shows an initial N + semiconductor substrate 205 (e.g., a heavily N + doped germanium substrate) carrying a p-type epitaxial layer 210 'P-type epitaxial layer 210 as layers 210-1, a 2, and 21 0-3. Three 100106597 Form No. A0101 Page 19 of 65 1003106142-0 201131774 Different doping concentrations are grown above the substrate 205. The grown p-type epitaxial layer 21 can also have a gradually graded doping concentration whose doping concentration gradually decreases from top to bottom. Then, an oxide layer and a nitride (Si/4) layer 2i2' are formed as a hard mask. In Fig. 33, using a trench mask (not shown), the hard mask 212 is first etched to include an oxide layer and a tantalum nitride layer. Then, the active trench 213b and the termination trench 213a are opened by germanium etching to enter the epitaxial layer 210. The open trench depth is approximately 36 to 40 microns and the sidewall angle is approximately 88 degrees. The width of the termination trench 213a may be greater than the active region trench 213b to ensure that the oxide filled in the trenches reaches the bottom of the trench as shown. Then, an N- epitaxial nanotube layer 215' is epitaxially grown on the sidewalls of the trenches 213a and 213b, and has a thickness of about 0.25 to 1.5 μm, and is replaced with an arsenic dopant, followed by N-na A P- epitaxial layer 216 is epitaxially grown over the rice tube 215. As shown in Fig. 34, a thin hdp oxide layer 220 is deposited and filled in the trench. It is to be noted that since the width of the termination groove 213a is large, although the P- epitaxial layer 216 sufficiently fills the bottom of the active region trench 3b, it can only fill a thin layer liner of the termination trench 2i3a. Therefore, the depth of the oxide layer 220 filled in the termination trench 2i3a is much smaller than that in the active trench 213b. A wider and wider oxide can be used in the boundary region to fill the wider trenches to distinguish between the different components when the different components are fabricated on the same semiconductor wafer. [0037] Then, using the back etching technique and/or the chemical mechanical planarization (c-hepatic) technique, the oxide layer 22G on the top surface is removed, and the straight-cut layer 212 is exposed. At this time, a network of oxidized columns (2) is formed in the termination region, and a semiconductor mesa structure 224 is included in the network. The termination area is covered by the width 100106597. Form No. A0101 Page 20 / Total 65 Page 1003106142-0 201131774 Ο ο The trench 213a etches the oxidation in the active region trench 213b by using the trench gate mask 218 covering the termination region Layer 220. Then, as shown in Fig. 35, the n-type implanted region 217 is prepared by performing a smear implant along the bare sidewall of the P- epitaxial layer 216. As shown in Fig. 36, the polysilicon gate 230 is prepared by the pad of the gate oxide layer 225. At this point, the hard mask 212 on the active area can be removed. Then, as described above, the p_body base region 235 and the heavy p+ region 240 are formed using a source mask (not shown), and as described above, the N + source is implanted and formed in the active cell region. Area 245, as shown in Figure 37. In Fig. 38, the trench gate mask 218 is removed together with the remaining hard mask 212 by terminating the hard mask 249. The semiconductor mesas 224, i.e., epitaxial layers 210-1, 210-2, and 210-3, are patterned in FIG. 39 by engraving #', leaving a temporary etched trench 222 between the oxide layers 220 of the termination region. . In FIG. 40, the etched trench 222 between the oxide layers 220 in the termination region is filled with a dielectric material 290 to fill the etched mesa structure in the termination region to form a deep and wide termination oxidization trench 289. . In Fig. 41, the termination of the hard mask 249' is performed to carry out the subsequent processing techniques as shown in Figs. 29 to 31, and the fabrication of the MOSFET element with the special termination region as shown in Fig. 18 is completed. Referring to Fig. 42, a plan view, Fig. 43 and Fig. 44 are cross-sectional views taken along line A-A, line and B-B' of the MOSFET element shown in Fig. 42 with a planar termination structure, respectively. For the sake of clarity, although the electrical connections formed by the metal layers are generally shown, the top views do not show the tops of the metal, oxide and purification layers, as shown in Figures 18 and 41, the planar termination is broad oxidation. An alternative embodiment of the trench. In the planar termination structure, the termination region 199' includes a mesa structure 110' similar to the active region, mesa 100106597 Form No. A0101 Page 21 / Total 65 Page 1003106142-0 201131774 Structure 110' is located between the oxide layers 120' with sidewalls Filled in the trenches and covered by an N-doped epitaxial layer 115'. The termination unit does not have the source/body regions 135, 140 and 145 of the active unit 198'. In contrast, as shown in Figs. 42 to 44, the P-mesa structure and the N- epitaxial layer are connected by the metal layers 150-1 to 150-5 so that each termination unit blocks a specific pinch-off voltage VPT. The passivation layer 195' may cover the metal layers 150-1 to 150-5. [0039] The last active cell (shown on the left side of the figure), shorted to the P-mesa structure of the first termination unit (and in the middle) by the metal layer 150-1 when the source voltage is 0 volts Polycrystalline germanium block 130'). More specifically, the metal layer 150-1 is connected to the P+ region 140' in the P-region 135'. The P-mesa structure 110' and the surrounding N- epitaxial layer 115' are depleted, raising the voltage of the N- epitaxial layer to the pinch-off voltage VPT1, that is, the voltage at which the N- epitaxial layer and the P-mesa structure are depleted. The N- epitaxial layer 115' is connected to the N-region 135'' surrounding the N+ region 140" of the first termination unit, and the N+ region 140" of the first termination unit is shorted to the lower by the metal layer 150-2. On the P-mesa structure of a termination unit (the next unit on the right side), the voltage is increased by a VPT1 due to depletion in the unit, so that the total voltage at this time is VPT2 2*VPT1. This will not stop until the component's operating voltage (bungee voltage) is reached. Referring to Fig. 45, first, the source potential is used as a reference voltage, for example, V = 0 of the metal layer 150-1, and the voltage is gradually increased in a progressive manner of the pinch-off step 155, so that the voltage at the metal layer 150-2 is VPT1. The voltage is increased to VPT1, then to VPT2 at metal layer 150-3, and finally raised to the component voltage, ie the 600 volt preset voltage at the last metal layer 150-n, as in Figure 45, closest to the edge of the semiconductor wafer The line is shown. 100106597 Form No. 1010101 Page 22 of 65 1003106142-0 201131774 [0041] 004 ο In the oxidized trench 120, a plurality of (four) cents are formed to prevent charges and substances from entering the oxide trench. , thereby improving the reliability of the cockroach. Since the flat-finishing structure requires a larger lateral distance than the wide oxidizing material to resist the voltage, the planar termination structure is not as compact as the wide oxidizing trench termination shown in Fig. 18. It should be noted that, similar to the grooves in the active cell region described above, the trench filled with vaporized helium is opened in the termination region, also with slightly inclined sidewalls. See Figure 46 for a description - similar to the first? The coffee element shown in the figure is a cross-sectional view of the unit element m, which is integrated with a base member 162' similar to that shown in the fourth item. The wide groove 'with a deep and wide oxidized filler i2i separates the elements. In this case, the back of the (iv) body is ground to the bottom of a deep and wide oxidizing fill 21 . At the bottom of the semiconductor material, an N-type layer 108 is implanted, and a p-type layer is 1 〇5 。. Since the coffee does not have an embedded diode like the 嶋ET, this embodiment is very useful for the pain of the monthly pain, as described in the U.S. Patent Application No. 12/, as described in (10). The single-P-matrix is used for back grinding and planting of K-stocks - P-like components. As shown in Fig. 47, the structure may be prepared without back grinding to implant the P-type layer 150-1 into a portion of the N-type semiconductor substrate 1〇8, which is detailed (10). Now, the preferred embodiment, but not as the ship n of the present invention, although the above (4) is a Π-通 u element, the present invention can also be used for the P-channel by inverting the conductivity type of the impurity-receiving region. element. A variety of different components can be prepared, including those with a planar _. Those skilled in the art will read the above 100106597 Form No. A0101 $23 pages/ Total 65 pages 1003106142-0 201131774 After the detailed description, various changes and modifications will undoubtedly be apparent. Accordingly, the appended claims are intended to cover all such modifications and modifications Although the present invention has been described in detail by the preferred embodiments thereof, it should be understood that the description Various modifications and alterations of the present invention will be apparent to those skilled in the art. Therefore, the scope of the invention should be limited by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS [0044] Fig. 1 is a cross-sectional perspective view showing a conventional structure of a conventional vertical super junction power element. Figure 2 is a cross-sectional view showing a conventional structure of a conventional vertical super junction power element. Fig. 3 is a cross-sectional view showing a MOSFET device having a trench junction super junction structure according to the present invention. 4 to 6 are cross-sectional views showing the MOSFET device of the present invention having a super-junction structure of alternating trench nanotubes. Figure 7 is a cross-sectional view showing an N-channel insulated gate bipolar transistor (IGBT) device having a trench nanotube super junction structure according to the present invention. Fig. 8 and Fig. 9 respectively show a cross-sectional view and an equivalent circuit diagram of a charge injection control resistor having a trench nanotube super junction structure according to the present invention. Figure 10 is a plan view of the structure shown in Figure 8. Figure 11 is another cross-sectional view of the structure shown in Figure 8. Figure 12 shows another embodiment of the MOSFET device shown in Figure 3, 100106597, Form No. A0101, Page 24/65, 1003106142-0, 201131774 Ο G, cross-section of the MOSFET device with trench nanotubes The face structure and the three different doping concentrations are extended. Figures 13 and 14 show two partial perspective views of two MOSFET elements, both of which have the trench nanotube super junction structure of the present invention. Fig. 15 shows a plan view similar to the MOSFET element shown in Fig. 14. Fig. 16 and Fig. 17 are plan views showing the structure of the closing member of the power element of the present invention. Figure 18 is a cross-sectional view showing the MOSFET device of the present invention having a trench nanotube super junction structure and a specially configured termination region. Fig. 19 through Fig. 31 are cross-sectional views showing a series of processes for forming a MOSFET device shown in Fig. 3. Figures 32 through 41 are a series of cross-sectional views showing the preparation process for configuring the termination region of the present invention. Figure 42 is a plan view of the planar termination region of the present invention; Figures 43 and 44 are cross-sectional views thereof; and Figure 45 is a view showing the voltage distribution of the pinch-off step over the entire termination region. Figures 46 and 47 show cross-sectional views of IGBT elements with Schottky elements. [Description of main component symbols] 100, 100-1, 102, 100-2, 100-3: MOSFET component; 101, 101': IGBT component; 105: N + substrate; 105-1 : P-base layer 100106597 105-1', 150-1' ' : P-type layer; Form No. A0101 Page 25 of 65 1003106142-0 201131774 108 : N-channel cut-off layer; 108': N-type layer; 108' ' : N-type semiconductor substrate; 110' : P-mesa structure; 110 : epitaxial layer; 110-1, 110-2, 110-3: P-doped layer; 115: trench nanotube; 115- 3 : N + epitaxial layer; 115' : N - epitaxial layer; 116, 116-2, 116-3, 216: P- epitaxial layer; 116-1 : N-- epitaxial layer; 117 ' 217 : N-type implant Zone; 120, 121, 120-2, 120-3: oxidized filler; 120': oxidized trench; 12 2: discontinuous region; 125: gate oxide layer; 130: trench gate; 130': polysilicon Block; 135: body region; 135', 175: P-zone; 135'', 165: N-zone; 140, 240: P + body contact zone; 140', 176: P+ zone; 140, ': N+ zone ; 145, 245: N + source region; 150: barrier metal layer; 100106597 Form No. A0101 Page 26 of 65 1003106142-0 201131774 150-1, 150-2, 150-3, 150-4, 150-5, 150-n: Metal layer; 1 5 5 . Source electrode, 160 : gate electrode; 161: PN junction diode; 162: Schottky diode; 162': Schottky component; 163: adjustable resistor R1; 170: Schottky contact metal; Trench; 190: dielectric layer; 19 5: mineral tooth block; 1 9 5 '··passivation layer; 198': active unit; 199': termination region; 205: N + semiconductor substrate; 215: N-nano tube Layer; 210: P-type epitaxial layer; 200: super junction nanotube MOSFET; 205-D: germanium metal; 210-1, 210-2, 210-3: epitaxial layer; 211: oxide layer; 212: nitride Xi (Si3N4) layer; 213: trench; 213a: termination trench; 213b: active trench; 100106597 Form No. A0101 Page 27 of 65 1003106142-0 201131774 218: Trench gate mask; 220: Oxidation Layer; 222: etched trench; 223: oxidized column; 224: semiconductor mesa structure; 225: gate oxide layer; 2 3 0: gate polycrystal layer; 235: body region; 249: termination of hard mask 250: passivation layer; 260-S: a source of metal; 289: terminating trench oxide; 290: dielectric material; A_A, 'B- B: Line Form Number A0101 0100106597 page 28/65 Total 1003106142-0

Claims (1)

201131774 七、申請專利範圍： 1 , 一種帶有溝槽-氧化物—奈米管超級接面之元件結構，其包 含： 第、電類型之一第一半導體層以及第二導電類型之一第 二半導體層，該第二半導體層沉積在該第一半導體層之上 方； 在該第二半導體層中打開之一溝槽，垂直延伸到該第一半 導體層； 〇 形成在該溝槽之側壁上的第一導電類型之一第一外延層； 以及 形成在該第一外延層上之一第二外延層； 其中該第-外延層與相鄰的半導體區域之間達到充分的電 4平衡。 ^ 2 .如申請專圍第㈣所述之元件結構，襄中在至少某些 該溝槽中，該第二辆層轻料了錢該第—外延層料 據的縫隙之底部。 〇 3.如申請專利範圍第2項所述之元件結構，其中該第二外延 層之侧壁朝著該溝槽之底部合彳并在一起。 4.如申請專利範圍第i項所述之元件結構，其中該溝槽之側 2具有—定㈣度，料絲形溝槽，軸著該 面匯聚。 - 5 · 7請專利範圍第i項所述之元件結構，其中該第二外延 層為第一導電類型。 6·=請專利範圍第i項所述之元件結構，其中該第二外延 為第二導電類型或本質半導體材料。 100106597 表單編號A0101 第29頁/共65頁 1003106142-0 201131774 /·如申請專利範圍第丨項所述之元件結構，其更包含： 在—中心縫隙中之-第-電介質填充物，該中心縫隙在該 溝槽的中心，未被該第二外延層佔據。 8.如申請專利範圍第丨項所述之元件結構，其更包含： —閘極電極，其沉積在至少某些該溝槽頂部中。 9·如申請專利範圍第8項所述之元件結構，其更包含： 位於該閘極電極下方很深之一介質層。 10 .如申請專利範圍第1項所述之元件結構，其更包含： 形成在相鄰該溝槽之間之—肖特基二極體和一 p_N接面二 極體。 11 .如申請專利範圍第1〇項所述之元件結構，其中該p_N接面 二極體是-電荷注人可控二極艘，其與—電荷注入可控電 阻器串聯’並與該肖特基二極體並聯。 12.如申請專利範圍第1項所述之元件結構，其中該第二半導 體層在兩個相鄰該溝槽之間的寬度，遠大於該第一外延層 的寬度。 13 ·如申請專利範圍第1項所述之元件結構，其中該第二半導 體層在兩個相鄰該溝槽之Μ的寬度，至少是該第一外延層 的寬度的三倍。 14 . 15 . 16 . 17 . 100106597 如申請專利範圍第1項所述之元件結構，其中該元件結構 更包含一金屬氧化物半導體場效電晶體（M〇SFET)。 如申請專利範圍第1項所述之元件結構，其中該元件結構 更包含一絕緣閘雙極電晶體（IGBT)。 如申請專利範圍第1項所述之元件結構，其中該元件結構 更包含與一二極體整合的一絕緣閘雙極電晶體（igbt)。 如申請專利範圍第1項所述之元件結構，其中該第二半導 表單編號A0101 第30頁/共65頁 1003106142-0 201131774 體層具有分級之摻雜結構，其摻雜濃度從上到下逐漸降低 〇 18 . 19 . 〇 20 . 21 . 22 . 〇 如申請專利範圍第7項所述之元件結構，其更包含： 具有介質溝槽之一終止結構，其包含由該第一介質填充物 和一第二介質填充物形成之一介質立柱之一網路，該第一 介質填充物和該第二介質填充物形成在該網路内該介質立 柱之間。 如申請專利範圍第7項所述之元件結構，其中至少一第二 元件沉積在半導體基體上，其中沉積在相鄰元件之間之該 溝槽具有較大的溝槽寬度。 如申請專利範圍第1項所述之元件結構，其中該元件結構 更包含具有條紋結構之電晶體單元。 如申請專利範圍第1項所述之元件結構，其中該元件結構 更包含具有封閉式單元佈局之電晶體單元。 如申請專利範圍第1項所述之元件結構，其更包含： . . ,： j 由一終止單元陣列構成之一終立區，在主動單元之介面處 帶有一第一終止單元，其中終i單;元更包含： 該第二半導體層之一臺面結構，& 該第一外延層形成在 其側壁上，該第二外延層形成在該第一外延層上，該臺面 結構靠近帶有介質填充物之該溝槽； 第一導電類型之一第一區域，形成在該臺面結構之頂面中 ;以及 第二導電類型之一第二區域，形成在該臺面結構之頂面中 ，與該臺面結構中之該第一區域分開， 其中大多數該終止單元之該第一區域都電連接到相鄰該終 止單元之該第二區域上。 100106597 表單編號 A0101 第 31 頁/共 65 頁 1003106142-0 201131774 Μ .-種帶有溝槽-氧化物-奈米管超級接面之元件結構之製備 方法，其包含： 在第二導電類型之-第二半導體層中刻餘—溝槽； 在該溝槽中，生長第-導電類型之一第一外延層；以及 在該第一外延層之上方，生長一第二外延層； 其中第一導電類型之一第—半導體層位於該第二半導體層 之下方，以及 其中該第一外延層觸及該第一半導體層。 Μ ·如申請專利範圍第23項所述之製備方法其中該第一外延 層與周圍之半導體區域達到電荷平衡。 25 .如申請專利範圍第23項所述之製傷方法，其中生長該第二 外延層，使該第二外延層充分填充該溝槽之底部^ Μ.如申請專利範圍第23項所述之製備方法，其更包含： 生長該第二外延層後，用一電介質填充該溝槽中剩餘之一 縫隙。 27·如申請專利範圍第26項所述之製備方法，其更包含： 用該電介質填充該溝槽中剩餘之痛隙後，背部刻脑電 介質，並在至少某些該溝槽之頂部中形成一溝槽閉極電極 〇 28.如申請專利範圍第26項所述之製備方法，其更包含： 在刻姓該溝槽時，同時刻钱一終止區中之該溝槽，以便用 留在介質填充溝槽之間之-半導體臺面結構，在該終止區 中形成介質填充溝槽之網路；以及 刻勉掉該終止區中之該半導體臺面結構，並用一第二介質 填充物填充空間，以便在該終止區中形成又寬又深之一電 介質溝槽。 100106597 表單編號A010〗 第32頁/共65頁 1003106142-0 201131774 29. —種製備電介質溝槽之方法，其包含： 在一半導體層中製備一溝槽之一網路，並用一第一電介質 填充該溝槽，以便形成含有一半導體臺面結構之一電介質 立柱之網路； 刻钱掉該電介質立柱之網路内之該半導體臺面結構，並用 —第二電介質填充縫隙，從而構成又寬又深之一電介質溝 槽。 〇201131774 VII. Patent application scope: 1. An element structure with a trench-oxide-nano tube super junction, comprising: a first semiconductor layer of a first type, an electrical type, and a second one of a second conductivity type a semiconductor layer, the second semiconductor layer is deposited over the first semiconductor layer; a trench is opened in the second semiconductor layer, extending perpendicularly to the first semiconductor layer; and germanium is formed on sidewalls of the trench a first epitaxial layer of a first conductivity type; and a second epitaxial layer formed on the first epitaxial layer; wherein a sufficient electrical 4 balance is achieved between the first epitaxial layer and an adjacent semiconductor region. ^ 2 . If the component structure described in the fourth paragraph is applied, in the at least some of the grooves, the second layer is lightly fed to the bottom of the gap of the first epitaxial layer. 3. The device structure of claim 2, wherein the sidewalls of the second epitaxial layer are joined together toward the bottom of the trench. 4. The component structure of claim i, wherein the side 2 of the trench has a predetermined (four) degree, a wire-shaped groove, on which the axis converges. - 5 - 7 The component structure described in the scope of claim 4, wherein the second epitaxial layer is of a first conductivity type. 6·= The component structure described in the scope of claim i, wherein the second epitaxy is a second conductivity type or an intrinsic semiconductor material. 100106597 Form No. A0101 Page 29 of 65 1003106142-0 201131774 / The component structure as described in the scope of the patent application, further comprising: a - dielectric filler in the center gap, the central gap At the center of the trench, it is not occupied by the second epitaxial layer. 8. The component structure of claim 2, further comprising: - a gate electrode deposited in at least some of the top of the trench. 9. The component structure of claim 8, further comprising: a dielectric layer located deep below the gate electrode. 10. The component structure of claim 1, further comprising: a Schottky diode and a p_N junction diode formed between adjacent trenches. 11. The component structure of claim 1, wherein the p_N junction diode is a charge-chargeable controllable dipole, which is connected in series with a charge injection controllable resistor. The special base diodes are connected in parallel. 12. The component structure of claim 1, wherein the width of the second semiconductor layer between two adjacent trenches is much greater than the width of the first epitaxial layer. The element structure of claim 1, wherein the width of the second semiconductor layer between two adjacent trenches is at least three times the width of the first epitaxial layer. 14.15.16.17. 100106597 The component structure of claim 1, wherein the component structure further comprises a metal oxide semiconductor field effect transistor (M〇SFET). The component structure of claim 1, wherein the component structure further comprises an insulated gate bipolar transistor (IGBT). The component structure of claim 1, wherein the component structure further comprises an insulating gate bipolar transistor (igbt) integrated with a diode. The component structure as described in claim 1, wherein the second semi-conductive form number A0101 is 30 pages/65 pages 1003106142-0 201131774 The body layer has a graded doping structure, and the doping concentration gradually increases from top to bottom. 〇20. 21 . 22 . The component structure of claim 7, further comprising: a termination structure having a dielectric trench comprising the first dielectric filler and A second dielectric fill forms a network of one of the dielectric posts, the first dielectric fill and the second dielectric fill being formed between the media posts within the network. The element structure of claim 7, wherein at least one of the second elements is deposited on the semiconductor substrate, wherein the trench deposited between adjacent elements has a larger trench width. The element structure of claim 1, wherein the element structure further comprises a transistor unit having a stripe structure. The component structure of claim 1, wherein the component structure further comprises a transistor unit having a closed cell layout. The component structure as described in claim 1, further comprising: . . , : j consisting of a termination unit array, and a first termination unit at the interface of the active unit, wherein The unit further includes: a mesa structure of the second semiconductor layer, & the first epitaxial layer is formed on a sidewall thereof, and the second epitaxial layer is formed on the first epitaxial layer, the mesa structure is close to the medium a trench of the filler; a first region of a first conductivity type formed in a top surface of the mesa structure; and a second region of a second conductivity type formed in a top surface of the mesa structure, and The first region of the mesa structure is separated, wherein a majority of the first region of the termination unit is electrically coupled to the second region adjacent the termination unit. 100106597 Form No. A0101 Page 31 of 65 1003106142-0 201131774 Μ - A method for preparing a component structure with a trench-oxide-nanotube super junction, comprising: in the second conductivity type - Depositing a trench in the second semiconductor layer; growing a first epitaxial layer of a first conductivity type in the trench; and growing a second epitaxial layer over the first epitaxial layer; wherein the first conductive layer One of the types of semiconductor layers is located below the second semiconductor layer, and wherein the first epitaxial layer contacts the first semiconductor layer. The preparation method of claim 23, wherein the first epitaxial layer and the surrounding semiconductor region are in charge balance. The method of claim 23, wherein the second epitaxial layer is grown such that the second epitaxial layer sufficiently fills the bottom of the trench. As described in claim 23 The preparation method further includes: after growing the second epitaxial layer, filling a gap in the trench with a dielectric. The preparation method of claim 26, further comprising: filling the remaining pain gap in the trench with the dielectric, engraving the brain dielectric on the back, and forming a top in at least some of the trenches The method of preparing the method of claim 26, further comprising: engraving the trench in the termination region at the same time as the trench is inscribed in the trench, so as to remain in the medium Filling a semiconductor mesa structure between the trenches, forming a network of dielectric filled trenches in the termination region; and engraving the semiconductor mesa structure in the termination region and filling the space with a second dielectric fill so that A wide and deep dielectric trench is formed in the termination region. 100106597 Form No. A010〗 Page 32 of 65 1003106142-0 201131774 29. A method of preparing a dielectric trench, comprising: preparing a network of trenches in a semiconductor layer and filling with a first dielectric The trench is formed to form a network comprising a dielectric pillar of a semiconductor mesa structure; the semiconductor mesa structure in the network of the dielectric pillar is engraved, and the gap is filled with a second dielectric to form a wide and deep A dielectric trench. 〇 100106597 表單編號A0101 第33頁/共65頁 1003106142-0100106597 Form No. A0101 Page 33 of 65 1003106142-0
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