CN104377238B - Configurations and methods for manufacturing devices with trench-oxide-nano-tube super-junctions - Google Patents

Configurations and methods for manufacturing devices with trench-oxide-nano-tube super-junctions Download PDF

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Publication number
CN104377238B
CN104377238B CN201410765884.XA CN201410765884A CN104377238B CN 104377238 B CN104377238 B CN 104377238B CN 201410765884 A CN201410765884 A CN 201410765884A CN 104377238 B CN104377238 B CN 104377238B
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groove
epitaxial layer
layer
device architecture
epitaxial
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CN104377238A (en
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哈姆扎·依玛兹
马督儿·博德
李亦衡
管灵鹏
王晓彬
陈军
安荷·叭剌
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Alpha and Omega Semiconductor Cayman Ltd
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Alpha and Omega Semiconductor Inc
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Abstract

This invention discloses a semiconductor power device disposed on a semiconductor substrate of a first conductivity type. The semiconductor substrate supports an epitaxial layer of a second conductivity type thereon wherein the semiconductor power device is supported on a super-junction structure. The super-junction structure comprises a plurality of trenches opened from a top surface in the epitaxial layer; wherein each of the trenches having trench sidewalls covered with a first epitaxial layer of the first conductivity type to counter charge the epitaxial layer of the second conductivity type. A second epitaxial layer may be grown over the first epitaixial layer. Each of the trenches is filled with a non-doped dielectric material in a remaining trench gap space. Each of the trench sidewalls is opened with a tilted angle to form converging U-shaped trenches.

Description

Device architecture with groove-oxide-nanotube super junction and preparation method
This case is divisional application
Original bill denomination of invention：Device architecture with groove-oxide-nanotube super junction and preparation method
Original bill application number：201110054042.X
The original bill applying date：On 2 28th, 2011
Technical field
The invention mainly relates to semiconductor power device, it more particularly relates to carry the groove of trenched side-wall The structure and preparation method of nanotube, wherein with the epitaxial layer covering groove side wall of doping, then filling groove with insulant Side wall, so that the semiconductor power device of measurable charge balance is neatly prepared with simplified preparation technology, while obtaining High-breakdown-voltage and very low resistance.
Background technology
Although with regard to the semiconductor device with vertical super-junction structures, in order to improve its electrology characteristic, existing many special Sharp information and disclosed technological document, but the association area of the design and preparation in super junction-semiconductor device, still deposit Limit to preparing in many technical barriers.More precisely, modal super-junction device includes MOS field Effect pipe (MOSFET) and igbt, with regard to these devices, existing many published patent information, comprising U.S. State's patent 5,438,215,5,216,275,4,754,310,6,828,631.Rattan flat (Fujihira) exists《Quasiconductor super junction device Part is theoretical》In (Japanese Applied Physics bulletin, volume 36, in October, 1997,6254-6262 page) book, it is proposed that vertical super junction The structure of device.More precisely, rattan puts down the Fig. 2 in the paper delivered illustrates a kind of vertical trench MOSFET super junction device Part, is hereby incorporated as Fig. 1 (1A).Rattan is flat also to propose a kind of with drift region vertical half in United States Patent (USP) 6,097,063 Conductor device, when device is in closed mode, has drift electric current to flow through in drift region, when device is in Disconnected mode, drift Drift electric current in stream area exhausts.The drift plot structure for being formed is the discrete drift region with multiple first conduction types, And the marker space of multiple second conduction types, wherein each marker space is all located in the adjacent drift region of difference, in parallel to be formed P-n junction.United States Patent (USP) 6,608,350 proposes a kind of vertical super-junction device, fills in the trench with layer of dielectric material, beautiful State's patent 5,981,996 is as shown in Fig. 2 (1B), it is proposed that a kind of vertical trench MISFET device.
However, in the structure and service behaviour of super-junction device described in these patented technologies and disclosure, still So there is many technology limitations, so as to limit these devices effectiveness in actual applications.The difficulty of conventional Super junction device Inscribe and the table top near filling of the limitation comprising deep trench, the size limitation of formation nanotube in the trench, holding terminator Charge balance, undamped inductive switching (UIS) scarce capacity of super-junction device, the vibration of super junction power device at region is asked N and P impurity in topic, the high manufacturing cost that super-junction device is slowly caused due to epitaxial growth speed, super-junction structures is in height The lower phase counterdiffusion of temperature, very big etc. the phase of termination area when being difficult to integrated different device and high-voltage applications on the same chip Close technical problem.
Therefore, in the design and preparation field of power semiconductor, it is necessary to which proposition forms the novelty of power device Device architecture and preparation method, so as to solve above-mentioned difficulties with limitation.
The content of the invention
Therefore, one aspect of the present invention be propose it is a kind of it is new, improvement device architecture and preparation method, by Trenched side-wall and bottom, grow a thin n-type doping epitaxial layer (such as arsenic epitaxial layer), are not filled up completely with or are partially filled with Groove, then side grows the second epitaxial layer on the first epitaxial layer, and is stitched with remaining composition of dielectric material filling of undoped Gap, during so as to solving to fill deep trench with epitaxial layer, frequently problem in traditional preparation method.Second epitaxial layer can be with The bottom of remaining groove gap is sufficient filling with, such that it is able to the more easily deposits dielectric materials in gap.
Another aspect of the present invention is, it is proposed that a kind of new, the device architecture of improvement with super-junction structures And preparation method, using charge balance concept, by nano tube structure, Rds, and element spacing very little are reduced, it is micro- to obtain 6 The 600V MOSFET of rice spacing, its conducting resistance rate are less than 9 milliohms/cm2.Which solves for during high tension apparatus for height The restriction of Rds.
Another aspect of the present invention is, it is proposed that a kind of new, the device architecture of improvement with super-junction structures And preparation method, the structure utilizes larger spacing and narrow N- epitaxial layers, and utilizes at the interdigital end of each active component Single element of the end with relatively large radius, keeps charge balance in the end of active region mesa structure.
Another aspect of the present invention is, it is proposed that a kind of new, the device architecture of improvement with super-junction structures And preparation method, super-junction structures are prepared in an epitaxial layer with doping content classification, such as on a N+ substrate P epitaxial layers are formed with three steps, is forced and is punctured generation in the relatively low part of drift region, so as to improve super junction MOSEFT device The UIS performances of part.
Another aspect of the present invention is, it is proposed that a kind of new, the device architecture of improvement with super-junction structures And preparation method, thick dielectric area is located at below gate electrode, to reduce gate-drain capacitance Crss, so as to solve super junction power device Oscillation problem.
Another aspect of the present invention is, it is proposed that a kind of new, the device architecture of improvement with super-junction structures And preparation method, by growing a thin simple layer N- epitaxial layer (thickness range of 0.1-1.0 microns), it is partially filled with ditch Groove, and remaining deep trench is filled with dielectric/oxide, so as to solve as in deep trench, epitaxial growth is slow, and cause Super-junction device high manufacturing cost problem.Additionally, lightly doped N-type epitaxy layer can be grown after N- epitaxial layers, Before remaining deep trench is filled with dielectric/oxide, groove is sufficient filling with, this is conducive to more easily being filled out with oxide Fill groove.
Another aspect of the present invention is, it is proposed that a kind of new, the device architecture of improvement with super-junction structures And preparation method, be formed about a very thin N-type nanotube layer in wider P-type region, and with wider P-type region Domain charge balance；As an example, three times relatively wide of P-type region field width of N-type nanotube layer, causes the doping content of boron to compare N-type N-type doping content in nanotube region is low three times.Therefore, limited boron can only be allowed to diffuse into N-type nanometer area under control, from And compensate unnecessary arsenic electric charge.Heavy N-type doping (such as arsenic or antimony) of N-type nanotube region, too will not move, so as to not P-type region is diffused in a large number can.Which solves at high temperature, the problem brought by N and P impurities phase counterdiffusion.
Another aspect of the present invention is, it is proposed that a kind of new, the device architecture of improvement with super-junction structures And preparation method, increase the trench region width at the first device demarcation line, such as a MOSFET element and one Second device (such as Schottky diode), is to be sufficient filling with big trench region with dielectric material --- it is different from active device, Active device is sufficient filling with silicon, then with silicon oxide (oxide or SiO2) filling remainder.Therefore, different devices can To be more easily integrated on same silicon.
Another aspect of the present invention is, it is proposed that a kind of new, the device architecture of improvement with super-junction structures And preparation method, a Schottky diode injection P-N diode controlled with is integrated, so as to reduce two The recovery charge of pole pipe, reduces the leakage current of high tension apparatus.
Another aspect of the present invention is, it is proposed that a kind of new, the device architecture of improvement with super-junction structures And preparation method, high pressure (HV) Schottky diode and a controlled injection P-N diode are integrated in into same silicon On chip, used as an igbt (IGBT), the wherein back side of IGBT carries emitter stage (for N- passage devices For be P-type) implantation.Lack a difficult problem for embedded type diode so as to solve IGBT structure.
Another aspect of the present invention is, it is proposed that a kind of termination structure of new, improvement, prepares wide medium groove Method is first by forming a SiO2Network, then etches away SiO2Silicon mesa structure in network, and use self-rotary glass Glass, HDP or polyimides, fill the region for just having etched away, carry out, depending on selected medium before or after metallization The type of material.Due to preparing suffered restriction, it is difficult to prepare not only wide but also deep medium ditch with traditional etching and fill method Groove, but the two-stage process of the present invention can utilize the preparation technology of standard, form a high-quality not only wide but also deep medium Filling groove.For every one side of a 600V device, using this wide oxide channel of terminator, one common The wide HV terminators of 6-10 mils, 2 mils can be reduced to.For low current product, this HV terminators increase chip chi It is very little, increase 15% or so (in the abilities of a TO-220 filling) to big chip, it is (right to the increase 50% or so of less chip Terminate in HV, be 53 × 53 mil ^2 chips, 8 mils/side).Therefore, because reducing the termination of suitable high-voltage applications device Area, so as to solve high-voltage MOSFET power device, needs a difficult problem for big terminator.
Read described further below and referring to the drawings afterwards, the present invention these and other the characteristics of and advantage, for this For the technical staff in field, undoubtedly it will be evident that.
Description of the drawings
Fig. 1 represents a kind of profile perspective of the traditional structure of existing vertical super junction power device.
Fig. 2 represents a kind of profile of the traditional structure of existing vertical super junction power device.
Fig. 3 represents the profile of the MOSFET element with groove nanotube super-junction structures of the present invention.
Fig. 4-Fig. 6 represents the section of the MOSFET element with alternating channels nanotube super-junction structures of the present invention Figure.
Fig. 7 represents the N- channel insulation grid bipolar transistors with groove nanotube super-junction structures of the present invention (IGBT) profile of device.
Fig. 8 and Fig. 9 represent the injection of the electric charge with groove nanotube super-junction structures control electricity of the present invention respectively The profile and equivalent circuit diagram of resistance device.
Top views of the Figure 10 for structure shown in Fig. 8.
Another profile of Figure 11 for structure shown in Fig. 8.
Figure 12 represents the profile of another embodiment of the MOSFET element shown in Fig. 3, and the MOSFET element carries ditch The epitaxial layer of groove nanotube super-junction structures and three different levels of doping.
Figure 13 and Figure 14 represent the Liang Ge fragmentary, perspective views of two kinds of MOSFET elements, and both MOSFET elements all carry this The described groove nanotube super-junction structures of invention.
Figure 15 represents the top view similar to the MOSFET element shown in Figure 14.
Figure 16 and Figure 17 represent the top view of the closure elements structure of power device of the present invention.
Figure 18 represents the profile of MOSFET element of the present invention, and the MOSFET element is super with groove nanotube The terminator of junction structure and special configuration.
Figure 19 to Figure 31 is a series of profile of the preparation process of the MOSFET element shown in expression Fig. 3.
Figure 32 to Figure 41 is a series of profile of preparation process for representing configuration terminator of the present invention.
Figure 42 is the top view of plane terminator of the present invention；Figure 43 and Figure 44 is its profile；Figure 45 represents whole The voltage's distribiuting of pinch off step on individual terminator.
Figure 46 and Figure 47 represent the profile of the IGBT device with schottky device.
Specific embodiment
Fig. 3 represents groove nano-tube MOSFET (MOSFET) device of the present invention 100 Profile.MOSFET element is formed in a P-type epitaxial layer 110, and P-type epitaxial layer 110 is located on N+ substrates 105.It is many The N+ epitaxial layers 115 and multiple grooves of individual groove nanotube is formed in epitaxial layer 110.Trenched side-wall carries small inclination Angle, to form a tapered trenches.As an example, side wall can be slightly slanted 87-89 degree.Each trenched side-wall is by N+ extensions Layer 115 is covered.Another lightly doped P- epitaxial layer 116 is grown in above N+ epitaxial layers 115.Due to remaining groove width and The inclination angle of groove, the side wall of P- epitaxial layers 116 are joined towards bottom, and are sufficient filling with the bottom of groove.With silicon oxide 120 etc. The remaining core of dielectric filler groove.MOSFET element 100 also includes the trench-gate 130 being formed at the top of groove, Trench-gate 130 is by 125 filling bag of grid oxic horizon round and N+ epitaxial layers by silicon oxide layer 120 and following side wall 115 insulation.MOSFET element 100 also surrounds the body zone of trench-gate 130.Each body zone contains a P- sheet Body area 135 and a heavily doped P+ body contact region 140.MOSFET element 100 also includes N+ source areas 145, N+ source areas 145 adjacent top surfaces for being deposited on MOSFET element 100, are surrounded by P body zones 140 and 135.MOSFET element 100 is also included One barrier metal layer 150, to contact source area 145 and P+ body contact regions 140, MOSFET element 100 can also be connected to On source electrode 155.Gate electrode 160 is also used for loading grid voltage on trench-gate 130.When opening MOSFET element When 100, a passage (not representing in figure) where adjacent trenches grid 130, can be formed in body zone 135.
P- epitaxial layers 110 and with side wall, the groove covered by N+ epitaxial layers 115 and lightly doped P- epitaxial layers 116, structure Into nano tube structure, so that MOSFET element obtains charge balance.The present invention proposes a kind of high tension apparatus of charge balance, should Device efficiently can be prepared.The N+ epitaxial layers 115 of side wall, i.e. nanotube, reach electric charge with the neighbouring part of P epitaxial layers 110 Balance so that the N+ epitaxial layers 115 of side wall constitute the drift region of MOSFET, the drift region is exhausted under Disconnected mode.P- extensions Layer 116 also includes a N-type implantation region 117 being located at below body zone 135, so that passage to be connected to the N+ extensions of side wall On drift region in layer 115.By exhausting N epitaxial layers from opposite side, and higher electric charge is allowed to be stored in N+ epitaxial layers 115 In, P- epitaxial layers 116 can provide further charge balance, and improve Rdson.For example, if being further added by 25% P-type Electric charge is stored in P- epitaxial layers 116, then can be just further added by 25% N-type electric charge and is stored in N+ epitaxial layers 115, from And make Rdson reduce by 25%.P- epitaxial layers 116 are also sufficient filling with the bottom of deep trench.This can make the vertical of remaining gap in groove It is horizontal smaller, easily these gaps can be filled with oxidation implant 120, to form the preparation such as cavity problem so as to avoid. Oxidation implant 120 makes trench-gate 130 and drain potentials insulation, and reduces gate-drain capacitance.
About 1 micron of N+ epitaxial layers 115 are wide, about 6 microns of the P epitaxial layers 110 between adjacent N+ epitaxial layers 115 Width, this only as an example, not as limitation.It is considered that P epitaxial layers 110 have two halves, the width of each half is all 3 microns, And charge balance is kept with N+ epitaxial layers 115.The part of 110 charge balance of N+ epitaxial layers 115 and P epitaxial layers, the electricity having Lotus concentration is about 1E12cm-2, therefore the doping content of P epitaxial layers 110 is 3.33E15cm-3, the doping content of N+ epitaxial layers 115 For 1E16cm-3.Additionally, the concentration of electric charges that 1 micron wide of P epitaxial layers 116 have is 0.25E12cm-2, doping content is 2.5E15cm-3, the doping content of N+ epitaxial layers 115 can be increased to 1.25E16cm-3, so as to reduce Rdson.
Fig. 4 represents an alternative embodiment of groove nanotube (MOSFET) device 100-1 of the present invention.MOSFET Device 100-1 is grown in N+ epitaxial layers except lightly doped N-- epitaxial layers 116-1 (rather than the P- epitaxial layers 116 shown in Fig. 3) Beyond on 115, other are all similar with the MOSFET element 100 shown in Fig. 3.Therefore, in MOSFET element 100-1 and N- is not needed Type implantation region 117.Lightly doped N-- epitaxial layers 116-1 is also sufficient filling with the bottom of groove, fills out in order to be subsequently formed oxidation Fill thing 120.After forming N+ epitaxial layers 115, it is possible to use same epitaxial chamber prepares N-- epitaxial layer 116-1, and If growing P epitaxial layers 116, it is necessary to which chip moved to another growth room, thus using N-- epitaxial layer 116-1 than P outside Prolong layer 116 to be easier to prepare.This also increases the yield of device.In one alternate embodiment, N epitaxial layers 116-1 can be used One intrinsic or lightly doped P-- layer replaces.
Fig. 5 represents an alternative embodiment of groove nanotube (MOSFET) device 100-2 of the present invention.MOSFET Device 100-2 is substantially similar with the MOSFET element 100 shown in Fig. 3, and simply groove is wider so that be formed in N+ epitaxial layers 115 The P epitaxial layers 116-2 of top is only served as a contrast in groove, can not be sufficient filling with channel bottom.Conversely, oxidation implant 120-2 It is filled with the overwhelming majority of channel bottom.
Fig. 6 represents an alternative embodiment of groove nanotube (MOSFET) device 100-3 of the present invention.MOSFET Device 100-3 is substantially similar with the MOSFET element 100 shown in Fig. 3, and simply P epitaxial layers 116-3 is except in oxidation implant Beyond bottom below 120-3 is thicker, in most of regions, P epitaxial layers 116-3 is very thin, so that N+ in that region Epitaxial layer 115-3 all with its counter-doping.If it is an option that implementing isotropism after growth P epitaxial layer 116-3 Light etching, then can just form this structure.Isotropic etching can remove the marginal portion of P epitaxial layer 116-3, Leave the bottom of P epitaxial layer 116-3.
Fig. 7 represents N- channel insulation grid bipolar transistor (IGBT) devices with groove nano tube structure of the present invention The profile of part 101.The IGBT device 101 is formed in P-type epitaxial layer 110, and P-type epitaxial layer 110 is located at substrate P layer 105- On 1, used as the colelctor electrode of IGBT, N- passages cutoff layer 108 is deposited between P- epitaxial layers 110 and P+IGBT emission layer 105-1. IGBT device 101 is similar with the structure of the MOSFET element shown in Fig. 3, also comprising the multiple grooves being formed in epitaxial layer 110 Nanotube, contains multiple grooves in groove nanotube.The groove for being formed carries side wall, and side wall has small inclination angle, and And each trenched side-wall is covered with 115, P- epitaxial layer 116 of a nanotube N+ epitaxial layer and is filled out with silicon oxide 120 The groove core for filling.IGBT device 101 also includes trench-gate 130, and trench-gate 130 is formed at the top of groove, by grid Oxide layer 125 filling bag in pole is round and the N+ epitaxial layers 115 by silicon oxide layer 120 with side wall insulate.IGBT device 101 is also Comprising the body zone around trench-gate.Each body zone is deposited under heavily doped P+ body contact regions 140 containing one The P- body zones 135 in face.IGBT device 101 also includes N+ source areas 145, and N+ source areas 145 are deposited on adjacent top surface, and by P Body zone 135 and 140 is surrounded.IGBT device 101 also includes a barrier metal layer 150, and barrier metal layer 150 is by source area 145 and body zone 140 be connected on emitter electrode 155.A gate electrode 160 is re-formed, so as on trench-gate 130 Loading grid voltage.
P- epitaxial layers 110 and the groove with the side wall covered by N+ epitaxial layers 115 for being formed, constitute nanotube knot Structure, to form the drift region of charge balance in IGBT device.
Fig. 8 represents the profile of the injection of the electric charge with groove nano tube structure control diode of the present invention.Fig. 9 With Schottky diode 162 and PN junction diode 161 in Fig. 8, represent that electric charge injection adjustable resistor R1's 163 is equivalent The circuit diagram of circuit.Electric charge injection adjustable resistor R1 163 is connected with PN junction diode 161, PN junction diode 161 and Xiao Te Based diode 162 is in parallel.Resistor 163 is desirably integrated in device, such as a metal and polyresistor, or Can also be external in device, the resistance value needed for selecting user.P-type epitaxial layer 110 is located at N/N+ substrate layers 105 On, as PN junction diode and the negative electrode of Schottky diode.Ohmic contact to P epitaxial layers 110 is formed in the third dimension, and one Until P+ areas 176.Schottky diode and PN junction diode are all located on P epitaxial layers 110, and the P epitaxial layers 110 for being formed are carried Multiple groove nanotubes, groove nanotube contain multiple grooves.The groove for being formed carries side wall, and side wall has small inclination Angle, and each trenched side-wall be covered with nanotube N+ epitaxial layers 115, P- epitaxial layers 116 and with silicon oxide 120 fill Groove core.Wider groove can be formed in deeper oxidation implant 121 more wider than other oxidation implants 120 On.When they are formed on same semiconductor wafer, so contribute to separating different devices.Schottky diode contains one Individual N- areas 165, Schottky contact metal 170 are covered with the top surface in N areas 165.N areas 165 are deposited on nanotube N+ epitaxial layers 115 Side, near oxide layer 120, and is contacted with P epitaxial layers 110 and N+ epitaxial layers 115.PN junction diode contains a P/P+ area 175/176, ohmic contact metal layer 180 is covered on the top surface in P/P+ areas 175/176 as a modulation grid.P areas 175 Contact with P epitaxial layers 110 and nanotube N+ epitaxial layers 115.Injection energy in the control P-N junction diodes of resistor R1 163 Level, is by reducing the voltage in whole PN junction diode (by voltage VR1=IDiode* R1), cause The quantity of electric charge reduce, Reverse recovery strengthened.The value of resistor R1 is larger, strengthens can Reverse recovery, and conductivity is adjusted System reduces bringing less forward conduction.The value of resistor R1 is less to bring reverse effect.By Schottky diode and PN Junction diode is in parallel, can further reduce the quantity of electric charge stored in PN junction diode.Change the size of resistor R1 163, can be with The quantity of electric charge stored in control PN junction diode 161 and the performance of diode.PN junction diode reduces high pressure (HV) Xiao Te The leakage current of based diode, optimizes forward drop Vf of multiple device.
As shown in the profile of Figure 10 and Figure 11, Schottky diode (being represented with N areas 165) and PN junction diode (being represented with P/P+ areas 175/176) is on the same striped of epitaxial layer 110.
Figure 12 represented similar to the MOSFET element shown in Fig. 3, the MOSFET element 102 with groove nano tube structure Side cut away view.P epitaxial layers 110 as one classification epitaxial layer 110 ', also with by three kinds of different levels of doping three Step is epitaxially-formed three P doped layer 110-1,110-2 and 110-3.Epi dopant concentration increases with the increase of height, That is the doping content of bottom P doped layer 110-1 is minimum, the doping content highest of top P doped layer 110-3.Outside classification Prolong layer 110 ' and improve the UIS of device by by breakdown region from the top of epitaxial layer toward moving down.And, by by under breakdown field Move on in P epitaxial layers 110, make the electric charge for being injected into P epitaxial regions 110 be more than N+ epitaxial layers 115, it is also possible to improve UIS.Although, Be used for preparation classification epitaxial layer in this is three step epitaxy layer, but can also use the epitaxial layer of more multistep.Also may be selected Using the single epitaxial layer being gradually classified, its doping content is gradually lowered from top to bottom.
Figure 13 and Figure 14 are denoted as the side perspective view of two kinds of different components of cord elements.In order to illustrate, this Place does not represent source electrode and body zone --- only represent grid and epitaxial layer.The device that Figure 13 is represented is similar to shown in Fig. 4 Device 100-1, the device that Figure 14 is represented is similar to the device 100 shown in Fig. 3.Figure 15 represents the vertical view of device shown in Figure 14 Figure, locus of discontinuity 122 are located in grid 130, close part P- epitaxial layer 116.Mask makes oxidation implant 120 in preparation process In, it is not etched in region 122.Same mask also makes the not implanted N-type in the P- epitaxial layers 116 of locus of discontinuity 122 Implant 117, N-type implant 117 are implanted into along groove elsewhere.Where with exposed P- epitaxial layers 116, in order to Charge balance is kept, the connection from source voltage to P- epitaxial layers 116 can be set up.Also may be selected, do not formed in grid 130 Locus of discontinuity 122, forms the implantation process not top layer implantation of N-type implant 117, but with mask, so as to allow P- The non-return doping in region of epitaxial layer 116, and be connected on source voltage.Can also select, this effect can also be led to Cross the P-type implantation step with mask to reach, the area that P- epitaxial layers 116 are exposed is created so as to form N-type implant 117 Domain.
Figure 16 and Figure 17 represent the top view of the MOSFET element with closure elements.Closing as shown in Figure 16 and Figure 17 Element compared with striated structure, in closure elements (i.e. 2.5 microns of the P- with 3 microns of silicon mesa structure of 6 × 6 Area, the groove opening of 0.25 micron of N- rings and 3 microns) in, closure elements as shown in Figure 16 and Figure 17 can be reduced about 30% Rds resistance.Figure 16 represents the closure elements layout of the nano tube structure without source electrode or body zone.P- epitaxial layers 110 centers for being located at each closure elements, and surrounded by nanotube N+ epitaxial layers 115 and P- epitaxial layers 116.Trench-gate 130 and gate oxide 125 around closure elements.Represented in Figure 17 is source electrode and body zone, P+ body contacts 140 In the center of each closure elements, surrounded by N+ source areas 145.To put it more simply, N- implantation regions 117 are not represented in figure. Also may be selected, in the location swap of trench-gate and quasiconductor, using the closure elements with discontinuous grid, make quasiconductor Substrate (including source electrode and body) surrounds trench-gate, and trench-gate is located at the center of closure elements.
Figure 18 is represented similar to the MOSFET element 102 shown in Figure 12, the MOSFET element with groove nano tube structure Side cut away view.P epitaxial layers 110, as three P doped layer 110-1,110-2 and 110-3, are by passing successively from top to bottom What the epitaxial process of the three kinds of different levels of doping for subtracting was formed.MOSFET element also includes a high pressure terminator, carries One not only wide but also deep termination groove 189 (such as 30 microns), and terminate groove with dielectric material 190 and the filling of oxide 120 189.What is formed terminates initial network of the groove 189 with a groove filled with oxide 120, and it can be with active ditch The oxide 120 of groove is formed simultaneously.Semiconductor mesa structure (not representing in figure) is between the network of oxide 120； Then semiconductor mesa structure is etched away, dielectric material 190 is filled in produced gap.The terminal of terminator is deposition Sawtooth block 195 on chip peripheral edge.
Figure 19 to Figure 31 is a series of side cut away views, is represented with the self aligned height similar to nanotube shown in Fig. 3 The preparation process of pressure (HV) semiconductor power device.Figure 19 represents initial N+ Semiconductor substrates 205, i.e., heavily doped N+ silicon lining Bottom, carries the P-type epitaxial layer 210 being grown in above substrate 205.P-type epitaxial layer 210 is it is also seen that be upper strata quasiconductor Substrate, N+ Semiconductor substrates 205 are considered as underlying semiconductor substrate.Can be with growth selection P-type epitaxial layer 210, with three kinds Or more kinds of different P- doping contents, or with the doping content being gradually classified, its doping content gradually drops from top to bottom It is low.Then, oxide layer 211 and silicon nitride (Si are formed3N4) layer 212, as hard mask.In fig. 20, using trench mask (figure In do not represent) etch hard mask first, comprising oxide layer 211 and silicon nitride layer 212.Then silicon etching is carried out, in extension Groove 213 is opened in layer 210.Open about 3.5 microns of the groove width of groove 213, about 36 to 40 microns of gash depth, side About 88 degree of wall angle.215 epitaxial growth of N nanotube layers above N nanotube layers 215, use by about 0.25 to 0.5 micron of thickness Arsenic dopants are adulterated, as shown in figure 21.P- epitaxial layers 216 can be grown in above N nanotube layers 215.As shown in figure 22, due to The size of groove 213 and inclined side wall, P- epitaxial layers 216 have been sufficient filling with the bottom of groove.Then, as shown in figure 24, will Very thin high-density plasma (HDP) oxide layer 220 is deposited in groove, and fills groove.
In fig. 24, using back etching process and/or CMP (CMP) technique, remove the oxygen on top surface SiClx (SiO2) 220, until silicon nitride layer 212 it is exposed out.(do not represented in figure) using trench-gate mask, will oxidation Layer 220 etches into about 1.5 to 2.0 microns of depth.As shown in figure 25, it is implanted into using N-type, in the exposed of P- epitaxial layers 216 N-type implant 217 is formed on the wall of side.
In fig. 26, the grid oxic horizon 225 of about 350-1200 angstrom of thickness is formed, and side is covered in along P- epitaxial layers 216 On wall.Deposition gate polysilicon layer 230, preferably from N+ original positions doped polysilicon layer.Back etches polycrystalline silicon 230, using CMP Smooth its top surface of technique, and remove hard mask oxide layer 211 and silicon nitride (Si3N4) layer 212.Further etches polycrystalline silicon layer 230, the grid 230 of a slight depression is formed, the top surface of grid polycrystalline silicon 230 is about lower 0.3 micron than mesa surfaces. Then a cushion oxide layer 232 is grown in top face.
In figure 27, it is implanted into using high-energy boron or P- bulk dopeds, forms body zone 235.Carry out high energy bulk doped During implantation, certain inclination angle to be carried, to prevent due to the negative mesa structure angle of trenched side-wall, and near trenched side-wall Masking is produced in region.After rising high-temperature, bulk doped driving is carried out, body zone 235 is diffused into into P- epitaxial layers 210, nanometer In pipe N epitaxial layers 215 and P- epitaxial layers 216.Then, when zero degree is close to, weight boron implantation is carried out, so as in body zone 235 The adjacent top surface of side forms P+ body contact regions 240.In Figure 28, mental retardation is carried out using source mask (not representing in figure) Phosphorous N+ implantation, to form the N+ source areas 245 being enclosed in P- body zones 235 and P+ areas 240.Under 900 degrees Celsius, profit Implantation activation 30 minutes is carried out with annealing process.In one alternate embodiment, N-type plant is carried out at a higher temperature Enter, so that the N-type region of embedment is produced below P- body zones 235, be equally used for MOSFET channel regions are connected to as N-type The N epitaxial layers 215 of implant 217.
Then, one silicon nitride (Si of formation on top surface3N4) hard mask layer (not representing in figure).Covered using termination Film (not representing in figure) carries out isotropic silicon etching in terminator, so as in the terminator between silicon oxide layer Mesa region in open groove (not representing in figure), then with electrolyte or SiO2Table top knot after filling etching Structure groove (such as the dielectric layer 190 shown in Figure 18).Back etch media layer 190, until hard mask layer is exposed out, then carves Lose and remove hard mask (not representing in figure).These techniques in terminator are as shown in figure 11.As shown in figure 29 that Sample, deposits the silica glass containing boric acid (BPSG) passivation layer 250.In fig. 30, using contact mask (not representing in figure), Open the contact openings through bpsg layer 250.In Figure 31, in one metal level of deposited on top, then using metal mask (not representing in figure), forms the pattern of source metal 260-S and gate pad (not representing in figure) on the metal layer. One metal level is also formed on the bottom of substrate 205, to prepare drain metal 205-D, so as to complete whole super junction nanotube MOSFET 200。
Be a series of side cut away views referring to Figure 32 to Figure 41, represent it is a kind of with nanotube as shown in Figure 3 from right The preparation process of the terminator of quasi- high pressure (HV) semiconductor power device.Figure 32 represents that initial N+ Semiconductor substrates 205 (are for example weighed N+ doped silicon substrates), P-type epitaxial layer 210 is carry, P-type epitaxial layer 210 uses three as layer 210-1,210-2 and 210-3 Different doping contents are planted, is grown in the top of substrate 205.The P-type epitaxial layer 210 for being grown can also have gradually be classified Doping content, its doping content is gradually lowered from top to bottom.Then, oxide layer and silicon nitride (Si are formed3N4) layer 212, as Hard mask.In fig. 33, (do not represented in figure) using trench mask, etch hard mask 212 first, comprising an oxide layer With a silicon nitride layer.Then, active groove 213b is opened using silicon etching and terminate groove 213a, in epitaxial layer 210. About 36 to 40 microns of the gash depth of opening, about 88 degree of side wall angle.The width for terminating groove 213a is likely larger than active area Groove 213b, to ensure that as shown in FIG., the oxide being filled in these grooves reaches channel bottom.Then, in ditch Side wall one N- extensions nanotube layer 215 of Epitaxial growth of groove 213a and 213b, about 0.25 to 0.5 micron of its thickness, and Adulterated with arsenic dopants, subsequently in N nanotubes 215 top epitaxial growth, one P- epitaxial layer 216.As shown in figure 34, in groove Middle deposition is simultaneously filled with thin HDP oxide layers 220.It should be noted that due to terminate groove 213a width it is larger, although P- extensions The bottom of 216 abundant filling active area trenches 213b of layer, is but only capable of filling a thin layer lining for terminating groove 213a.Cause This, the depth that oxide layer 220 is filled in groove 213a is terminated is much smaller than the depth in active groove 213b.Can be in frontier district Wider groove is filled using not only deep but also wide oxide in domain, during to prepare different components on same semiconductor wafer, distinguishes These different devices.
Then, using back etch process and/or CMP (CMP) technique, remove the oxide layer on top surface 220, until silicon nitride layer 212 it is exposed out.At this moment, the network of an oxidation column 223 can be formed in terminator, in the net Contain semiconductor mesa structure 224 in network.Terminator is covered with wide groove 213a, is covered using the trench-gate for being covered with terminator Film 218, etches the oxide layer 220 in active area groove 213b.Then, as shown in figure 35, along the exposed side wall of P- epitaxial layers 216 N-type implantation is carried out, N-type implantation region 217 is prepared.As shown in figure 36, by the liner of grid oxic horizon 225, prepare polysilicon Grid 230.At this point it is possible to remove the hard mask 212 on active area.Then, as described above, forming 235 He of P- bodies base region Weight P+ areas 240.(do not represented in figure) using source mask, as described above, in active cell area, being implanted into and being formed N+ sources Polar region 245, as shown in figure 37.In Figure 38, using hard mask 249 is terminated, by trench-gate mask 218 and remaining hard mask 212 remove together.In Figure 39, using silicon etching, etching semiconductor mesa structure 224, i.e. epitaxial layer 210-1,210-2 and 210-3, between the oxide layer 220 of terminator, leaves interim etching groove 222.In Figure 40, filled with dielectric material 290 Etching groove 222 between the oxide layer 220 in terminator, to fill the etching mesa structure in terminator, forms again Deep and wide termination oxidation groove 289.In Figure 41, remove and terminate hard mask 249, carry out follow-up as shown in Figure 29 to Figure 31 Handling process, completes the preparation of the MOSFET element with special terminator as shown in figure 18.
Figure 42 is top view, Figure 43 and Figure 44 respectively MOSFET elements as shown in figure 42 with plane termination structure Along A-A ' lines and the profile of B-B ' lines.For clarity, although substantially indicate the electrical connection formed by metal level, But top view does not represent the top of metal, oxide and passivation layer, as shown in Figure 18 and Figure 41, plane terminates being wide One optional alternate embodiment of oxidation groove.In plane termination structure, terminator 199 ' includes the platform similar to active area Face structure 110 ', between the groove filled with oxide layer 120 ', trenched side-wall is by N doped epitaxial layers for mesa structure 110 ' 115 ' are covered with P- epitaxial layers 116 ', and P- epitaxial layers 116 ' also include a N-type implantation region 117 '.Terminate unit not have The source/body area 135,140 and 145 of active cell 198 '.Conversely, as shown in Figure 42 to Figure 44, outside P- mesa structures and N- Prolong layer to be connected by metal level 150-1 to 150-5, so that each terminates unit one specific pinch-off voltage VPT of locking.Passivation layer 195 ' can cover metal level 150-1 to 150-5.
Last active cell (as shown in left side in figure), it is when source voltage is 0 volt, by metal level 150-1, short It is connected to the P- mesa structures (and in middle polysilicon block 130 ') of the first termination unit.More precisely, metal level 150-1 It is connected to 135 ' Nei P+ areas 140 ' of P areas.The N- epitaxial layers 115 ' of P- mesa structures 110 ' and surrounding exhaust, by N- epitaxial layers Voltage is increased to pinch-off voltage VPT1, i.e., voltage when N- epitaxial layers and P- mesa structures exhaust.N- epitaxial layers 115 ' are connected to bag Round first terminate unit N+ areas 140 " N areas 135 " on, first terminate unit N+ areas 140 " it is short by metal level 150-2 It is connected on the next P- mesa structures for terminating unit (the next unit on right side), due to exhausting in the unit, makes Voltage increases a V againPT1, so that total voltage now is VPT2≈2*VPT1.Running voltage (leakage until reaching device Pole tension) when, such case can just stop.Referring to Figure 45, first by source potential as the reference voltage, such as metal level 150- 1 V=0, voltage by pinch off step 155 it is gradual in the way of gradually increase so that the voltage at metal level 150-2 be VPT1。 Voltage is incremented to VPT1, then reach the V at metal level 150-3PT2, device voltage is finally increased to, i.e., in last metal Layer 150-n at 600 volts of predeterminated voltages, as in Figure 45 near semiconductor chip edge line shown in.
Polysilicon block 130 ' is formed in oxidation groove 120 ', with the oxidation for preventing electric charge and dirt from entering in oxidation groove Thing, so as to improve the reliability of device.As plane termination structure is compared with wide oxidation groove, need it is bigger it is horizontal away from From to intercept running voltage, therefore the plane termination structure wide oxidation groove termination structure not as shown in figure 18 is compact.Should also It is noted that it is similar with the groove in above-mentioned active cell area, open with silica-filled groove in terminator, also carry The side wall being slightly inclined.
Figure 46 represents a kind of profile of the IGBT device 101 ' similar to shown in Fig. 7, the IGBT device 101 ' with it is similar It is mutually integrated in the schottky device 162 ' shown in Fig. 4.With not only deep but also the wide groove of wide oxidation implant 121, will be device separate. In this case, by the bottom of Semiconductor substrate backgrind to not only deep but also wide oxidation implant 121.In semi-conducting material Bottom, implanted with n-type layer 108 ' and P-type layer 105-1 '.As IGBT has embedded type diode unlike MOSFET, therefore The embodiment is particularly useful.It should be appreciated that, as U.S. Patent Application No. be 12/484, as described in 166, to without After the single P- substrates for having initial epitaxial layer carry out backgrind and implantation, device can be constituted with this single P- substrates.Such as Shown in Figure 47, preparing the structure can also be without the need for backgrind, so as to by P-type layer 150-1 " it is implanted to a part of N-type quasiconductor In substrate 108 ".
Although the present invention has been described in detail existing preferred embodiment, the limitation of the present invention is should not be used as.For example, Although described in described above is n- passage devices, the present invention is by the conduction type reversion by doped region, it is also possible to In p- passage devices.A variety of devices can be prepared, comprising those devices with planar gate.Those skilled in the art After member reads above-mentioned detailed description, various changes and modifications undoubtedly will be evident that.Therefore, appending claims should be covered Whole variations and modifications in the true intention and scope of the present invention.
Although present disclosure has been made to be discussed in detail by above preferred embodiment, but it should be appreciated that above-mentioned Description is not considered as limitation of the present invention.After those skilled in the art have read the above, for the present invention's Various modifications and substitutions all will be apparent.Therefore, protection scope of the present invention should be limited to the appended claims.

Claims (21)

1. a kind of device architecture with groove-oxide-nanotube super junction, it is characterised in that include：
Second semiconductor layer of the first semiconductor layer of one the first conduction type and second conduction type, described Two semiconductor layers are deposited on the first semiconductor layer；
The groove opened in the second described semiconductor layer, extends vertically up to the first described semiconductor layer；
First epitaxial layer of one the first conduction type being formed on the side wall of described groove；And
One the second epitaxial layer being formed on the first described epitaxial layer；The first wherein described epitaxial layer is partly led with adjacent Sufficient charge balance is reached between body region；
One, by the terminator that cellular array is constituted is terminated, terminates unit with one first in the interface of active cell, Wherein each termination unit is also included：
The mesa structure of one the second semiconductor layer, and the first epitaxial layer is formed on its side wall, and the second epitaxial layer is formed On the first epitaxial layer, the mesa structure is near the groove with Filled Dielectrics thing；
The first area of one the first conduction type, is formed in the top surface of the mesa structure；And
The second area of one the second conduction type, is formed in the top surface of the mesa structure, in the mesa structure First area separates,
Wherein each second area for terminating unit is all electronically connected on the adjacent next first area for terminating unit.
2. device architecture as claimed in claim 1, it is characterised in that at least some groove, second epitaxial layer fills Divide the bottom for being filled with the gap not occupied by the first epitaxial layer.
3. device architecture as claimed in claim 2, it is characterised in that bottom of the side wall of second epitaxial layer towards groove It is combined.
4. device architecture as claimed in claim 1, it is characterised in that the side wall of the groove has certain angle, with shape Tapered groove, and assemble towards the bottom surface of groove.
5. device architecture as claimed in claim 1, it is characterised in that second epitaxial layer is the first conduction type.
6. device architecture as claimed in claim 1, it is characterised in that second epitaxial layer is the second conduction type or intrinsic Semi-conducting material.
7. device architecture as claimed in claim 1, it is characterised in that also include：The first electrolyte in center slot is filled out Thing is filled, the center slot is not occupied by second epitaxial layer at the center of groove.
8. device architecture as claimed in claim 1, it is characterised in that also include：One gate electrode, which is deposited at least one In at the top of a little grooves.
9. device architecture as claimed in claim 8, it is characterised in that also include：One medium being located at below gate electrode The remaining core of layer filling groove.
10. device architecture as claimed in claim 1, it is characterised in that also include：Form Schottky between adjacent trenches Diode and PN junction diode.
11. device architectures as claimed in claim 10, it is characterised in that the PN junction diode is that a kind of electric charge injection is controllable Diode, which is connected with an electric charge injection controllable resistor, and in parallel with Schottky diode.
12. device architectures as claimed in claim 1, it is characterised in that the second described semiconductor layer is in two adjacent trenches Between width, more than the width of the first described epitaxial layer.
13. device architectures as claimed in claim 1, it is characterised in that the second described semiconductor layer is in two adjacent trenches Between width, three times of at least described the first epitaxial layer width.
14. device architectures as claimed in claim 1, it is characterised in that the device architecture also includes a metal-oxide Semiconductor field MOSFET.
15. device architectures as claimed in claim 1, it is characterised in that the device architecture also includes an insulated gate bipolar Transistor IGBT.
16. device architectures as claimed in claim 1, it is characterised in that the device architecture is also comprising one and diode collection Into insulated gate bipolar transistor IGBT.
17. device architectures as claimed in claim 1, it is characterised in that the second described semiconductor layer has the doping of classification Structure, its doping content are gradually lowered from top to bottom.
18. device architectures as claimed in claim 7, it is characterised in that also include：
One termination structure with medium groove, it is stood comprising a medium formed by the first described dielectric filler The network of post, and the second dielectric filler being formed between medium column described in network.
19. device architectures as claimed in claim 7, it is characterised in that at least one second devices are deposited on Semiconductor substrate On, wherein the groove being deposited between adjacent devices is bigger than the groove width of other grooves.
20. device architectures as claimed in claim 1, it is characterised in that the device architecture is also included with striated structure Transistor unit.
21. device architectures as claimed in claim 1, it is characterised in that the device architecture is also comprising with isolated cell The transistor unit of layout.
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