CN104599966A - Configurations and methods for manufacturing devices with trench-oxide-nano-tube super-junctions - Google Patents

Configurations and methods for manufacturing devices with trench-oxide-nano-tube super-junctions Download PDF

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Publication number
CN104599966A
CN104599966A CN201410766372.5A CN201410766372A CN104599966A CN 104599966 A CN104599966 A CN 104599966A CN 201410766372 A CN201410766372 A CN 201410766372A CN 104599966 A CN104599966 A CN 104599966A
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groove
epitaxial loayer
layer
preparation
super
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CN104599966B (en
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哈姆扎·依玛兹
马督儿·博德
李亦衡
管灵鹏
王晓彬
陈军
安荷·叭剌
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Alpha and Omega Semiconductor Cayman Ltd
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Alpha and Omega Semiconductor Inc
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Abstract

This invention discloses a semiconductor power device disposed on a semiconductor substrate of a first conductivity type. The semiconductor substrate supports an epitaxial layer of a second conductivity type thereon wherein the semiconductor power device is supported on a super-junction structure. The super-junction structure comprises a plurality of trenches opened from a top surface in the epitaxial layer; wherein each of the trenches having trench sidewalls covered with a first epitaxial layer of the first conductivity type to counter charge the epitaxial layer of the second conductivity type. A second epitaxial layer may be grown over the first epitaixial layer. Each of the trenches is filled with a non-doped dielectric material in a remaining trench gap space. Each of the trench sidewalls is opened with a tilted angle to form converging U-shaped trenches.

Description

With device architecture and the preparation method of groove-oxide-nanotube super junction
This case is divisional application
Original bill denomination of invention: with device architecture and the preparation method of groove-oxide-nanotube super junction
Original bill application number: 201110054042.X
The original bill applying date: on February 28th, 2011.
Technical field
The present invention relates generally to semiconductor power device, or rather, the present invention relates to the structure with the groove nanotube of trenched side-wall and preparation method, wherein with the epitaxial loayer covering groove sidewall of doping, then filling insulating material trenched side-wall is used, to prepare the semiconductor power device of measurable charge balance neatly by the preparation technology simplified, obtain high-breakdown-voltage and very low resistance simultaneously.
Background technology
Although about the semiconductor device with vertical super-junction structures, in order to improve its electrology characteristic, existing many patent information and disclosed technological document, but in the design of super junction-semiconductor device and the association area of preparation, still there is many technical barriers and limit to preparation.Or rather, modal super-junction device comprises metal oxide semiconductor field effect tube (MOSFET) and igbt, about these devices, existing many published patent information, comprise United States Patent (USP) 5,438,215,5,216,275,4,754,310,6,828,631.Rattan flat (Fujihira), in " semiconductor super-junction device is theoretical " (Japanese Applied Physics bulletin, 36 volumes, in October, 1997,6254-6262 page) book, proposes the structure of vertical super-junction device.Or rather, rattan Fig. 2 put down in the paper delivered illustrates a kind of vertical trench MOSFET super-junction device, is cited as Fig. 1 (1A) at this.Rattan is flat also at United States Patent (USP) 6, and 097, propose a kind of vertical semiconductor devices with drift region in 063, when device is in closed mode, have drift electric current to flow through in drift region, when device is in Disconnected mode, the drift electric current in drift region exhausts.The drift region structure formed is the discrete drift region with multiple first conduction type, and the marker space of multiple second conduction type, and wherein each marker space is arranged in drift region adjacent respectively, formation p-n junction in parallel.United States Patent (USP) 6,608,350 propose a kind of vertical super-junction device, and fill in the trench with layer of dielectric material, United States Patent (USP) 5,981,996 as shown in Fig. 2 (1B), proposes a kind of vertical trench MISFET device.
But, in the structure and service behaviour of the super-junction device described in these patented technologies and disclosure, still there is many technology limitation, thus limit these devices validity in actual applications.A difficult problem and the limitation of conventional Super junction device comprise the filling of deep trench, form the size restrictions of nanotube in the trench, keep the mesa region place charge balance near terminator, undamped inductive switching (UIS) scarce capacity of super-junction device, the oscillation problem of super junction power device, because epitaxial growth speed slowly causes the high manufacturing cost of super-junction device, N and P impurity at high temperature phase counterdiffusion in super-junction structures, be difficult to integrated different device on the same chip, and the Related Technical Issues such as termination area during high-voltage applications is very large.
Therefore, in the design and preparation field of power semiconductor, be necessary the device architecture and the preparation method that propose the novelty forming power device, thus solve above-mentioned difficulties and limitation.
Summary of the invention
Therefore, one aspect of the present invention be propose a kind of novel, improvement device architecture and preparation method, by in trenched side-wall and bottom, grow a thin N-type doped epitaxial layer (such as arsenic epitaxial loayer), do not fill completely or be partially filled groove, then side grows the second epitaxial loayer on the first epitaxial layer, and fills remaining formation gap with the dielectric material of undoped, thus solution with epitaxial loayer fill deep trench time, the problem often run in traditional preparation method.Second epitaxial loayer fully can fill the bottom of all the other groove gaps, thus can in gap deposits dielectric materials more easily.
Another aspect of the present invention is, propose a kind of device architecture that is novel, improvement with super-junction structures and preparation method, utilize charge balance concept, pass through nano tube structure, reduce Rds, and element spacing is very little, to obtain the 600V MOSFET of 6 micron pitch, its conducting resistance rate is less than 9 bold and unconstrained Europe/cm 2.Which solves for during high tension apparatus for the restriction of high Rds.
Another aspect of the present invention is, propose a kind of device architecture that is novel, improvement with super-junction structures and preparation method, this structure utilizes larger spacing and narrow N-epitaxial loayer, and utilize the single element at the interdigital end of each active element with relatively large radius, keep charge balance at the end of active region mesa structure.
Another aspect of the present invention is, propose a kind of device architecture that is novel, improvement with super-junction structures and preparation method, super-junction structures is prepared in an epitaxial loayer with doping content classification, such as on a N+ substrate, form P epitaxial loayer by three steps, force to puncture and occur in the lower part of drift region, thus improve the UIS performance of super junction MOSEFT device.
Another aspect of the present invention is, propose a kind of device architecture that is novel, improvement with super-junction structures and preparation method, thick dielectric area is positioned at below gate electrode, to reduce grid-drain capacitance Crss, thus solves the oscillation problem of super junction power device.
Another aspect of the present invention is, propose a kind of device architecture that is novel, improvement with super-junction structures and preparation method, by growing a thin simple layer N-epitaxial loayer (thickness range of 0.1-1.0 micron), be partially filled groove, and fill remaining deep trench by dielectric/oxide, thus solve because epitaxial growth in deep trench is slow, and the high manufacturing cost problem of the super-junction device caused.In addition, lightly doped N-type epitaxy layer can grow after N-epitaxial loayer, and before filling remaining deep trench by dielectric/oxide, abundant filling groove, this is conducive to using oxide filling groove more easily.
Another aspect of the present invention is, proposes a kind of device architecture that is novel, improvement with super-junction structures and preparation method, forms a very thin N-type nanotube layer, and balance with wider P-type area charge at wider P-type areas adjacent; Exemplarily, the wider P-type region of N-type nanotube layer is wide three times, causes the doping content of boron lower than the N-type doping content in N-type nanotube region three times.Therefore, limited boron can only be allowed to diffuse into N-type nanometer area under control, thus compensate unnecessary arsenic electric charge.Heavy N-type doping (such as arsenic or antimony) of N-type nanotube region, can not too movement, thus can not be diffused into P-type district in a large number.Which solves at high temperature, the problem that the counterdiffusion of N and P impurity phase brings.
Another aspect of the present invention is, propose a kind of device architecture that is novel, improvement with super-junction structures and preparation method, increase the trench region width at the first device line of demarcation place, such as a MOSFET element and second device (such as Schottky diode), fully fill large trench region with dielectric material---different from active device, active device is fully filled with silicon, then use silica (oxide or SiO2) to fill remainder.Therefore, different devices can be integrated on same silicon more easily.
Another aspect of the present invention is, propose a kind of device architecture that is novel, improvement with super-junction structures and preparation method, a Schottky diode and a controlled injection P-N diode are integrated, thus reduce the recovery charge of diode, reduce the leakage current of high tension apparatus.
Another aspect of the present invention is, propose a kind of device architecture that is novel, improvement with super-junction structures and preparation method, high pressure (HV) Schottky diode and a controlled injection P-N diode are integrated on same silicon wafer, as an igbt (IGBT), wherein the back side of IGBT is implanted with emitter (being P-type for N-passage device).Thus solve the difficult problem that IGBT structure lacks embedded type diode.
Another aspect of the present invention is, propose a kind of termination structure that is novel, improvement, the method preparing wide medium groove is first by formation SiO2 network, then the silicon mesa structure in SiO2 network is etched away, and with spin-on glass, HDP or polyimides, fill the region that just etched away, before metallization or after carry out, depend on the type of selected dielectric material.Owing to preparing suffered restriction, be difficult to prepare not only wide but also dark medium groove by traditional etching and fill method, but two-stage process of the present invention can utilize the preparation technology of standard, form a high-quality not only wide but also dark Filled Dielectrics groove.For each side of a 600V device, utilize this wide oxide channel of terminator, the HV terminator that a common 6-10 mil is wide, 2 mils can be reduced to.For low current product, this HV terminator increases wafer size, increases about 15% (in the ability that a TO-220 fills), increase about 50% (stopping for HV, is 53 × 53 mil ^2 wafers, 8 mils/side) to less wafer to wafer.Therefore, owing to reducing the terminator of applicable high-voltage applications device, thus solve high-voltage MOSFET power device, need a difficult problem for large terminator.
Read following to describe in detail and with reference to after accompanying drawing, these and other characteristics and advantages of the present invention, for a person skilled in the art, undoubtedly will be apparent.
Accompanying drawing explanation
Fig. 1 represents the profile perspective of the traditional structure of existing a kind of vertical super junction power device.
Fig. 2 represents the profile of the traditional structure of existing a kind of vertical super junction power device.
Fig. 3 represents the profile of the MOSFET element with groove nanotube super-junction structures of the present invention.
Fig. 4-Fig. 6 represents the profile of the MOSFET element with alternating channels nanotube super-junction structures of the present invention.
Fig. 7 represents the profile of N-channel insulation grid bipolar transistor (IGBT) device with groove nanotube super-junction structures of the present invention.
Fig. 8 and Fig. 9 represents profile and the equivalent circuit diagram of the charge injection control resistor with groove nanotube super-junction structures of the present invention respectively.
Figure 10 is the vertical view of structure shown in Fig. 8.
Another profile that Figure 11 is structure shown in Fig. 8.
Figure 12 represents the profile of another embodiment of the MOSFET element shown in Fig. 3, and this MOSFET element is with the epitaxial loayer of groove nanotube super-junction structures and three different levels of doping.
Figure 13 and Figure 14 represents the Liang Ge fragmentary, perspective view of two kinds of MOSFET element, and these two kinds of MOSFET element are all with groove nanotube super-junction structures of the present invention.
Figure 15 representation class is similar to the vertical view of the MOSFET element shown in Figure 14.
Figure 16 and Figure 17 represents the vertical view of the closure elements structure of power device of the present invention.
Figure 18 represents the profile of MOSFET element of the present invention, and this MOSFET element is with the terminator of groove nanotube super-junction structures and special configuration.
Figure 19 to Figure 31 is the profile of the preparation process of the MOSFET element shown in a series of expression Fig. 3.
Figure 32 to Figure 41 is a series of profiles representing the preparation process of configuration terminator of the present invention.
Figure 42 is the vertical view of plane terminator of the present invention; Figure 43 and Figure 44 is its profile; Figure 45 represents the voltage's distribiuting of pinch off step on whole terminator.
Figure 46 and Figure 47 represents the profile of the IGBT device with schottky device.
Embodiment
Fig. 3 represents the profile of groove nano-tube MOSFET (MOSFET) device 100 of the present invention.MOSFET element is formed in a P-type epitaxial loayer 110, and P-type epitaxial loayer 110 is positioned on N+ substrate 105.Multiple groove nanotube 115 and multiple groove are formed and prolong outside in layer 110.Trenched side-wall with small inclination angle, to form a tapered trenches.Exemplarily, sidewall can tilt 87-89 degree slightly.Each trenched side-wall is covered by N+ epitaxial loayer 115.Another lightly doped P-epitaxial loayer 116 grows above N+ epitaxial loayer 115.Due to the inclination angle of remaining groove width and groove, the sidewall of P-epitaxial loayer 116 is joined towards bottom, and the bottom of abundant filling groove.With remaining core such as dielectric filler groove such as silica 120 grade.MOSFET element 100 also comprises the trench-gate 130 being formed in groove top, trench-gate 130 by grid oxic horizon 125 filling bag round, and to be insulated by silicon oxide layer 120 and N+ side wall layer 115 below.MOSFET element 100 also comprises the body zone surrounding trench-gate 130.Each body zone is containing a P-body zone 135 and a heavily doped P+ body contact region 140.MOSFET element 100 also comprises the adjacent top surface that source area, N+ source area 145, N+ 145 is deposited on MOSFET element 100, is surrounded by P body zone 140 and 135.MOSFET element 100 also comprises a barrier metal layer 150, and to contact source area 145 and P+ body contact region 140, MOSFET element 100 also can be connected on source electrode 155.Gate electrode 160 also for loading grid voltage on trench-gate 130.When opening MOSFET element 100, in body zone 135, a passage (not indicating in figure) can be formed in the place of adjacent trenches grid 130.
P-epitaxial loayer 110 and with sidewall, the groove that covered by N epitaxial loayer 115 and lightly doped N-epitaxial loayer 116, forms nano tube structure, obtains charge balance to make MOSFET element.The present invention proposes a kind of high tension apparatus of charge balance, this device can be prepared efficiently.N side wall layer 115, i.e. nanotube, the neighbouring part with P epitaxial loayer 110 reaches charge balance, and make N side wall layer 115 form the drift region of MOSFET, this drift region exhausts under Disconnected mode.P-epitaxial loayer 116 also comprises a N-type implantation region 117 be positioned at below body zone 135, so that by expanding channels on the drift region in N side wall layer 115.By exhausting N epitaxial loayer from opposite side, and allow higher charge storage in N epitaxial loayer 115, P-epitaxial loayer 116 can provide further charge balance, and improves Rdson.Such as, if the P-type charge storage increasing by 25% is again in P-epitaxial loayer 116, so just can increase by the N-type charge storage of 25% again in N-epitaxial loayer 115, thus make Rdson reduce by 25%.P-side wall layer 116 also fully fills the bottom of deep trench.This can make to remain the smaller in length and breadth of gap in groove, can fill these gaps like a cork, thus avoid the preparation problems such as formation cavity with oxidation filler 120.Oxidation filler 120 makes trench-gate 130 and drain potentials insulate, and reduces grid-drain capacitance.
About 1 micron wide of N-epitaxial loayer 115, about 6 microns wide of the P epitaxial loayer 110 between adjacent N-epitaxial loayer 115, this only exemplarily, not as limitation.Can think that P epitaxial loayer 110 has two halves, the width of every half is all 3 microns, and keeps charge balance with N epitaxial loayer 115.The part of N epitaxial loayer 115 and P epitaxial loayer 110 charge balance, the concentration of electric charges had is about 1E12cm -2, therefore the doping content of P epitaxial loayer 110 is 3.33E15cm -3, the doping content of N epitaxial loayer 115 is 1E16cm -3.In addition, the concentration of electric charges that the P epitaxial loayer 116 of 1 micron wide has is 0.25E12cm -2, doping content is 2.5E15cm -3, the doping content of N epitaxial loayer 115 can be elevated to 1.25E16cm -3, thus reduce Rdson.
Fig. 4 represents an embodiment of groove nanotube (MOSFET) device 100-1 of the present invention.MOSFET element 100-1 is except the P-epitaxial loayer 116 shown in lightly doped N--epitaxial loayer 116-1(instead of Fig. 3) grow except on N+ epitaxial loayer 115, other are all similar with the MOSFET element 100 shown in Fig. 3.Therefore, N-type implantation region 117 is not needed in MOSFET element 100-1.Next the bottom of lightly doped N--epitaxial loayer 116-1 also abundant filling groove, so that form oxidation filler 120.After forming N epitaxial loayer 115, same epitaxial chamber can be utilized to prepare N--epitaxial loayer 116-1, and P epitaxial loayer 116 will be grown, just need wafer to move to another growth room, therefore use N--epitaxial loayer 116-1 to be easier to preparation than P epitaxial loayer 116.This also increases the output of device.In one alternate embodiment, N epitaxial loayer 116-1 can replace with a lightly doped P--layer of intrinsic-OR.
Fig. 5 represents an embodiment of groove nanotube (MOSFET) device 100-2 of the present invention.MOSFET element 100 shown in MOSFET element 100-2 and Fig. 3 is substantially similar, and just groove is wider, and the P epitaxial loayer 116-2 be formed in above N+ epitaxial loayer 115 is only served as a contrast in groove, can not fully bottom filling groove.On the contrary, the overwhelming majority that filler 120-2 is filled with channel bottom is oxidized.
Fig. 6 represents an embodiment of groove nanotube (MOSFET) device 100-3 of the present invention.MOSFET element 100 shown in MOSFET element 100-3 and Fig. 3 is substantially similar, just P epitaxial loayer 116-3 is except the bottom below oxidation filler 120-3 is thicker, in most of region, P epitaxial loayer 116-3 is very thin, to such an extent as in that region N+ epitaxial loayer 115-3 all with its counter-doping.If it is an option that implement isotropic light etching after growth P epitaxial loayer 116-3, so just this structure can be formed.Isotropic etching can remove the marginal portion of P epitaxial loayer 116-3, leaves the bottom of P epitaxial loayer 116-3.
Fig. 7 represents the profile of N-channel insulation grid bipolar transistor (IGBT) device 101 with groove nano tube structure of the present invention.This IGBT device 101 is formed in P-type epitaxial loayer 110, and P-type epitaxial loayer 110 is positioned on substrate P layer 105-1, and as the collector electrode of IGBT, N-passage cutoff layer 108 is deposited between P-epitaxial loayer 110 and P+IGBT emission layer 105-1.IGBT device 101 and the similar of the MOSFET element shown in Fig. 3, also comprise the multiple groove nanotubes be formed in epitaxial loayer 110, containing multiple groove in groove nanotube.The groove formed is with sidewall, and sidewall has small inclination angle, and the groove core that each trenched side-wall is coated with a N nanotube layer 115, P-epitaxial loayer 116 and fills with silica 120.IGBT device 101 also comprises trench-gate 130, and trench-gate 130 is formed in groove top, by grid oxic horizon 125 filling bag round, and to be insulated by silicon oxide layer 120 and N+ side wall layer 115.IGBT device 101 also comprises the body zone around trench-gate.Each body zone is containing a P-body zone 135 be deposited on below heavily doped P+ body contact region 140.IGBT device 101 also comprises source area, N+ source area 145, N+ 145 and is deposited on adjacent top surface, and is surrounded by P body zone 135 and 140.IGBT device 101 also comprises a barrier metal layer 150, and source area 145 and body zone 140 are connected on emitter electrode 155 by barrier metal layer 150.Form a gate electrode 160 again, to load grid voltage on trench-gate 130.
P-epitaxial loayer 110 and the groove with the sidewall covered by N epitaxial loayer 115 formed, form nano tube structure, to form the drift region of charge balance in IGBT device.
Fig. 8 represents that the charge injection with groove nano tube structure of the present invention controls the profile of diode.Schottky diode 162 in Fig. 9 Fig. 8 and PN junction diode 161, represent the circuit diagram of the equivalent electric circuit of charge injection adjustable resistor R1 163.Charge injection adjustable resistor R1 163 connects with PN junction diode 161, and PN junction diode 161 is in parallel with Schottky diode 162.Resistor 163 can be integrated in device, such as, as a metal and polyresistor, or also can be external in device, makes user can select required resistance value.P-type epitaxial loayer 110 is positioned on N/N+ substrate layer 105, as the negative electrode of PN junction diode and Schottky diode.Ohmic contact to P epitaxial loayer 110 is formed in the third dimension, until P+ district 176.Schottky diode and PN junction diode are all positioned on P epitaxial loayer 110, and the P epitaxial loayer 110 formed is with multiple groove nanotube, and groove nanotube contains multiple groove.The groove formed is with sidewall, and sidewall has small inclination angle, and the groove core that each trenched side-wall is coated with N nanotube layer 115, P-epitaxial loayer 116 and fills with silica 120.Wider groove can be formed on darker oxidation filler 121 wider than other oxidation filler 120.When they are formed on same semiconductor wafer, contribute to like this being separated different devices.Schottky diode contains a N-district 165, and Schottky contact metal 170 is covered with the end face in N district 165.N district 165 is deposited on above nanotube 115, near oxide layer 120, and contacts with P epitaxial loayer 110 and N doped region 115.PN junction diode contains a P/P+ district 175/176, and ohmic contact metal layer 180, as a modulation grid, covers on the end face in P/P+ district 175/176.P district 175 contacts with P epitaxial loayer 110 and nanotube layer 115.Resistor R1 163 controls the injection energy level in P-N junction diode, is by reducing voltage in whole PN junction diode (by voltage V r1=I diode* R1), cause the quantity of electric charge that PN junction diode stores to reduce, Reverse recovery is enhanced.The value of resistor R1 is comparatively large, and Reverse recovery can be made to strengthen, and conductivity modulation reduction brings less forward conduction.The less meeting of value of resistor R1 brings reverse effect.Schottky diode is in parallel with PN junction diode, the quantity of electric charge stored in PN junction diode can be reduced further.The size of changing resistor R1 163, can control the performance of the quantity of electric charge and the diode stored in PN junction diode 161.PN junction diode reduces the leakage current of high pressure (HV) Schottky diode, optimizes the forward drop Vf of multiple device.
As shown in the profile of Figure 10 and Figure 11, Schottky diode (representing with N district 165) and PN junction diode (representing with P/P+ district 175/176) are positioned on the same striped of epitaxial loayer 110.
Figure 12 representation class is similar to the MOSFET element shown in Fig. 3, with the side cut away view of the MOSFET element 102 of groove nano tube structure.P epitaxial loayer 110, as the epitaxial loayer 110 ' of a classification, also grows formation three P doped layers 110-1,110-2 and 110-3 with the three step epitaxy by three kinds of different levels of doping.Epi dopant concentration increases with the increase of height, and that is the doping content of bottom P doped layer 110-1 is minimum, and the doping content of top P doped layer 110-3 is the highest.The epitaxial loayer 110 ' of classification, by being moved down from the top of epitaxial loayer is past breakdown region, improves the UIS of device.And, by breakdown field is moved down in P epitaxial loayer 110, make the electric charge being injected into P epitaxial region 110 more than N district 115, also can improve UIS.Although for the preparation of classification epitaxial loayer in this example is three step epitaxy layer, also can use the epitaxial loayer of more multistep.Also can the epitaxial loayer of the single classification gradually of choice for use, its doping content reduces from top to bottom gradually.
Figure 13 and Figure 14 represents the side perspective view of two kinds of different components as cord elements.In order to explain explanation, do not indicate source electrode and body zone herein---only indicate grid and epitaxial loayer.The device that Figure 13 represents is similar to the device 100-1 shown in Fig. 4, and the device that Figure 14 represents is similar to the device 100 shown in Fig. 3.Figure 15 represents the vertical view of device shown in Figure 14, and locus of discontinuity 122 is arranged in grid 130, close part P-epitaxial loayer 116.Mask makes oxidation filler 120 in preparation process, is not etched in region 122.Same mask also makes not implanted P-type implant 117, P-type implant 117 in the P-epitaxial loayer 116 of locus of discontinuity 122 implant along groove in other places.In the place with exposed P-epitaxial loayer 116, in order to keep charge balance, the connection from source voltage to P-epitaxial loayer 116 can be set up.Can select, not form locus of discontinuity 122 in grid 130, the implantation process forming P-type implant 117 is not that top layer is implanted yet, but with mask, thus allow the non-return doping in region of P-epitaxial loayer 116, and be connected on source voltage.Also it is an option that this effect also can be reached by the P-type implantation step with mask, thus formation P-type implant 117 creates the region that P-epitaxial loayer 116 is exposed.
Figure 16 and Figure 17 represents the vertical view of the MOSFET element with closure elements.Closure elements is as shown in Figure 16 and Figure 17 compared with striated structure, in the closure elements with the silicon mesa structure of 3 microns of 6 × 6 (i.e. the groove opening of the P-district of 2.5 microns, the N-ring of 0.25 micron and 3 microns), closure elements as shown in Figure 16 and Figure 17 can reduce the Rds resistance of about 30%.Figure 16 represents the closure elements layout of the nano tube structure without source electrode or body zone.P-epitaxial loayer 110 is positioned at the center of each closure elements, and is surrounded by N-type nanotube 115 and N--epitaxial loayer 116.Trench-gate 130 and gate oxide 125 are round closure elements.Represented by Figure 17 is source electrode and body zone, and P+ body contacts 140 is positioned at the center of each closure elements, is surrounded by N+ source area 145.In order to simplify, in figure, do not indicate P-implantation region 117.Also can select, when the location swap of trench-gate and semiconductor, use the closure elements with discontinuous grid, make Semiconductor substrate (comprising source electrode and body) surround trench-gate, trench-gate is positioned at the center of closure elements.
Figure 18 representation class is similar to the MOSFET element 102 shown in Figure 12, with the side cut away view of the MOSFET element of groove nano tube structure.P epitaxial loayer 110, as three P doped layers 110-1,110-2 and 110-3, is that the epitaxial process of three kinds of different levels of doping by successively decreasing successively is from top to bottom formed.MOSFET element also comprises a high pressure terminator, with a not only wide but also dark termination groove 189(such as 30 microns), and fill with dielectric material 190 and oxide 120 and stop groove 189.The termination groove 189 formed is with the initial network of a groove of filling with oxide 120, and it can be formed with the oxide 120 of active groove simultaneously.Semiconductor mesa structure (not indicating in figure) is between the network of oxide 120; Then etch away semiconductor mesa structure, dielectric material 190 is filled in produced gap.The terminal of terminator is the sawtooth block 195 be deposited on wafer peripheral edge.
Figure 19 to Figure 31 is a series of side cut away view, represents the preparation process with self aligned high pressure (HV) semiconductor power device being similar to nanotube shown in Fig. 3.Figure 19 represents initial N+ Semiconductor substrate 205, i.e. heavily doped N+ silicon substrate, carries the P-type epitaxial loayer 210 that growth is square on a substrate 205.P-type epitaxial loayer 210 also can find out it is upper strata Semiconductor substrate, and N+ Semiconductor substrate 205 can regard underlying semiconductor substrate as.Can growth selection P-type epitaxial loayer 210, have the P-doping content that three kinds or more kind is different, or have the doping content of classification gradually, its doping content reduces from top to bottom gradually.Then, oxide layer 211 and silicon nitride (Si3N4) layer 212 is formed, as hard mask.In fig. 20, utilize trench mask (not indicating in figure) first to etch hard mask, comprise oxide layer 211 and silicon nitride layer 212.Then carry out silicon etching, in epitaxial loayer 210, open groove 213.The groove width opening groove 213 is about 3.5 microns, and gash depth is about 36 to 40 microns, and side wall angle is about 88 degree.N nanotube layer 215 epitaxial growth is above N nanotube layer 215, and thickness is about 0.25 to 0.5 micron, with arsenic dopants doping, as shown in figure 21.P-epitaxial loayer 216 can grow above N nanotube layer 215.As shown in figure 22, due to the size of groove 213 and the sidewall of inclination, N--epitaxial loayer 216 is fully filled with the bottom of groove.Then, as shown in figure 24, very thin high-density plasma (HDP) oxide layer 220 is deposited in groove, and filling groove.
In fig. 24, utilize back etching process and/or CMP (CMP) technique, the silica (SiO2) 220 on removing end face, until silicon nitride layer 212 is out exposed.Use trench-gate mask (not indicating in figure), oxide layer 220 is etched into the degree of depth of about 1.5 to 2.0 microns.As shown in figure 25, utilize N-type to implant, the exposed sidewall of P-epitaxial loayer 216 forms N-type implant 217.
In fig. 26, form the grid oxic horizon 225 that thickness is about 350-1200 dust, cover on sidewall along P-epitaxial loayer 216.Deposition of gate polysilicon layer 230, preferably selects the in-situ doped polysilicon layer of N+.Back etch polysilicon 230, utilizes CMP its end face smooth, and removes hard mask oxide layer 211 and silicon nitride (Si3N4) layer 212.Further etches polycrystalline silicon layer 230, form the grid 230 of a slight depression, the end face of grid polycrystalline silicon 230 is more about than mesa surfaces low 0.3 micron.Then a cushion oxide layer 232 is grown in top face.
In figure 27, utilize high-energy boron or P-bulk doped to implant, form body zone 235.Carry out high energy bulk doped when implanting, with certain inclination angle, to stop the negative mesa structure angle due to trenched side-wall, and produce in region near trenched side-wall and cover.After raised temperature, carry out bulk doped driving, body zone 235 is diffused in P-epitaxial loayer 210, N nanotube layer 215 and N--epitaxial loayer 216.Then, when close to zero degree, carry out weight boron and implant, so that the adjacent top surface above body zone 235 forms P+ body contact region 240.In Figure 28, utilize source mask (not indicating in figure) to carry out the phosphorous N+ of low energy and implant, to form the N+ source area 245 be enclosed in P-body zone 235 and P+ district 240.Under 900 degrees Celsius, annealing process is utilized to carry out implantation activation 30 minutes.In one alternate embodiment, at a higher temperature, N-type implantation is carried out, to produce the N-type region imbedded below P-body zone 235, equally for MOSFET channel region being connected to the N epitaxial loayer 215 as N-type implant 217.
Then, end face forms a silicon nitride (Si3N4) hard mask layer (not indicating in figure).Termination mask (not indicating in figure) is utilized to carry out isotropic silicon etching in terminator, to open groove (not indicating in figure) in the mesa region in the terminator between silicon oxide layer, then fill the mesa structure groove (dielectric layer 190 such as shown in Figure 18) after etching with dielectric or SiO2.Back etch media layer 190, until hard mask layer is out exposed, then etches and removes hard mask (not indicating in figure).These techniques in terminator as shown in figure 11.As shown in Figure 29, silex glass (BPSG) passivation layer 250 of deposition containing boric acid.In fig. 30, utilize contact mask (not indicating in figure), open the contact openings through bpsg layer 250.In Figure 31, at deposited on top metal level, then utilize metal mask (not indicating in figure), form the pattern of source metal 260-S and gate pad (not indicating in figure) on the metal layer.Also form a metal level in the bottom of substrate 205, to prepare drain metal 205-D, thus complete whole super junction nanotube MOSFET 200.
Be a series of side cut away view see Figure 32 to Figure 41, represent a kind of preparation process of terminator of autoregistration high pressure (HV) semiconductor power device with nanotube as shown in Figure 3.Figure 32 represents initial N+ Semiconductor substrate 205(such as heavy N+ doped silicon substrate), carry P-type epitaxial loayer 210, P-type epitaxial loayer 210 as layer 210-1,210-2 and 210-3, by three kinds of different doping contents, growth above substrate 205.The P-type epitaxial loayer 210 grown also can have the doping content of classification gradually, and its doping content reduces from top to bottom gradually.Then, oxide layer and silicon nitride (Si3N4) layer 212 is formed, as hard mask.In fig. 33, utilize trench mask (not indicating in figure), first etch hard mask 212, comprise an oxide layer and a silicon nitride layer.Then, utilize silicon etching open active groove 213b and stop groove 213a, enter in epitaxial loayer 210.The gash depth opened is about 36 to 40 microns, and side wall angle is about 88 degree.The width stopping groove 213a may be greater than active area groove 213b, and to ensure as shown in the figure, the oxide be filled in these grooves arrives channel bottom.Then, at sidewall Epitaxial growth N-extension nanotube layer 215 of groove 213a and 213b, its thickness is about 0.25 to 0.5 micron, and adulterates by arsenic dopants, epitaxial growth P-epitaxial loayer 216 above N nanotube 215 subsequently.As shown in figure 34, deposit in the trench and be filled with thin HDP oxide layer 220.It should be noted that due to the width that stops groove 213a comparatively large, although the abundant bottom of filling active area trenches 213b of P-epitaxial loayer 216, only can fill the skim lining stopping groove 213a.Therefore, oxide layer 220 in the degree of depth stopping filling in groove 213a much smaller than the degree of depth in active groove 213b.Not only dark but also wide oxide can be used to fill wider groove at borderline region, so that when preparing different components on same semiconductor wafer, distinguish the device that these are different.
Then, utilize back etch process and/or CMP (CMP) technique, the oxide layer 220 on removing end face, until silicon nitride layer 212 is out exposed.At this moment, the network of an oxidation column 223 can be formed in terminator, in the network containing semiconductor mesa structure 224.Terminator is covered with wide groove 213a, utilizes the trench-gate mask 218 being covered with terminator, is etched with the oxide layer 220 in the groove 213b of source region.Then, as shown in figure 35, the exposed sidewall along P-epitaxial loayer 216 carries out N-type implantation, preparation N-type implantation region 217.As shown in figure 36, by the liner of grid oxic horizon 225, prepare polysilicon gate 230.Now, the hard mask 212 on active area can be removed.Then, as mentioned above, He Chong P+ district, P-body base region 235 240 is formed.Utilize source mask (not indicating in figure), as mentioned above, in active cell district, implant and form N+ source area 245, as shown in figure 37.In Figure 38, utilize and stop hard mask 249, trench-gate mask 218 is removed together with remaining hard mask 212.In Figure 39, utilize silicon etching, etching semiconductor mesa structure 224, i.e. epitaxial loayer 210-1,210-2 and 210-3, between the oxide layer 220 of terminator, leave interim etching groove 222.In Figure 40, be filled in the etching groove 222 between the oxide layer 220 in terminator with dielectric material 290, to fill the etching mesa structure in terminator, form not only dark but also wide termination oxidation groove 289.In Figure 41, removing stops hard mask 249, carries out the subsequent treatment process as shown in Figure 29 to Figure 31, completes the preparation of the MOSFET element with special terminator as shown in figure 18.
Figure 42 is vertical view, Figure 43 and Figure 44 is respectively the profile along A-A ' line and B-B ' line of the MOSFET element as shown in figure 42 with plane termination structure.For clarity, although substantially indicate the electrical connection formed by metal level, vertical view does not indicate the top of metal, oxide and passivation layer, and as shown in Figure 18 and Figure 41, plane termination is an embodiment of wide oxidation groove.In plane termination structure, terminator 199 ' comprises the mesa structure 110 ' being similar to active area, and mesa structure 110 ' is positioned between oxide layer 120 ', fills in the trench, and be covered with by N doped epitaxial layer 115 ' with sidewall.Stop the source/body district 135,140 and 145 that unit does not have active cell 198 '.On the contrary, as shown in Figure 42 to Figure 44, P-mesa structure is connected by metal level 150-1 to 150-5 with N-epitaxial loayer, to make the specific pinch-off voltage VPT of each termination unit locking one.Passivation layer 195 ' can covering metal layer 150-1 to 150-5.
Last active cell (as shown in left side in figure), when source voltage is 0 volt, by metal level 150-1, is shorted to the P-mesa structure (and the polysilicon block 130 ' in centre) of the first termination unit.Or rather, metal level 150-1 is connected to 135' Nei P+ district of P district 140 '.The N-epitaxial loayer 115 ' of P-mesa structure 110 ' and surrounding exhausts, and the voltage of N-epitaxial loayer is increased to pinch-off voltage V pT1, voltage when namely N-epitaxial loayer and P-mesa structure exhaust.On N-epitaxial loayer 115 ' is connected to the N+ district 140 ' surrounding the first termination unit ' N district 135 ' ', the N+ district 140 ' of the first termination unit ' be shorted on the next P-mesa structure stopping unit (the next unit on right side) by metal level 150-2, owing to exhausting in this unit, voltage is made to increase again a V pT1, thus make total voltage now be V pT2≈ 2*V pT1.Until when reaching operating voltage (drain voltage) of device, this situation just can stop.See Figure 45, first by source potential as the reference voltage, the such as V=0 of metal level 150-1, voltage increases gradually in the gradual mode of pinch off step 155, makes the voltage at metal level 150-2 place be V pT1.Voltage delivery increases to V pT1, then reach the V at metal level 150-3 place pT2, be finally elevated to device voltage, i.e. 600 volts of predeterminated voltages at an in the end metal level 150-n place, as in Figure 45 near shown in the line of semiconductor chip edge.
In oxidation groove 120 ', form polysilicon block 130 ', to prevent electric charge and dirt from entering the oxide be oxidized in groove, thus improve the reliability of device.Because plane termination structure is compared with wide oxidation groove, need larger lateral separation, to intercept operating voltage, therefore wide oxidation groove termination structure is as shown in figure 18 not compact for this plane termination structure.Should also be noted that with the groove in above-mentioned active cell district similar, open with silica-filled groove in terminator, also with the sidewall tilted slightly.
Figure 46 represents a kind of profile being similar to the IGBT device 101 ' shown in Fig. 7, and this IGBT device 101 ' is with to be similar to the schottky device 162 ' shown in Fig. 4 mutually integrated.With the wide groove of not only dark but also wide oxidation filler 121, device is separated.In this case, by the bottom of Semiconductor substrate backgrind to not only dark but also wide oxidation filler 121.In the bottom of semi-conducting material, implanted with n-type layer 108 ' and P-type layer 105-1 '.Because IGBT has embedded type diode unlike MOSFET, therefore this embodiment is very useful.Should it is clear that, be 12/484, described in 166 as U.S. Patent Application No., backgrind carried out to the single P-substrate without initial epitaxial layer and after implanting, device can be formed with this single P-substrate.As shown in figure 47, preparing this structure also can without the need to backgrind, P-type layer 150-1 ' ' to be implanted to a part of N-type Semiconductor substrate 108 ' ' in.
Although the present invention has described existing preferred embodiment in detail, should as limitation of the present invention.Such as, described in illustrating although above is n-passage device, and the present invention, by being reversed by the conduction type of doped region, also can be used for p-passage device.Various different device can be prepared, comprise those devices with planar gate.After those skilled in the art reads above-mentioned detailed description, various changes and modifications undoubtedly will be apparent.Therefore, appending claims should contain whole change in true intention of the present invention and scope and correction.
Although content of the present invention has done detailed introduction by above preferred embodiment, will be appreciated that above-mentioned description should not be considered to limitation of the present invention.After those skilled in the art have read foregoing, for multiple amendment of the present invention and substitute will be all apparent.Therefore, protection scope of the present invention should be limited to the appended claims.

Claims (6)

1., with a preparation method for the device architecture of groove-oxide-nanotube super junction, it is characterized in that, comprise:
Etching groove in the second semiconductor layer of the second conduction type;
In described groove, growth first conduction type the first epitaxial loayer and
Above the first described epitaxial loayer, grow second epitaxial loayer;
Wherein the first semiconductor layer of the first conduction type is positioned at below the second described semiconductor layer, and
The first wherein said epitaxial loayer touches the first semiconductor layer.
2. preparation method as claimed in claim 1, it is characterized in that, the semiconductor regions of described first epitaxial loayer and surrounding reaches charge balance.
3. preparation method as claimed in claim 1, is characterized in that, grow the second epitaxial loayer, make the bottom of the abundant filling groove of described second epitaxial loayer.
4. preparation method as claimed in claim 1, is characterized in that, also comprise: after growing described second epitaxial loayer, with gap remaining in dielectric filler groove.
5. preparation method as claimed in claim 4, is characterized in that, also comprise:
Behind gap remaining in dielectric filler groove, back etching dielectrics, and a trench gate electrode is formed in the top of at least some groove.
6. preparation method as claimed in claim 4, is characterized in that, also comprise:
When the groove described in etching, etch the groove in terminator, by the semiconductor mesa structure stayed between Filled Dielectrics groove, to form the network of Filled Dielectrics groove in terminator simultaneously; And
Etch away the semiconductor mesa structure in terminator, and with second medium filler packing space, so that the dielectric trenches that formation one is not only wide but also dark in terminator.
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CN107910374A (en) * 2017-12-13 2018-04-13 深圳市晶特智造科技有限公司 Superjunction devices and its manufacture method

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102610643B (en) * 2011-12-20 2015-01-28 成都芯源系统有限公司 Trench MOSFET device
CN103378171B (en) * 2012-04-28 2017-11-14 朱江 A kind of groove Schottky semiconductor device and preparation method thereof
US9685511B2 (en) * 2012-05-21 2017-06-20 Infineon Technologies Austria Ag Semiconductor device and method for manufacturing a semiconductor device
CN103681778B (en) * 2012-09-09 2017-04-26 朱江 Groove charge compensation schottky semiconductor device and preparation method thereof
CN103413763B (en) * 2013-08-22 2016-09-28 上海华虹宏力半导体制造有限公司 Super junction transistor and forming method thereof
CN104681438B (en) * 2013-11-27 2017-10-20 上海华虹宏力半导体制造有限公司 A kind of forming method of semiconductor devices
TWI567974B (en) * 2014-07-28 2017-01-21 萬國半導體股份有限公司 Termination design for nanotube mosfet
JP2017050423A (en) * 2015-09-02 2017-03-09 株式会社東芝 Semiconductor device manufacturing method
CN105405889B (en) * 2015-11-04 2019-01-08 中国科学院微电子研究所 A kind of groove MOSFET with comprehensive current expansion path
CN105655385B (en) * 2016-01-15 2018-08-21 上海华虹宏力半导体制造有限公司 The manufacturing method of groove-shaped super-junction device
WO2018107429A1 (en) * 2016-12-15 2018-06-21 深圳尚阳通科技有限公司 Super junction component and manufacturing method therefor
CN106847923B (en) * 2017-02-08 2019-10-11 上海华虹宏力半导体制造有限公司 Superjunction devices and its manufacturing method
CN107068735A (en) * 2017-03-16 2017-08-18 上海华虹宏力半导体制造有限公司 The manufacture method of groove-shaped super junction
CN107180865B (en) * 2017-06-30 2020-01-07 东南大学 Low-noise low-loss insulated gate bipolar transistor
CN109273439A (en) * 2018-09-14 2019-01-25 深圳市心版图科技有限公司 A kind of power device protection chip and preparation method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101083282A (en) * 2006-05-30 2007-12-05 半导体元件工业有限责任公司 Semiconductor device having sub-surface trench charge compensation regions and method
CN101421836A (en) * 2004-12-27 2009-04-29 三维半导体公司 Process for high voltage superjunction termination
CN101471254A (en) * 2007-12-27 2009-07-01 佳能株式会社 Method for forming dielectric films
JP2009188177A (en) * 2008-02-06 2009-08-20 Fuji Electric Device Technology Co Ltd Semiconductor element, and method of manufacturing the same

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4088033B2 (en) * 2000-11-27 2008-05-21 株式会社東芝 Semiconductor device
EP1261036A3 (en) * 2001-05-25 2004-07-28 Kabushiki Kaisha Toshiba Power MOSFET semiconductor device and method of manufacturing the same
JP4695824B2 (en) * 2003-03-07 2011-06-08 富士電機ホールディングス株式会社 Manufacturing method of semiconductor wafer
US7638841B2 (en) * 2003-05-20 2009-12-29 Fairchild Semiconductor Corporation Power semiconductor devices and methods of manufacture
JP4903055B2 (en) * 2003-12-30 2012-03-21 フェアチャイルド・セミコンダクター・コーポレーション Power semiconductor device and manufacturing method thereof
US7176524B2 (en) * 2005-02-15 2007-02-13 Semiconductor Components Industries, Llc Semiconductor device having deep trench charge compensation regions and method
US7750398B2 (en) * 2006-09-26 2010-07-06 Force-Mos Technology Corporation Trench MOSFET with trench termination and manufacture thereof
CN100589253C (en) * 2008-04-29 2010-02-10 西安理工大学 Oxide filling extension groove grid super node MOSFET and its making method
US20090315104A1 (en) * 2008-06-20 2009-12-24 Force Mos Technology Co. Ltd. Trench MOSFET with shallow trench structures

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101421836A (en) * 2004-12-27 2009-04-29 三维半导体公司 Process for high voltage superjunction termination
CN101083282A (en) * 2006-05-30 2007-12-05 半导体元件工业有限责任公司 Semiconductor device having sub-surface trench charge compensation regions and method
CN101471254A (en) * 2007-12-27 2009-07-01 佳能株式会社 Method for forming dielectric films
JP2009188177A (en) * 2008-02-06 2009-08-20 Fuji Electric Device Technology Co Ltd Semiconductor element, and method of manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106229335A (en) * 2016-08-01 2016-12-14 上海华虹宏力半导体制造有限公司 Method for filling deep trench
CN107910374A (en) * 2017-12-13 2018-04-13 深圳市晶特智造科技有限公司 Superjunction devices and its manufacture method

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