CN203659870U - Super junction device and semiconductor structure comprising same - Google Patents
Super junction device and semiconductor structure comprising same Download PDFInfo
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- CN203659870U CN203659870U CN201320674971.5U CN201320674971U CN203659870U CN 203659870 U CN203659870 U CN 203659870U CN 201320674971 U CN201320674971 U CN 201320674971U CN 203659870 U CN203659870 U CN 203659870U
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 77
- 230000001413 cellular effect Effects 0.000 claims description 3
- 230000007246 mechanism Effects 0.000 claims description 3
- 210000000746 body region Anatomy 0.000 abstract 3
- 239000010410 layer Substances 0.000 description 51
- 230000015572 biosynthetic process Effects 0.000 description 8
- 239000003990 capacitor Substances 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000005457 optimization Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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Abstract
A super junction device and a semiconductor structure comprising the same are disclosed. The super junction device comprises a semiconductor body having first and second surfaces, a source region of a first electric conduction type, a drain region of a first electric conduction type, a body region of a second electric conduction type, a drift region, and a groove gate structure extending from the first surface to first regions of the drift region, wherein the source region in the semiconductor is placed at the first surface, the drain region in the semiconductor is placed at the second surface, the body region in the semiconductor body is arranged between the source region and the drain region, the drift region in the semiconductor body is arranged between the body region and the drain region, the drift region consists of the first regions of the first electric conduction type and second regions of the second electric conduction type, and the first regions and the second regions are arranged alternately along a direction parallel to the first surface. The groove gate structure comprises a groove in the semiconductor body, a gate electrode in the groove and a first grid electrode oxide layer arranged between the semiconductor body and the gate electrode, wherein the first gate electrode oxide layer surrounds the gate electrode. A part, arranged a between the bottom part of the gate electrode and the bottom part of the groove, of the first gate electrode oxide layer is 150 nm to 600 nm in thickness.
Description
Technical field
The utility model relates to field of semiconductor devices, more particularly, relates to the super junction device and the semiconductor structure that comprises this super junction device of the groove structure with optimization.
Background technology
In recent years, super junction device is applied more and more widely.In the conventional super junction device of n raceway groove, the p post of alternative arrangement and n column combination form compound buffer layer, are used for replacing the N-shaped epitaxial loayer in MOSFET device.Typical p post in compound buffer layer is surrounded by adjacent n post, and typical n post is surrounded by adjacent p post.
To surpass junction transistors as example, at drain source voltage V
dSwhen≤50V, due to exhausting fast of n post and p post, super junction transistors can realize very high switching speed and low-down switching loss.But this may cause ring trend to become large, it even may cause damaging device.Therefore, should avoid at high V
dSunder low-down grid-drain capacitance C
gD.In addition, grid-source capacitor C
gSincrease be more satisfactory because it can reduce grid voltage V
gSamplitude, this grid voltage V
gSamplitude be for example by by stray inductance or drain voltage V in source electrode connection line
dSthe rising feedback generation that causes.This can contribute to for example to be avoided dV under normal use condition
dSthe startup that/dt causes.On the other hand, under extreme dV/dt and dI/dt condition, for example, under commutation condition, by dV
dSthe startup that/dt causes may be needed.
For optimised devices, especially carry out optimised devices for the groove unit that is easy to have higher transconductance, importantly select the C optimizing
gD/ C
gSthe absolute C of ratio and optimization
gDand C
dSvalue.Therefore, need to modify so that device capacitor adapts to depend on V to transistor unit structure
dSdifferent application requirements.
For power transistor, especially super junction transistors, it is upper that gate pads is generally disposed in thick-oxide (oxygen), and the typical thickness of this thick-oxide is >=1 μ m, or at least >=500nm.This advantage having be utilize toe-in to close gate pads is connected to the bond strength of grid connection line in when encapsulation higher.Above-mentioned electric capacity depends on the size of gate pads, grid potential is distributed in to the region of the additional metal line such as grid slideway or gate fingers on chip, oxidated layer thickness and the doped level below gate pads.The electric capacity of gate pads can also contribute to require to optimize described device for the electric capacity of optimizing switching characteristic.
Utility model content
The purpose of this utility model is to provide a kind of super junction device of the groove structure with optimization and comprises the semiconductor structure of this super junction device.
To achieve these goals, according to an aspect of the present utility model, provide a kind of super junction device, this super junction device comprises:
There is the semiconductor body on the first and second surfaces;
Be arranged in the source region of the first conduction type of described semiconductor body at first surface place;
Be arranged in the drain region of the first conduction type of described semiconductor body at second surface place;
The tagma of the second conduction type in the described semiconductor body between described source region and described drain region;
Drift region in described semiconductor body between described tagma and described drain region, described drift region is to be formed by the firstth district of the first conduction type and the Second Region of the second conduction type of the direction alternative arrangement along being parallel to described first surface; With
Trench gate structure, it extends to described firstth district of described drift region from described first surface, wherein said trench gate structure is included in the groove in described semiconductor body, the gate electrode in described groove and between described semiconductor body and described gate electrode and around the first grid oxide layer of described gate electrode
It is characterized in that,
The thickness of the part between the bottom of described gate electrode and the bottom of described groove of described first grid oxide layer is in the scope of 150 nm-600 nm.
In certain embodiments, the degree of depth > 2 μ m of described groove.
In certain embodiments, the degree of depth > 3 μ m of described groove.
In certain embodiments, the thickness of the part between the bottom of described gate electrode and the bottom of described groove of described first grid oxide layer is in the scope of 300 nm-600 nm.
In certain embodiments, any part of the described first grid oxide layer between the sidewall of described gate electrode and the sidewall of described groove is all not more than 150 nm in cellular zone.
According to an aspect of the present utility model, a kind of semiconductor structure is provided, this semiconductor structure comprises:
The active cell district being formed by multiple described super junction devices;
Surround the semiconductor region in described active cell district and be formed on the second grid oxide layer on described semiconductor region;
Embed the grid slideway in described second grid oxide layer; With
Embed the field plate in described second grid oxide layer,
It is characterized in that,
The thickness of the second grid oxide layer below described field plate is greater than the thickness of the second grid oxide layer below at least a portion of described grid slideway.
In certain embodiments, in an end of described grid slideway, at least a portion of described grid slideway is arranged in the groove of described semiconductor region, and is surrounded by described second grid oxide layer in described groove.
In certain embodiments, described semiconductor structure also comprises the gate pads being positioned in described second grid oxide layer, and described gate pads is by least one through hole and described grid slideway electric connection.
In certain embodiments, the drain electrode short circuit of described field plate and described super junction device is to form the termination mechanism of described semiconductor structure.
In certain embodiments, described semiconductor region by the firstth district of the first conduction type and the Second Region of the second conduction type along the Width alternative arrangement of described semiconductor region and form.
In certain embodiments, the thickness of the second grid oxide layer below another end of described grid slideway is identical with the thickness of the second grid oxide layer below described field plate.
In certain embodiments, be arranged in the source electrode that described semiconductor region and the described Second Region below described grid slideway are connected to the tagma of described super junction device or are connected to described super junction device by contact.
In certain embodiments, the thickness of the second grid oxide layer below described at least a portion of described grid slideway is less than 150 nm.
By implementing according to the super junction device of embodiment of the present utility model, can adjust according to demand the grid-drain capacitance C of (for example increase or reduce) super junction device
gD.For example, when gate electrode, to be filled the degree of depth of groove at place large (such as being greater than 2 μ m or 3 μ m) time, grid-drain capacitance C
gDcan be increased, thereby can reduce stray inductance or the drain voltage V in for example connecting by source electrode
dSthe feedback that produces of rising and the grid voltage V that causes
gSthe amplitude of spike.And for example, when bottom oxide thicker (thickness is greater than 150 nm or is even greater than 300 nm) below gate electrode in groove, grid-drain capacitance C
gDcan be reduced, thereby can reduce the also switching speed of the super junction device of raising of drain feedback.
In addition, by implementing according to the semiconductor structure of embodiment of the present utility model, below the gate pads of this semiconductor structure and/or grid slideway and/or gate fingers, adopt thinner grid oxic horizon (for example thickness is 150 nm) and below the field plate in grid potential, adopt thick grid oxic horizon, grid-drain capacitance C
gDalso can be increased, thereby can reduce grid voltage V
gSthe amplitude of spike.
Especially, for most of gate pads region, grid oxic horizon is general thinner than 150 nm, the gate electrode of being for example made up of polysilicon is deposited on the grid oxic horizon in groove (place at the end that approaches gate pads may exist oxide layer step or oxide layer slope, and the thickness of oxide layer is from the grid oxic horizon level increase oxygen level of showing up).Pad metal on gate electrode is connected to gate electrode by least one contact hole.If existence is connected to the p district of the source potential below gate pads/slideway, at least at low V
dSunder (depending on p doping content), drain-source capacitor C
dSincrease.
That gate pads may be according to the on state resistance R of super junction transistors by the issuable problem of variant part
dS, onand there is different capacitance profile.Due to gate pads area by the minimum dimension required assembling that is conventionally set to super junction transistors to minimize chip area and cost, therefore the less transistor size that is compared to of gate pads area and total chip area is maximum, i.e. high R
dS, on.For one group of R
dS, on-for the scope of the super junction transistors of identical basic technology, may expect that minimum transistor chip has the switching characteristic identical from maximum transistor so that user more easily replaces super junction transistors and meets different rated current or power.Thus, the area of gate electrode and maximum super junction transistors chip that gash depth is adjusted in a line are advantageously set and (there is minimum R
dS, ontransistor) switching characteristic, and (there is higher R along with super transistor chip becomes more and more less
dS, onvalue), reduce gradually the thin oxide region below gate electrode and/or increase the oxidated layer thickness of channel bottom.
Brief description of the drawings
These and other feature and advantage of the present utility model are by by becoming obviously below with reference to the detailed description of accompanying drawing, in the accompanying drawings:
Fig. 1 schematically shows according to the sectional view of the super junction device of an embodiment of the present utility model.
Fig. 2 schematically shows according to the sectional view of the super junction device of another embodiment of the present utility model.
Fig. 3 schematically shows according to the sectional view of the semiconductor structure that comprises super junction device of an embodiment of the present utility model.
Embodiment
Referring now to the accompanying drawing that embodiment of the present utility model is shown, embodiment of the present utility model is more fully described hereinafter.But the utility model can carry out specifically to implement and should not be construed as limited to embodiment described in this paper in many different forms.Or rather, it is in order to make the disclosure content more thoroughly with complete that these embodiment are provided, and will pass on all sidedly scope of the present utility model to those skilled in the art.Spread all in full, similar numeral refers to similar element.In addition, the Ceng He of each shown in accompanying drawing district is schematically and is not necessarily to scale.Therefore the utility model is not limited to the relative size shown in accompanying drawing, spacing and aligning.In addition, be familiar with as those skilled in the art, the layer being formed on substrate or other layer mentioned in this article can refer to be formed directly into the layer on substrate or other layer, the layer in one or more interlayer that also can refer to form on substrate or other layer.And term " the first conduction type " and " the second conduction type " refer to contrary conduction type, for example N or P type, but the each embodiment that describes and illustrate here also comprises its complementary embodiment.
The term that used is in this article just to describing the object of specific embodiment and being not intended to limit the utility model.As used herein, singulative " ", " one " and " being somebody's turn to do " intention also comprise plural form, unless otherwise clearly instruction of context.Also will understand, when using term " to comprise " herein and/or when " comprising ", it specifies the existence of feature, entirety, step, operation, element and/or the parts narrated, but does not get rid of existence or the interpolation of one or more further features, entirety, step, operation, element, parts and/or its cohort.
Unless otherwise limited, all terms (comprising technology and scientific terminology) that use herein have the implication identical with the implication of conventionally understanding as the utility model those skilled in the art.Also should be interpreted as thering is the implication consistent with they implications in background and the association area of this specification by understanding term as used herein, and by not explaining in mode idealized or form-separating excessively, so limit unless clear and definite in this article.
Accompanying drawing is by illustrating relative doping content at doping type " n " or " p " side instruction "-" or "+".For example, " n-" represents the doping content lower than the doping content of " n " doped region, and " n+ " doped region has than " n " the doping content that doped region is high.The doped region of identical relative doping content there is no need to have identical absolute doping content.For example, two different " n " doped regions can have identical or different absolute doping content.
Fig. 1 schematically shows according to the sectional view of the super junction device 100 of an embodiment of the present utility model.
In this example, for convenience's sake, super junction device 100 is described as an example of N-shaped device example.But super junction device 100 can be also p-type device.In addition, in certain embodiments, super junction device 100 can be super node MOSFET.
In this embodiment, drift region 130 comprises n district and the p district of multiple Width alternative arrangements along drift region, and wherein at least p district contacts p+ tagma 150, and these n districts and p district are as electric charge compensating region.In this case, between the n district in p+ tagma 150 source region 160 and drift region 130.Preferably, each in these n districts and p district is cylindricality, as shown in Figure 1.
In addition, super junction device 100 also comprises trench gate structure, and wherein groove is configured to extend into the n district of drift region 130 from the upper surface in tagma 150, and the basal surface of this groove is arranged in the n district of drift region 130.Gate electrode 170 is formed in groove, and has been full of oxide layer 180 in space between gate electrode 170 and groove.In other words, oxide layer 180 is surrounded gate electrode 170, thereby can be by gate electrode 170 and trench wall isolation.In one embodiment, this super junction device 100 also comprise be formed on source region 160 in case with the source electrode 184 of its formation ohmic contact and be formed on drain region 120 below in case with the drain electrode 110 of its formation ohmic contact.In this case, oxide layer 190 is formed on the top of gate electrode 170, to source electrode 184 and gate electrode 170 are insulated, as shown in Figure 1.In one embodiment, gate electrode 170 and source electrode 184 all can be made up of polysilicon or metal.
The formation of said structure can utilize semiconductor fabrication process well known to those skilled in the art to complete, and repeats no more here.
In embodiment as shown in Figure 1, the degree of depth > 2 μ m of described groove, preferably > 3 μ m.In this case, because the degree of depth of groove is deep, therefore can increase grid-drain capacitance C
gDthereby, can reduce grid voltage V
gSamplitude.
Fig. 2 schematically shows according to the sectional view of the super junction device 200 of another embodiment of the present utility model.
Be similar to the super junction device 100 shown in Fig. 1, super junction device 200 comprises N-shaped drift region 230.N+ impure drain region 220 is formed on below N-shaped drift region 230 by for example epitaxial growth.The source region 260 of p-type tagma 250 and n+ doping is formed on N-shaped drift region 230 successively.
In this embodiment, drift region 230 comprises n district and the p district of multiple Width alternative arrangements along drift region, and wherein at least p district contacts p+ tagma 250, and these n districts and p district are as electric charge compensating region.In this case, between the n district in p+ tagma 250 source region 260 and drift region 230.Preferably, each in these n districts and p district is cylindricality, as shown in Figure 2.
In addition, super junction device 200 also comprises trench gate structure, and wherein groove is configured to extend into the n district of drift region 230 from the upper surface in tagma 250, and the basal surface of this groove is arranged in the n district of drift region 230.Gate electrode 270 is formed in groove, and has been full of oxide layer 280 in space between gate electrode 270 and groove.In other words, oxide layer 280 is surrounded gate electrode 270, thereby can be by gate electrode 270 and trench wall isolation.In one embodiment, this super junction device 200 also comprise be formed on source region 260 in case with the source electrode 284 of its formation ohmic contact and be formed on drain region 220 below in case with the drain electrode 210 of its formation ohmic contact.In this case, oxide layer 290 is formed on the top of gate electrode 270, to source electrode 284 and gate electrode 270 are insulated, as shown in Figure 2.In one embodiment, gate electrode 270 and source electrode 284 all can be made up of polysilicon or metal.
The formation of said structure can utilize semiconductor fabrication process well known to those skilled in the art to complete, and repeats no more here.
In embodiment as shown in Figure 2, the thickness of the oxide layer between described gate electrode 270 and channel bottom is in the scope of 150 nm-600 nm, preferably in the scope of 300 nm-600 nm.In this case, because the oxide layer below gate electrode in groove is thicker, therefore can reduce grid-drain capacitance C
gDthereby, can reduce the also switching speed of the super junction device of raising of drain feedback.In addition or alternatively, by selecting thicker grid oxic horizon 280 can realize capacitor C on a sidewall of groove
gDfurther reduce (as shown in FIG.).
Preferably, the part between the sidewall of gate electrode 270 and the sidewall of groove of oxide layer 280 has the thickness that is less than 150 nm.
In the utility model, by implementing according to the super junction device of the embodiment shown in Fig. 1 and Fig. 2, can adjust according to demand the grid-drain capacitance C of (for example increase or reduce) super junction device
gD.If expect to increase grid-drain capacitance C
gD, can the degree of depth of groove be made deeplyer; And if expectation reduces grid-drain capacitance C
gD, can the thickness of the oxide layer below gate electrode in groove be made thicklyer.Expecting to reduce grid-drain capacitance C
gDsituation under, the degree of depth of groove can keep and the degree of depth identical in the embodiment of Fig. 1; Preferably, the degree of depth of groove can be reduced, to meet and to reduce grid-drain capacitance C better
gDdemand.
Fig. 3 schematically shows according to the sectional view of the semiconductor structure that comprises super junction device 3000 of an embodiment of the present utility model.
Note, super junction device 300 employings in Fig. 3 and Fig. 1 or with the super junction device of the embodiment shown in Fig. 2 identical structure, therefore, in order to give prominence to better crucial part of the present utility model, will be omitted about the description of super junction device 300.But, read for the ease of those skilled in the art, still mark with similar Reference numeral with element corresponding in Fig. 1 or Fig. 2.
In Fig. 3, only show a super junction device 300 as an example; In fact, semiconductor structure 3000 can comprise multiple super junction devices or super statement of account unit 300, the active cell district of the plurality of super junction device or super knot cell formation semiconductor structure 3000.
As shown in Figure 3, semiconductor structure 3000 also comprises the semiconductor region around multiple super junction devices, is formed with oxide layer 380 on this semiconductor region.Grid slideway 370 is embedded in oxide layer 380, wherein in an end of grid slideway 370, at least a portion of grid slideway 370 is arranged in the groove that is formed on described semiconductor region, and this at least a portion of grid slideway 370 oxidized layer in this groove surrounds, thereby by this at least a portion of grid slideway 370 and trench wall insulation.
In one embodiment, semiconductor structure 3000 also comprises the gate pads 386 being formed on above oxide layer 380, and described gate pads 386 is by least one through hole and described grid slideway 370 electric connections.
Further, semiconductor structure 3000 also comprises the field plate 374 being embedded in oxide layer 380.In one embodiment, described field plate 374 and super junction device 300(or semiconductor structure 3000) drain electrode 388 short circuits to form the termination mechanism of semiconductor structure 3000.
In one embodiment, be similar in drift region, semiconductor region also comprises n district and the p district of multiple Width alternative arrangements along semiconductor region.Preferably, each in these n districts and p district is cylindricality, as shown in Figure 3.In one embodiment, be arranged in semiconductor region and the p district below grid slideway 370 and can be connected to by another p district the source electrode of super junction device 300.Described p district and n district also can be omitted and exist only in described cellular zone in terminator.
In the embodiment shown in fig. 3, the thickness of the oxide layer 380 below field plate 374 is greater than the thickness of the oxide layer 380 below at least a portion of grid slideway 370.Preferably, the thickness of the oxide layer 380 below another end of grid slideway 370 is identical with the thickness of the oxide layer below field plate 374, makes to have oxide layer step or oxide layer slope in another end of grid slideway 370.Preferably, the thickness of the oxide layer below described at least a portion of grid slideway 370 is less than 150 nm.
In the utility model, by implementing according to the semiconductor structure shown in Fig. 3, below the grid slideway of this semiconductor structure, adopt thinner oxide layer (for example thickness is 150 nm or less) and below the field plate in grid potential, adopt thick oxide layer, can increase grid-drain capacitance C
gDthereby, can reduce grid voltage V
gSthe amplitude of spike.
In the description of carrying out about Fig. 1-3 in the above, in order to give prominence to better the utility model, therefore only improvement structure of the present utility model be have been described in detail, well known to a person skilled in the art some semiconductor device structures and only summarize or even omitted.In addition, the formation of the semiconductor device structure in the utility model all can adopt semiconductor fabrication process well known to those skilled in the art to complete, and repeats no more here.
Although describe the utility model and advantage thereof in detail by exemplary embodiment above, but those skilled in the art are to be understood that, in the case of not departing from the spirit and scope of the present utility model that are defined by the following claims, can carry out multiple replacement and modification to the utility model.
Claims (13)
1. a super junction device, comprising:
There is the semiconductor body on the first and second surfaces;
Be arranged in the source region of the first conduction type of described semiconductor body at first surface place;
Be arranged in the drain region of the first conduction type of described semiconductor body at second surface place;
The tagma of the second conduction type in the described semiconductor body between described source region and described drain region;
Drift region in described semiconductor body between described tagma and described drain region, described drift region is to be formed by the firstth district of the first conduction type and the Second Region of the second conduction type of the direction alternative arrangement along being parallel to described first surface; With
Trench gate structure, it extends to described firstth district of described drift region from described first surface, wherein said trench gate structure is included in the groove in described semiconductor body, the gate electrode in described groove and between described semiconductor body and described gate electrode and around the first grid oxide layer of described gate electrode
It is characterized in that,
The thickness of the part between the bottom of described gate electrode and the bottom of described groove of described first grid oxide layer is in the scope of 150 nm-600 nm.
2. super junction device according to claim 1, is characterized in that, the degree of depth > 2 μ m of described groove.
3. super junction device according to claim 2, is characterized in that, the degree of depth > 3 μ m of described groove.
4. super junction device according to claim 1, is characterized in that, the thickness of the part between the bottom of described gate electrode and the bottom of described groove of described first grid oxide layer is in the scope of 300 nm-600 nm.
5. super junction device according to claim 1, is characterized in that, any part of the described first grid oxide layer between the sidewall of described gate electrode and the sidewall of described groove is all not more than 150 nm in cellular zone.
6. a semiconductor structure, comprising:
The active cell district being formed by multiple super junction devices according to claim 1;
Surround the semiconductor region in described active cell district and be formed on the second grid oxide layer on described semiconductor region;
Embed the grid slideway in described second grid oxide layer; With
Embed the field plate in described second grid oxide layer,
It is characterized in that,
The thickness of the second grid oxide layer below described field plate is greater than the thickness of the second grid oxide layer below at least a portion of described grid slideway.
7. semiconductor structure according to claim 6, it is characterized in that, in an end of described grid slideway, at least a portion of described grid slideway is arranged in the groove of described semiconductor region, and is surrounded by described second grid oxide layer in described groove.
8. semiconductor structure according to claim 7, is characterized in that, described semiconductor structure also comprises the gate pads being positioned in described second grid oxide layer, and described gate pads is by least one through hole and described grid slideway electric connection.
9. semiconductor structure according to claim 8, is characterized in that, the drain electrode short circuit of described field plate and described super junction device is to form the termination mechanism of described semiconductor structure.
10. semiconductor structure according to claim 9, is characterized in that, described semiconductor region by the firstth district of the first conduction type and the Second Region of the second conduction type along the Width alternative arrangement of described semiconductor region and form.
11. semiconductor structures according to claim 7, is characterized in that, the thickness of the second grid oxide layer below another end of described grid slideway is identical with the thickness of the second grid oxide layer below described field plate.
12. semiconductor structures according to claim 10, is characterized in that, are arranged in the source electrode that described semiconductor region and the described Second Region below described grid slideway are connected to the tagma of described super junction device or are connected to described super junction device by contact.
13. semiconductor structures according to claim 6, is characterized in that, the thickness of the second grid oxide layer below described at least a portion of described grid slideway is less than 150 nm.
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| CN201320674971.5U CN203659870U (en) | 2013-10-30 | 2013-10-30 | Super junction device and semiconductor structure comprising same |
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| CN201320674971.5U CN203659870U (en) | 2013-10-30 | 2013-10-30 | Super junction device and semiconductor structure comprising same |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018121600A1 (en) * | 2016-12-28 | 2018-07-05 | 苏州东微半导体有限公司 | Super junction power transistor and preparation method thereof |
| US10164086B2 (en) | 2015-09-23 | 2018-12-25 | Infineon Technologies Austria Ag | Vertical field effect transistor device having alternating drift regions and compensation regions |
| CN110416309A (en) * | 2019-08-29 | 2019-11-05 | 无锡新洁能股份有限公司 | A kind of Superjunction power semiconductor device and preparation method thereof |
| CN115224024A (en) * | 2022-09-15 | 2022-10-21 | 北京芯可鉴科技有限公司 | Super junction device of integrated gate-drain capacitor and manufacturing method |
-
2013
- 2013-10-30 CN CN201320674971.5U patent/CN203659870U/en not_active Expired - Lifetime
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10164086B2 (en) | 2015-09-23 | 2018-12-25 | Infineon Technologies Austria Ag | Vertical field effect transistor device having alternating drift regions and compensation regions |
| US10608103B2 (en) | 2015-09-23 | 2020-03-31 | Infineon Technologies Austria Ag | Method for forming vertical field effect transistor devices having alternating drift regions and compensation regions |
| WO2018121600A1 (en) * | 2016-12-28 | 2018-07-05 | 苏州东微半导体有限公司 | Super junction power transistor and preparation method thereof |
| CN110416309A (en) * | 2019-08-29 | 2019-11-05 | 无锡新洁能股份有限公司 | A kind of Superjunction power semiconductor device and preparation method thereof |
| CN110416309B (en) * | 2019-08-29 | 2024-04-09 | 无锡新洁能股份有限公司 | Super junction power semiconductor device and manufacturing method thereof |
| CN115224024A (en) * | 2022-09-15 | 2022-10-21 | 北京芯可鉴科技有限公司 | Super junction device of integrated gate-drain capacitor and manufacturing method |
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