CN104681438B - A kind of forming method of semiconductor devices - Google Patents
A kind of forming method of semiconductor devices Download PDFInfo
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- CN104681438B CN104681438B CN201310613731.9A CN201310613731A CN104681438B CN 104681438 B CN104681438 B CN 104681438B CN 201310613731 A CN201310613731 A CN 201310613731A CN 104681438 B CN104681438 B CN 104681438B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 238000000034 method Methods 0.000 title claims abstract description 31
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 118
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 118
- 239000010703 silicon Substances 0.000 claims abstract description 118
- 239000000758 substrate Substances 0.000 claims abstract description 68
- 238000000407 epitaxy Methods 0.000 claims abstract description 34
- 239000002184 metal Substances 0.000 claims abstract description 19
- 229910052751 metal Inorganic materials 0.000 claims abstract description 19
- 238000005224 laser annealing Methods 0.000 claims abstract description 10
- 238000002347 injection Methods 0.000 claims description 12
- 239000007924 injection Substances 0.000 claims description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 238000002513 implantation Methods 0.000 claims description 10
- 238000009792 diffusion process Methods 0.000 claims description 9
- 238000011049 filling Methods 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- 239000011248 coating agent Substances 0.000 claims description 6
- 238000000576 coating method Methods 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 5
- 239000010931 gold Substances 0.000 claims description 5
- 229910052737 gold Inorganic materials 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 229910052785 arsenic Inorganic materials 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 238000001704 evaporation Methods 0.000 claims description 3
- 230000008020 evaporation Effects 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 108090000723 Insulin-Like Growth Factor I Proteins 0.000 claims description 2
- 102000013275 Somatomedins Human genes 0.000 claims description 2
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- 229910052787 antimony Inorganic materials 0.000 claims description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 2
- 238000000926 separation method Methods 0.000 claims description 2
- 229910003978 SiClx Inorganic materials 0.000 claims 2
- DOTMOQHOJINYBL-UHFFFAOYSA-N molecular nitrogen;molecular oxygen Chemical compound N#N.O=O DOTMOQHOJINYBL-UHFFFAOYSA-N 0.000 claims 2
- 238000004519 manufacturing process Methods 0.000 abstract description 11
- 230000015556 catabolic process Effects 0.000 abstract description 7
- 238000010586 diagram Methods 0.000 description 11
- 238000002156 mixing Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000003701 mechanical milling Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
Abstract
The present invention discloses a kind of forming method of semiconductor devices, comprises the following steps：1）Deep trench is etched in bulk silicon substrate side；2）Channel bottom is injected and trap is pushed away；3）Silicon epitaxy layer is filled in trench interiors and is planarized；Then base, source region, grid, dielectric layer and front metal electrode are formed；4）Bulk silicon substrate opposite side is thinned, and opposite side progress ion implanting, laser annealing, back metal electrode are formed.The present invention makes the breakdown voltage of semiconductor devices, conducting resistance keep stable by the adjustment to silicon epitaxy doping concentration, gash depth and silicon wafer thickness.The inventive method can reduce the manufacturing cost of super-junction device, production efficiency be improved, while the conducting resistance of device can be reduced.
Description
Technical field
The invention belongs to semiconductor integrated circuit manufacture field, and in particular to semiconductor image sensor, more particularly to one
Plant full isolation back side illumination image sensor and its manufacture method.
Background technology
VDMOSFET（VerticalDouble-diffusedMOSFET, vertical double-diffused MOS transistor）It can use and subtract
The thickness of thin drain terminal drift region reduces conducting resistance, however, the thickness of drain terminal drift region, which is thinned, will reduce puncturing for device
Voltage, therefore in VDMOS, the breakdown voltage for improving device is conflict with the conducting resistance for reducing device.Super junction
MOSFET is using new structure of voltage-sustaining layer-using a series of p-type being alternately arranged and N-type semiconductor thin layer, in low voltage
P-type N-type region is exhausted under lower backward voltage, realizes that electric charge is mutually compensated for, so that p-type N-type region can be real under high-dopant concentration
Existing high breakdown voltage, so as to obtain low on-resistance and high-breakdown-voltage simultaneously, break traditions power MOSFET theoretical limits.
Super junction MOSFET difficult point is that device architecture forms difficulty, and the p-type and N-type semiconductor being mainly alternately arranged are thin
The formation of Rotating fields.General forming method is：In N-type silicon epitaxy layer（That is the first semiconductor layer 22 in Fig. 1）It is upper to form deep
Groove, then use P-type silicon epitaxial layer（That is the second semiconductor layer 23 in Fig. 1）Deep trench is filled, the structure of existing device is shown in Fig. 1.
Due to involving thick epitaxial growth, deep plough groove etched, trench fill etc., cost is higher.How growth cost always industry is reduced
The direction of boundary's research.
The content of the invention
The technical problem to be solved in the present invention is to provide a kind of forming method of semiconductor devices is proposed, production can be reduced
Cost, improves production efficiency.
In order to solve the above technical problems, the present invention provides a kind of forming method of semiconductor devices, comprise the following steps：
1）Deep trench is etched in bulk silicon substrate side；
2）Channel bottom is injected and trap is pushed away；
3）Silicon epitaxy layer is filled in trench interiors and is planarized；Then base, source region, grid, dielectric layer and front are formed
Metal electrode；
4）Bulk silicon substrate opposite side is thinned, and ion implanting, laser annealing, back-side gold are carried out to opposite side
Category electrode is formed.
It is used as preferred technical scheme, step 1）In, the zanjon groove depth is 10-80 μm, and width is 1-10 μm, zanjon
Separation is 2-15 μm, and the doping concentration for the bulk silicon substrate surveyed in advance so that the depth of deep trench is served as a contrast with semiconductor silicon
The doping concentration at bottom is into positive corresponding relation.
It is used as preferred technical scheme, step 1）In, the bulk silicon substrate is N-type or p-type, and doping concentration is
1E13-1E17cm-3。
It is used as preferred technical scheme, step 1）In, increase following steps before the etching deep trench：In semiconductor silicon
Grown dielectric layer, the dielectric layer is at least one of silica, silicon nitride, silicon oxynitride, and thickness is 0.1 μm of -2 μ
m。
It is used as preferred technical scheme, step 2）In, the doping class of the injection carrier type and bulk silicon substrate
Type is identical, and implantation dosage is 1E11-1E14atom/cm2, Implantation Energy is 10-100Kev.
It is used as preferred technical scheme, step 2）In, increase following steps before injection：First at zanjon groove sidewall and bottom
Portion grows a layer dielectric, and the deielectric-coating is at least one of silica, silicon nitride, silicon oxynitride, then is carved with anisotropic
Etching method removes the deielectric-coating of zanjon trench bottom.
It is used as preferred technical scheme, step 2）In, the trap that pushes away is specially：The ion for being injected into channel bottom is carried out
High temperature diffusion, makes it be diffused into below channel bottom 5-40 μm, and injection diffusion layer is between channel bottom formation one is continuous not
Disconnected injection doped layer.
It is used as preferred technical scheme, step 3）In, it is described to be carried out in two steps in trench interiors filling silicon epitaxy layer：First
Step, has the silicon epitaxy of identical doping type in deep trench underfill and bulk silicon substrate；Second step, continues in groove
The filling silicon epitaxy opposite with bulk silicon substrate doping type, until groove is filled up completely with, also, the silicon substrate surveyed in advance
Doping concentration so that second step inserts the doping concentration of the silicon epitaxy layer of groove and the doping concentration of bulk silicon substrate into just right
It should be related to.
It is used as preferred technical scheme, step 4）In, the thickness after the bulk silicon substrate is thinned is 30-200 μm, and
The doping concentration for the silicon substrate surveyed in advance, makes to be thinned the rear thickness of silicon chip and the doping concentration of silicon substrate into positive corresponding relation.
It is used as preferred technical scheme, step 4）In, the species of the ion implanting is at least one in B, P, As, Sb
Kind, Implantation Energy is 10-1000Kev, and implantation dosage is 1E13-1E17atoms/cm2。
It is used as preferred technical scheme, step 4）In, the energy of the laser annealing is 1.0-3.0J/cm2, spot length
For 1-3mm, spot width is 0.3-1.5mm；Floor height doping implanted layer is formed after laser annealing at the bulk silicon substrate back side,
With follow-up metal electrode formation Ohmic contact.
It is used as preferred technical scheme, step 4）In, the method that the back metal electrode is formed by evaporation or sputtering
Metal level is formed at the bulk silicon substrate back side as first electrode, the species of metal is at least one in Ti, Ni, Ag, Au, Al
Kind, thickness is 0.1-2 μm.
When so-called positive corresponding relation refers to variables A increase, variable B also increases；When negative corresponding relation refers to variables A increase,
Variable B reduces.
The super-junction device of method is manufactured as described above, when the doping concentration Cn of silicon substrate is fluctuated within the specific limits, device
Breakdown voltage BV and the conducting resistance Ron doping concentration Cp that pass through silicon epitaxy（Make the carrier amount phase of super junction P posts and N posts
Deng）, gash depth d and be thinned after silicon wafer thickness t adjustment and keep constant because：
BV∞d/Cn Ron∞t/Cn
Carrier is injected in channel bottom in addition and promoted, reduce the conducting resistance Ron of device.Inject and push away trap
Depth 5-40 microns of depth below channel bottom.
Compared to the prior art, the invention has the advantages that：The present invention is by silicon epitaxy doping concentration, groove
The adjustment of depth and silicon wafer thickness, makes the breakdown voltage of semiconductor devices, conducting resistance keep stable.The inventive method can drop
The manufacturing cost of low super-junction device, improves production efficiency, while the conducting resistance Ron of device can be reduced.
Brief description of the drawings
Fig. 1 is the structural representation of existing device；
Fig. 2-Figure 12 is the manufacturing process flow schematic diagram of the embodiment of the present invention；Wherein, Fig. 2 is the step of the embodiment of the present invention
Rapid 1）After the completion of section structure schematic diagram；Fig. 3 is the step 2 of the embodiment of the present invention）After the completion of section structure schematic diagram；Figure
4 be the step 3 of the embodiment of the present invention）After the completion of section structure schematic diagram；Fig. 5 is the step 4 of the embodiment of the present invention）After the completion of
Section structure schematic diagram；Fig. 6 is the step 5 of the embodiment of the present invention）The silicon epitaxy first step filling after the completion of section structure
Schematic diagram；Fig. 7 is the step 5 of the embodiment of the present invention）Section structure schematic diagram after the completion of the filling of silicon epitaxy second step；Fig. 8 is
The step 6 of the embodiment of the present invention）After the completion of section structure schematic diagram；Fig. 9 is the step 7 of the embodiment of the present invention）After the completion of
Section structure schematic diagram；Figure 10 is the step 8 of the embodiment of the present invention）After the completion of section structure schematic diagram；Figure 11 is the present invention
The step 9 of embodiment）After the completion of section structure schematic diagram；Figure 12 is the step 10 of the embodiment of the present invention）After the completion of section
Structural representation；
Description of reference numerals is as follows：
1 is bulk silicon substrate, and 2 be dielectric layer, and 3 be the second silicon epitaxy layer, and 4 be the first silicon epitaxy layer, and 5 be base region, 6
It is gate dielectric layer for source area, 7,8 be grid, and 9 be before-metal medium layer, and 10 be second electrode, and 11 be front injection diffusion
Layer, 12 be that diffusion layer is injected at the back side, and 13 be first electrode.
21 be bulk silicon substrate, and 22 be the first semiconductor layer, and 23 be the second semiconductor layer, and 24 be base, and 25 be source region,
26 be gate dielectric layer, and 27 be grid, and 28 be before-metal medium layer, and 29 be second electrode, and 30 be first electrode.
Embodiment
The present invention is further detailed explanation with reference to the accompanying drawings and examples.
Embodiment：
As shown in Fig. 2-Figure 12, a kind of forming method of semiconductor devices of the invention specifically includes following steps：
1）The somatomedin layer 2 on bulk silicon substrate 1, bulk silicon substrate 1 can be N-type or p-type, and doping concentration is
1E13-1E17cm-3;Dielectric layer 2 is at least one of silica, silicon nitride, silicon oxynitride, and thickness is 0.1 μm -2 μm（See figure
2）.
2）Deep trench is etched on bulk silicon substrate 1, zanjon well width is 1-10 μm, and depth is between 10-80 μm, groove
Away from for 2-15 microns（See Fig. 3）；And the doping concentration for the bulk silicon substrate 1 surveyed in advance so that the depth of deep trench is with partly leading
The doping concentration of body silicon substrate 1 presets the breakdown voltage of device into positive corresponding relation, when mixing for bulk silicon substrate 1
When miscellaneous concentration is higher, the depth of appropriate increase groove, when the doping concentration of bulk silicon substrate 1 is relatively low, then appropriate reduction ditch
The depth of groove so that when the doping concentration of bulk silicon substrate 1 is fluctuated within the specific limits（+/- the 50% of reservation value）, device
Breakdown voltage keeps constant.
3）Ion implanting is carried out in channel bottom, the type for injecting ion is identical with the doping type of bulk silicon substrate 1,
If bulk silicon substrate 1 is doped to N-type, N-type is injected to；If bulk silicon substrate 1 is p-type, implanting p-type；Injection
Dosage is 1E11-1E14atom/cm2, Implantation Energy is 10-100Kev；To prevent trenched side-wall to be injected into ion, it can use
The method that trenched side-wall is protected with deielectric-coating, specific practice is：First in trenched side-wall and the layer dielectric of bottom grown one（Oxidation
At least one of silicon, silicon nitride, silicon oxynitride）, then with anisotropic etching method the deielectric-coating of channel bottom is removed, so
After carry out ion implanting（See Fig. 4）.
4）High temperature diffusion is carried out to the ion for being injected into channel bottom, it is diffused into below channel bottom 5-40 μm, and
Diffusion layer is injected in channel bottom one continuous continual injection doped layer of formation, and diffusion layer 11 is injected as front（See figure
5）.
5）Groove is filled with silicon epitaxy process.Silicon epitaxy filling is carried out in two steps：The first step, in channel bottom filling and half
Conductor silicon substrate 1 has the silicon epitaxy of identical doping type, i.e. the first silicon epitaxy layer 4, if bulk silicon substrate 1 is doped to N
Type, then the first silicon epitaxy layer 4 is N-type, sees Fig. 6；Second step, the second step filling of silicon epitaxy, its doping type and semiconductor silicon
Substrate 1 is on the contrary, form the second silicon epitaxy layer 3, if bulk silicon substrate 1 is doped to N-type, the second silicon epitaxy layer 3 is P
Type；If bulk silicon substrate 1 is p-type, the second silicon epitaxy layer 3 is N-type, sees Fig. 7.Outside first silicon epitaxy layer 4 and the second silicon
The doping type for prolonging layer 3 is opposite.The doping concentration for the bulk silicon substrate 1 surveyed in advance so that second step inserts the second of groove
The doping concentration of silicon epitaxy layer 3 and the doping concentration of bulk silicon substrate 1 mixing into positive corresponding relation, i.e. bulk silicon substrate 1
When miscellaneous concentration is high, the doping concentration of the second silicon epitaxy layer 3 is also high；When the doping concentration of bulk silicon substrate 1 is low, the second silicon epitaxy
The doping concentration of layer 3 is also low, and final purpose is to make the semiconductor between the carrier total amount of silicon epitaxy in single groove and groove
The carrier total amount of silicon substrate 1 is equal（See Fig. 7）.
6）With chemical mechanical milling tech to being planarized at the top of groove（See Fig. 8）；
7）Next with routine MOSFET techniques formation base region 5, before source area 6, gate dielectric layer 7, grid 9, metal
Dielectric layer 9, second electrode 10 etc.（See Fig. 9）.
8）Bulk silicon substrate 1 is thinned.Thickness after bulk silicon substrate 1 is thinned is 30-200 μm, and in advance
The doping concentration of the silicon substrate of survey, makes to be thinned the rear thickness of silicon chip and the doping concentration of silicon substrate into positive corresponding relation.It is i.e. advance
If the conducting resistance of low device, when the doping concentration of silicon substrate is high, the thickness of silicon substrate after appropriate increase is thinned；Work as silicon substrate
Doping concentration it is low when, the thickness of silicon substrate after appropriate reduction is thinned so that the doping concentration of silicon substrate ripple within the specific limits
When dynamic（+/- the 50% of reservation value）, the conducting resistance of device keeps constant（See Figure 10）.
9）Backside particulate injects and laser annealing.The species of ion implanting is at least one of B, P, As, Sb, injects energy
Measure as 10-1000Kev, implantation dosage is 1E13-1E17atoms/cm2.The energy of laser annealing is 1.0-3.0J/cm2, hot spot
Length is 1-3mm, and spot width is 0.3-1.5mm.After injection and laser annealing a floor height is formed at the back side of bulk silicon substrate 1
Adulterated implanted layer, and diffusion layer 12 is injected as the back side, can contact electricity with follow-up metal electrode formation Ohmic contact to reduce
Resistance.The characteristics of laser annealing is that thermal range is controlled, i.e., only silicon substrate back temperature is high, and positive temperature is unaffected, no
Influence whether the device at the back side（See Figure 11）.
10）Back metal electrode is formed.Metal level is formed with the method for evaporation or sputtering at the back side of bulk silicon substrate 1 to make
For first electrode 13.The species of metal is at least one of Ti, Ni, Ag, Au, Al, and thickness is 0.1-2 μm（See Figure 12）.
The present invention makes hitting for semiconductor devices by the adjustment to silicon epitaxy doping concentration, gash depth and silicon wafer thickness
Wear voltage, conducting resistance and keep stable.The inventive method can reduce the manufacturing cost of super-junction device, improve production efficiency,
The conducting resistance of device can be reduced simultaneously.
Claims (10)
1. a kind of forming method of semiconductor devices, it is characterised in that：Comprise the following steps：
1）Deep trench is etched in bulk silicon substrate side；
2）Channel bottom is injected and trap is pushed away；
3）Silicon epitaxy layer is filled in trench interiors and is planarized；It is described to be carried out in two steps in trench interiors filling silicon epitaxy layer：The
One step, has the silicon epitaxy of identical doping type in deep trench underfill and bulk silicon substrate；Second step, continues in groove
The interior filling silicon epitaxy opposite with bulk silicon substrate doping type, until being filled up completely with groove, also, the silicon substrate surveyed in advance
Doping concentration so that second step inserts the doping concentration of the silicon epitaxy layer of groove and the doping concentration of bulk silicon substrate into just
Corresponding relation；Then base, source region, grid, dielectric layer and front metal electrode are formed；
4）Bulk silicon substrate opposite side is thinned, the thickness after the bulk silicon substrate is thinned is 30-200 μm, and
The doping concentration for the silicon substrate surveyed in advance, makes to be thinned the rear thickness of silicon chip and the doping concentration of silicon substrate into positive corresponding relation；And
Opposite side progress ion implanting, laser annealing, back metal electrode are formed.
2. a kind of forming method of semiconductor devices as claimed in claim 1, it is characterized in that, step 1）In, the deep trench
Depth is 10-80 μm, and width is 1-10 μm, and zanjon separation is 2-15 μm, and the doping for the bulk silicon substrate surveyed in advance is dense
Degree so that the depth of deep trench and the doping concentration of bulk silicon substrate are into positive corresponding relation.
3. a kind of forming method of semiconductor devices as claimed in claim 1, it is characterized in that, step 1）In, the semiconductor
Silicon substrate is N-type or p-type, and doping concentration is 1E13-1E17cm-3。
4. a kind of forming method of semiconductor devices as claimed in claim 1, it is characterized in that, step 1）In, the etching is deep
Increase following steps before groove：The somatomedin layer on bulk silicon substrate, the dielectric layer is silica, silicon nitride, nitrogen oxygen
At least one of SiClx, thickness is 0.1 μm -2 μm.
5. a kind of forming method of semiconductor devices as claimed in claim 1, it is characterized in that, step 2）In, the injection is carried
Flow subtype identical with the doping type of bulk silicon substrate, implantation dosage is 1E11-1E14 atom/cm2, Implantation Energy is
10-100Kev。
6. a kind of forming method of semiconductor devices as claimed in claim 1, it is characterized in that, step 2）In, before injection
Increase following steps：First in zanjon groove sidewall and the layer dielectric of bottom grown one, the deielectric-coating is silica, silicon nitride, nitrogen oxygen
At least one of SiClx, then the deielectric-coating of zanjon trench bottom is removed with anisotropic etching method.
7. a kind of forming method of semiconductor devices as claimed in claim 1, it is characterized in that, step 2）In, it is described to push away trap tool
Body is：High temperature diffusion is carried out to the ion for being injected into channel bottom, it is diffused into below channel bottom 5-40 μm, and injection is expanded
Layer is dissipated in channel bottom one continuous continual injection doped layer of formation.
8. a kind of forming method of semiconductor devices as claimed in claim 1, it is characterized in that, step 4）In, the ion note
The species entered is at least one of B, P, As, Sb, and Implantation Energy is 10-1000Kev, and implantation dosage is 1E13-
1E17atoms/cm2。
9. a kind of forming method of semiconductor devices as claimed in claim 1, it is characterized in that, step 4）In, the laser is moved back
The energy of fire is 1.0-3.0J/cm2, spot length is 1-3mm, and spot width is 0.3-1.5mm；Partly led after laser annealing
The body silicon substrate back side forms floor height doping implanted layer, with follow-up metal electrode formation Ohmic contact.
10. a kind of forming method of semiconductor devices as claimed in claim 1, it is characterized in that, step 4）In, the back-side gold
Category electrode is formed by evaporation or the method for sputtering forms metal level at the bulk silicon substrate back side as first electrode, metal
Species is at least one of Ti, Ni, Ag, Au, Al, and thickness is 0.1-2 μm.
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| CN105118824A (en) * | 2015-07-21 | 2015-12-02 | 上海华虹宏力半导体制造有限公司 | Manufacturing method of photoetching alignment mark applied to double-layer epitaxial process |
| CN108550529B (en) * | 2018-04-28 | 2021-10-15 | 江苏新顺微电子股份有限公司 | Manufacturing method of high-voltage VDMOS device |
| CN109659236B (en) * | 2018-12-17 | 2022-08-09 | 吉林华微电子股份有限公司 | Process method for reducing VDMOS recovery time and VDMOS semiconductor device thereof |
| CN109830434B (en) * | 2019-01-30 | 2022-12-23 | 上海朕芯微电子科技有限公司 | Wafer back thinning metallization method |
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| CN104377238B (en) * | 2010-03-05 | 2017-04-12 | 万国半导体股份有限公司 | Configurations and methods for manufacturing devices with trench-oxide-nano-tube super-junctions |
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