CN102005452A - Integrated schottky diode in high voltage semiconductor device - Google Patents
Integrated schottky diode in high voltage semiconductor device Download PDFInfo
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Abstract
The invention provides a method for preparing a semiconductor power device in a semiconductor substrate consisting of an active element region and a termination region. The method comprises the following steps: growing a field oxide layer and forming a pattern in the termination region and the active element region on the top surface of the semiconductor substrate; arranging a polycrystalline silicon layer on the top surface of the semiconductor substrate away from the field oxide layer by a section of gap region, and forming a pattern; forming a body doping region in the semiconductor substrate by blank body doping implantation, the body doping region being substantially aligned with the gap region, and then diffusing the body doping region into the body region in the semiconductor substrate; implanting a high-concentration body doped region surrounding the body region and having a higher doping concentration than the body region; and implanting a source region having a conductivity type opposite to that of the body region by using a source mask, the source region being surrounded in the body region and surrounded by the body doping region having a high concentration.
Description
Technical field
The present invention relates generally to the structure and the preparation method of semiconductor power device.Or rather, the invention relates to the device architecture and the preparation method of the semiconductor power device of integrated schottky diode, need not extra mask,, reduce power loss so that shorten the shut-in time.
Background technology
Press for by as internal body diodes, integrated schottky diode is realized semiconductor power device.Or rather, shown in Figure 1A, because the embedded body diode that P+, P-and N-epitaxial loayer constitute, make HV MOSFET have negative drain electrode-to the P-i-N diode of-source voltage Vds＜0 as one.From this tagma of P-, high level is injected into the N-epitaxial region, causes very big opening time and loss.In addition, the change of the electric current of two-forty, promptly very big di/dt can cause voltage glitch, reduces " soft coefficient " S.But, in order to improve the performance of HV-DMOS, must reduce opening time and loss, that is to say, reduce QRR (Qrr), recovery time (Trr), and improve soft coefficient S.When HV MOSFET and inner Schottky diode integrate,, can improve the performance of HV MOSFET by solving above-mentioned technology limitation.
Except the above-mentioned requirements to the semiconductor power device that has integrated schottky diode, semiconductor power device also is widely used in power supply and motor control.Usually by the bridge-type topologies shown in Figure 1B, form semiconductor power device.For this application type, as a free wheeling diode, be very favorable with internal body diodes.If high-voltage MOSFET, super-junction semiconductor power device and IGBT device are used for power supply and motor control application, these devices usually can be subjected to the restriction of high Qrr and power loss.Schottky diode as internal body diodes, when being integrated into semiconductor power device, just can be solved these technical barriers.But for Schottky diode is integrated as an internal body diodes of the power device in the zone, the structure and the method for traditional preparation semiconductor power device will utilize an extra mask to stop this zone usually.This extra mask can produce adverse influence to production cost.
For these reasons, press for the structure and the preparation method that improve with as the integrated semiconductor power device of the Schottky diode of internal body diodes, so that solve an above-mentioned technology limitation and a difficult problem.
Summary of the invention
Therefore one aspect of the present invention is exactly to propose a kind of extra mask that do not need, with integrated novel preparation method and the device architecture of semiconductor power device of Schottky diode.
Or rather, one aspect of the present invention is to propose preparation structure and method a kind of and the semiconductor power device modified form that Schottky diode is integrated, does not need extra mask, and significantly reduces Qrr, Trr, improves soft coefficient.
Another aspect of the present invention is to propose a kind of and integrated semiconductor power device modified form device architecture and the preparation method of Schottky diode, by show up distance between the diode of the edge that reduces planar gate, to constitute self-alignment this tagma, and the end face of covering source electrode and top, this tagma, schottky metal is as source electrode and emitter metal, directly integrated with Schottky diode, part as transistor unit, need not to increase component size, thereby reduce by 50% Qrr, 20% Trr, increase by about 33% soft coefficient S.
In brief, preferred embodiment of the present invention has proposed a kind of semiconductor power device that is arranged in the Semiconductor substrate.This semiconductor power device is made of active element zone and terminator.Semiconductor power device also comprises patterned field oxide, and it is arranged in the terminator, and in the active element zone away from the gap area place of the patterned polysilicon layer on the Semiconductor substrate end face.Semiconductor power device also comprises this tagma of the doping that is arranged in the Semiconductor substrate, Semiconductor substrate is from beginning abundant diffusion with zone below the end face that gap area is alignd, and extends to patterned polysilicon layer and the following zone of patterned field oxide.Semiconductor power device also comprises the impure source district that is enclosed in this tagma, and its conduction type is opposite with this tagma.Semiconductor power device also comprises the high concentration body-doped region that is enclosed in the source area, and its doping content is than the doping content height in this tagma around the source area.In another embodiment, semiconductor power device also comprises a patterned schottky metal layer, occupied before covering by the field oxide in the active element zone, subsequently from the zone that the end face of Semiconductor substrate is removed, wherein patterned schottky metal layer also part extends in the gap area, so that contact this tagma and source area, be the semiconductor power device in the active element zone, form and treat integrated Schottky diode.In another embodiment, semiconductor power device also comprises shallow body-doped region, is arranged near this tagma that is located immediately at the schottky metal layer below, and this tagma of the depth ratio of shallow body-doped region is much shallow.In another embodiment, Semiconductor substrate is to be made of a N-type epitaxial loayer, is used to carry the body-doped region of the P-type conduction type of the source area that surrounds N-type conduction type.In another embodiment, Semiconductor substrate is to be made of a P-type epitaxial loayer, is used to carry the body-doped region of the N-type conduction type of the source area that surrounds P-type conduction type.In another embodiment, semiconductor power device also comprises a N-channel mosfet power device that is positioned on the N-N-type semiconductor N substrate.In another embodiment, semiconductor power device also comprises a P-channel mosfet power device that is arranged on the P-N-type semiconductor N substrate.In another embodiment, semiconductor power device also comprises a kind of igbt (IGBT) power device.In another embodiment, semiconductor power device also comprises igbt (IGBT) power device that is arranged on the N-N-type semiconductor N substrate, comprise the P-type bottom layer that has N-type doped region, N-type doped region is arranged near the bottom surface of Semiconductor substrate, the integrated schottky diode in the corresponding active element district.In another embodiment, semiconductor power device also comprises a super-junction semiconductor power device that contains alternating N-type and P-type doping column, and Semiconductor substrate is positioned at body-doped region below.In another embodiment, semiconductor power device also comprises a super-junction semiconductor power device that is arranged in the N-N-type semiconductor N substrate, Semiconductor substrate comprises that the P-type column that is positioned at below, bulk doped district constitutes, and P-type doped region and N-type column are entrained between the P-type column.
The invention allows for a kind of method for preparing semiconductor power device in Semiconductor substrate, wherein Semiconductor substrate is made of active element district and terminator.This method comprises: A) in terminator on the Semiconductor substrate end face and the active element district, and the growth field oxide, and form pattern; B) on the end face of the Semiconductor substrate of leaving one section gap area of field oxide, deposit a polysilicon layer, and form pattern; And C) implants by the bulk doped of no mask, in Semiconductor substrate, form the bulk doped district, fully align, then the bulk doped district is diffused into this tagma in the Semiconductor substrate with slit region.In another embodiment, this method also comprises implants the high concentration bulk doped district that is enclosed in this tagma, its doping content is also higher than the doping content in this tagma, utilize source mask implant source polar region, the conduction type of source area is opposite with this tagma, source area is enclosed in this tagma, and is enclosed by the bulk doped district of high concentration and to gather around.In another embodiment, this method also is included in the semiconductor power device top, deposits an insulating barrier, and opens contact openings with the contacting metal mask, and remove field oxide; The deposition schottky metal layer is filled contact openings, to contact this tagma and source area, in the active element district, forms the integrated schottky diode of semiconductor power device.In another embodiment, this method also is included in the semiconductor power device top, deposits an insulating barrier, and opens contact openings with the contacting metal mask, and remove field oxide; Implant shallow body-doped region, be arranged near this tagma that is located immediately at below the Semiconductor substrate end face, the degree of depth of shallow body-doped region is significantly less than this tagma.In another embodiment, implant body-doped region and comprise that the N-type epitaxial loayer being arranged on the N-N-type semiconductor N substrate is implanted to the bulk doped district with P-type alloy, and implant the N-type source area that is enclosed in this tagma of P-type.In another embodiment, implant body-doped region and comprise that the P-type epitaxial loayer being arranged on the P-N-type semiconductor N substrate is implanted to the bulk doped district with N-type alloy, and implant the P-type source area that is enclosed in this tagma of N-type.In another embodiment, make semiconductor power device and also comprise, make the MOSFET power device.In another embodiment, make semiconductor power device and also comprise, make the IGBT power device.In another embodiment, making semiconductor power device also comprises, in N-N-type semiconductor N substrate, make the IGBT power device, near the bottom surface of Semiconductor substrate, implantation has the P-type bottom of N-type doped region, and described N-type doped region is corresponding to Schottky diode integrated in the active element district.In another embodiment, make semiconductor power device and also comprise,, make the super-junction semiconductor power device by forming alternating N-type and P-type doping column in the Semiconductor substrate below body-doped region.In another embodiment, make semiconductor power device and also comprise, by in N-N-type semiconductor N substrate, form the P-type column that is positioned at the below, described bulk doped district that forms with the doping of P-type alloy, N-type column is between P-type column.
Read the detailed description of following preferred embodiment, and with reference to after the various accompanying drawings, for a person skilled in the art, the advantage of these and other aspects of the present invention undoubtedly will be apparent.
Description of drawings
Figure 1A represents the not profile of traditional plane HV MOSFET device of integrated schottky diode.
Figure 1B represents the full bridge circuit structure used in a kind of power supply and the motor controller spare.
Fig. 2 represents the profile that has the HV MOSFET device of integrated schottky diode of the present invention.
Fig. 2-1 expression is of the present invention to have the profile of termination structure of high-voltage MOSFET (HV MOSFET) semiconductor power device of integrated schottky diode.
Fig. 3 A to 3F is a series of expressions profiles that have the HV MOSFET preparation of devices process of integrated schottky diode of the present invention.
Fig. 3 A-1 to 3F-1 is the corresponding profile in termination zone in a series of each preparation process of presentation graphs 3A to 3F.
Fig. 4 represents the profile that has igbt (IGBT) device of integrated schottky diode of the present invention.
Fig. 5 A and 5B represent the profile that has two super-junction semiconductor power devices of integrated schottky diode of the present invention.
Fig. 6 A to 6I is the profile of the preparation process of the super-junction semiconductor power device of a series of expressions shown in Fig. 5 A.
Fig. 6 D-1 represents to utilize annealing process, makes the zone diffusion of boron implant, constitutes a plurality of P-doping columns, and Fig. 6 D-2 is the part of Fig. 6 D-1, represents remaining technology.
Fig. 7 A to 7E is the profile of the preparation process of a series of expressions another kind of super-junction semiconductor power device of the present invention.
Fig. 8 represents the profile that has a kind of optional super-junction semiconductor power device of integrated schottky diode of the present invention.
Embodiment
Referring to Fig. 2, the profile of the active element 100 of high voltage metal-oxide semiconductor field effect pipe (HV MOSFET) semiconductor power device that of the present invention and Schottky diode is integrated.HV MOSFET device is positioned on the N+ silicon substrate 105, and epitaxial loayer 110 is formed on N+ substrate 105 tops.Planar gate 125 is formed on grid oxic horizon 120 tops.This tagma 130 of P-is formed in the epitaxial loayer of grid oxic horizon below 120, and grid oxic horizon 120 surrounds N+ source area 135.Metal oxide semiconductor field effect tube (MOSFET) device 100 also comprises a P+ doped region 140 in this tagma 130 of P-.Source metal 150 covers on the end face, directly contacts with this tagma 130 of source area 135 and P-.Drain metal 160 is formed on the back side of Semiconductor substrate 105 as a drain electrode, thereby constitutes the active element of vertical MOSFET power device.Because the characteristics of substrate 105 are exactly than epitaxial loayer 110 thick manyfolds, therefore should proportionally not draw by figure.MOSFET device and inner Schottky diode are integrated, utilize schottky metal 150 as source metal, near the schottky region this tagma 130 of end face, P+ district 140, this tagma 130 of P-and the P-of covering source area 135.In order to reduce leakage current, below the schottky metal 150 in schottky region, directly prepare a very shallow P implant layer 145.High-voltage MOSFET (HV MOSFET) semiconductor power device contains the active element 100 of a plurality of parallel connections, to improve existing handling property.High-voltage MOSFET (HV MOSFET) semiconductor power device also comprises the active element termination structure on every side of neighboring area, so that bear near the voltage the Waffer edge.The termination structure of high-voltage MOSFET (HV MOSFET) semiconductor power device of Fig. 2-1 expression integrated schottky diode of the present invention.This termination structure comprises a plurality of field plates 125 ', by metallic conductor 150 ', passes guard ring contact implant 140 ', is electrically connected on the floating guard ring 130 ', and extends to the field plate 115 ' of the horizontal boundary top of guard ring 130 '.
Fig. 3 A to 3F is the profile of the preparation process of a series of expressions high-voltage MOSFET (HV MOSFET) 100 as shown in Figure 2, and Fig. 3 A-1 to 3F-1 is illustrated in the corresponding profile in termination zone in each preparation process.In Fig. 3 A and 3A-1, N buffering doped substrate 105 is being carried the N-epitaxial loayer 110 that is grown in above it, and the thickness of N-epitaxial loayer 110 is about 50 to 75 millimeters.In Fig. 3 B and 3B-1, utilize first mask (not expressing among the figure), growth and etching field oxide so that form field oxide 115 in active area, form field oxide 115 ' in the terminator.In Fig. 3 C, the grid oxic horizon 120 of at first growing, polysilicon layer 125 of deposition above grid oxic horizon 120 utilizes second mask (clearly not expressing among the figure) then, in grid 125, forms the pattern of polysilicon layer.According to identical technology, in the terminator shown in Fig. 3 C-1, form thin oxide layer 120 ' and polysilicon structure 125 '.In Fig. 3 D, to carry out the P-bulk doped and implant, diffusion subsequently forms this tagma 130 of P-.Utilize the 3rd mask (not expressing among the figure), carry out the N+ source electrode and implant, form source area 135.Remove source electrode and implant after the mask, carry out P+ and implant,, form P+ body contact zone 140 so that below N+ source area 135, reach the next door.Utilize existing field oxide and grid polycrystalline silicon 125 as mask, carry out the P-body and implant doping and P+ implantation, therefore do not need extra mask.The dosage that N+ implants is more much bigger than P+ and the implantation of P-body, will play a leading role in the zone of implanting.In the terminator shown in Fig. 3 D-1, because the 3rd bury and stop source electrode to be implanted, therefore utilize existing field oxide and grid polycrystalline silicon 125 as mask, only carry out that the P-body is implanted and P+ implants, constitute floating guard ring 130 ' and guard ring joint 140 '.In Fig. 3 E, utilize low-temperature oxidation (LTO) deposition, form oxide layer 128, utilize the 4th mask (not expressing among the figure) then, pass oxide layer 128, open contact openings, and utilize shallow P-to implant, form shallow P-district 145.Although, for the zone is exposed in the formation of giving next step Schottky, in opening the process of contact hole, removed the field oxide 115 in the active area, but, as shown in the figure pass oxide layer 128 ' and thin oxide layer 120 ', when opening contact hole, but kept the field oxide 115 ' in the terminator of Fig. 3 E-1.In Fig. 3 F, utilize the 5th mask (not expressing among the figure), as an emission metal level, preparation metal layer at top 150 also forms pattern.Can select the 6th mask (not expressing among the figure) preparation passivation layer (not expressing among the figure) for use and form pattern, in the device top face, preparation polyimide layer (not expressing among the figure) also forms pattern with the 7th mask (not expressing among the figure).Shown in Fig. 3 F, carry out back metallization then, form drain electrode 160 at the back of substrate 105.In the terminator, metal level forms pattern in metallic conductor 150 ', so that polysilicon 125 ' is electrically connected to floating guard ring 130 ', thereby constitutes a plurality of field plates 125 '.The terminal of device shown in field plate 125 ' and floating guard ring 130 ' the pie graph 3F-1 is with the high pressure in the carrying fringe region.Described as above-mentioned technology, because first mask in active area, provides field oxide, implant for the forming process of Schottky stops body, and first mask is used to stop field plate structure in the terminator, therefore the forming process of Schottky does not need special mask.
Fig. 4 represents the profile of a kind of igbt of the present invention (IGBT) 200.IGBT 200 is formed in the Semiconductor substrate 205 (for example P type substrate 205) with first conduction type.The epitaxial loayer 210 of second conduction type (for example the N-epitaxial loayer 210) is positioned at P type substrate 205 tops.IGBT 200 is a kind of vertical IGBT devices, and collector electrode 260 is arranged on the bottom surface of substrate, and emitter 250 is arranged on the end face.Grid 225 is arranged on gate insulator 220 tops.N+ source area 235 is formed on emitter below 250, and emitter 250 is enclosed in this tagma 230 of P-, just near emitter N-district 235.When the added voltage of grid surpassed threshold voltage, inner PNP bipolar transistor was opened.Electric current passes this tagma 230 of P+ doped region 240 and P from the emitter region 235, to drain region (as the part of N-epitaxial loayer 110), to substrate 205, arrives collector electrode 260 then.By with schottky metal 250 as emitter metal, cover on the end face of these 230 tops, tagma of emitter region 235, P+ district 240 and P-, the IGBT device also integrates with inner Schottky diode.Schottky metal 250 is homepitaxy layer 210 directly contacts with emitter region 235.In order to reduce leakage current, below schottky metal 250, directly form an extremely shallow P implant layer 245.In a part of P+ substrate layer 205, form a N+ doped region 205-N.N+ doped region 205-N is connected to collector electrode 260 on the N-epitaxial loayer, and makes integrated Schottky diode be connected between emitter 250 and the collector electrode 260.
Except parent material is the P+ substrate 250 of carrying N-epitaxial loayer 210, rather than the N+ substrate 150 of carrying N-epitaxial loayer 110, and be before back metallization, carry out N+ and implant, to constitute outside the N+ doped region 205-N, other preparation process of IGBT device are shown in Fig. 3 A to 3F.Optional process can be never begins with the N-substrate of epitaxial loayer.Before the back metallization process shown in Fig. 3 F, and carry out carrying out the implantation (not expressing among the figure) that implant on the P+ surface and N+ is with mask overleaf after the grinding of back, to constitute N+ substrate zone 205-N.Because the of the present invention and integrated IGBT device 200 of Schottky diode also can contain just like the termination structure shown in Fig. 2-1, therefore, when forming integrated Schottky, do not need extra mask.
Fig. 5 A represents the profile that has the super-junction semiconductor power device 300 of integrated schottky diode of the present invention.Super junction device 200 is positioned on the N+ silicon substrate 305 that has epitaxial loayer 310, by outer layer growth and implantation process hereinafter described, forms P-doping vertical pillars 315 in epitaxial loayer 310.Planar gate 330 is formed on the grid oxic horizon 325.This tagma 335 of P-is formed in the epitaxial loayer, and the grid oxic horizon that surrounds N+ source area 340 is below 325.Extra P+ body contact zone 336 is formed within this tagma 335 of P-.This tagma 335 of P-is formed on P-doping column 315 tops, and the P+ district as in the P-doping column 315 is directly adjacent to source area 340.Cover the source metal 360 on the end face, directly contact with this tagma 335 of source area 340 and P-.Be formed on the back side of Semiconductor substrate 305 as the drain metal 370 of drain electrode, thereby constitute a vertical super junction power device.By with schottky metal 360 as source metal, cover on the end face of source area 340, P+ district 336 and Schottky contacts P-doped region 350 tops, inner Schottky diode and super junction device are integrated.Schottky metal 360 directly contacts with source area 340 with epitaxial loayer 310.In order to reduce leakage current, below the schottky metal between the grid 330 360, directly form an extremely shallow P implant layer 350.Because the of the present invention and integrated IGBT device 300 of Schottky diode also can contain just like the termination structure shown in Fig. 2-1, therefore, when forming integrated Schottky, do not need extra mask.
Fig. 5 B represents to have the profile of the another kind of super-junction semiconductor power device 300 ' that is similar to the design feature shown in Fig. 5 B.Unique difference is, P-doping column 315 ' extends downwards in epitaxial loayer 310, extend to place with a certain distance from the top, bottom of the epitaxial loayer 310 that has a common boundary with base substrate N+ layer 305 always, yet in the power device shown in Fig. 5 A 300, P-doping column 315 extends to the bottom of epitaxial loayer 310 always.Because the of the present invention and integrated IGBT device 300 ' of Schottky diode also can contain just like the termination structure shown in Fig. 2-1, therefore, when forming integrated Schottky, do not need extra mask.
In order to reduce the recovery electric charge (Qrr) shown in Fig. 5, Fig. 6 A to 6J is the profile of the preparation process of a kind of super-junction semiconductor power device that has an integrated Schottky diode of a series of expressions.In Fig. 6 A, preparation process is at first from first N-epitaxial loayer 310-1 that grow at N+ substrate 305.In Fig. 6 B, utilize mask (not expressing among the figure) preparation collimating marks, the pad oxide 308 of growing subsequently.Utilize mask 309 etching oxides then, and under 200Kev, carry out boron and implant, so that in first epitaxial loayer 310-1, form P-district 315-1.To implant the infringement that brings in order repairing, to remove after the mask 309, under 900 degrees centigrade, annealed 30 minutes.Remove oxide pad 308, second the epitaxial loayer 310-2 that grow subsequently repeats above-mentioned preparation process, forms a plurality of epitaxial loayer 310-1 to 310-K in the second epitaxial loayer 310-2.Shown in Fig. 6 C, repeat same preparation process, formed a plurality of epitaxial loayer 310-1 to 310-K in each epitaxial loayer, implant 315-1 to 315-K.In Fig. 6 D, under 1150 degrees centigrade, to anneal 400-600 minute, the diffused with boron implantation region constitutes a plurality of P-doping columns 315.
In Fig. 6 D-1, under 1150 degrees centigrade, to anneal 400-600 minute, the diffused with boron implantation region constitutes a plurality of P-doping columns 315.Fig. 6 D-2 is the sub-fraction of Fig. 6 D-1 schematic diagram, represents all the other steps of this preparation process.In order to simplify, in these steps, a plurality of N-epitaxial loayer 310-1 to 310-K are expressed as a single continuous N-epitaxial loayer 310.
In Fig. 6 E, utilize first mask (not expressing among the figure), growth and etching field oxide 320.In Fig. 6 F, growth grid oxic horizon 325, polysilicon layer 330 of deposition above grid oxic horizon 325 and field oxide 320 utilizes second mask (clearly not expressing among the figure) then subsequently, polysilicon layer is formed the pattern of grid 330.In Fig. 6 G, carry out the P doping and implant, form this tagma 336 of P+ and this tagma 335 of P-.Utilize source mask as the 3rd mask, carry out the N+ source electrode and implant, form source area 340.In Fig. 6 H, carry out BPSG insulation deposition, utilize the 4th mask (not expressing among the figure) subsequently, carry out the contact openings process, formation has the insulating barrier 345 of contact openings, carries out Schottky subsequently and implants, and forms P-doping Schottky contact region 350 below the contact openings between the grid.In Fig. 6 I, form schottky metal layer 350 as source metal, and utilize the 5th mask on end face, to form pattern, on the bottom surface, form back-metal 360, as drain electrode.According to the same sampling technology shown in Fig. 3 A-1 to 3F-1, the termination structure of preparation shown in Fig. 2-1.
In order to reduce Qrr, Fig. 7 A to 7E is the profile of the optional preparation process of a kind of super-junction semiconductor power device that has an integrated Schottky diode of a series of expressions.These procedural representations prepare the optional method of P-column 315.In Fig. 7 A, preparation process is at first from the N-epitaxial loayer 410 of growing at N+ substrate 405.In Fig. 7 B, utilize mask (not expressing among the figure) in epitaxial loayer 410, to open a plurality of deep trench 415.In Fig. 7 C, 415-P fills deep trench with the P-dopant material, in Fig. 7 D, utilizes chemico-mechanical polishing (CMP) technology to carry out the planarization processing procedure then, removes the P-dopant material from the end face of epitaxial loayer 410 tops.Thereby in epitaxial loayer 410, form a plurality of P and N column 415-P and 410-N.
In Fig. 7 E, utilize the identical preparation process shown in Fig. 6 E to 6I, form and the integrated super-junction semiconductor power device 400 of Schottky diode.Super junction device 400 is positioned on the N+ silicon substrate 405 that has N-epitaxial loayer 410, epitaxial loayer be formed on N+ substrate 405 (for example shown in an embodiment in, be the arsenic doping substrate layer) top, have P-doping vertical pillars 415-P in the epitaxial loayer.Planar gate 430 is formed on grid oxic horizon 425 tops.This tagma 435 of P-is formed in the epitaxial loayer of grid oxic horizon below 425 that surrounds N+ source area 440.Use for high tension apparatus, this tagma 435 of P-is formed on P-doping column 415-P top.P+ district 436 is formed in the P-body 435, is directly adjacent to source area 440.Cover the source metal 460 on the end face, directly contact with this tagma 435 of source area 440 and P-.Be formed on the back side of Semiconductor substrate 405 as the drain metal 470 of drain electrode, thereby constitute a vertical super junction power device.By with schottky metal 460 as source metal, cover on the end face of source area 440, P+ district 436 and Schottky contacts P-doped region 450 tops, inner Schottky diode and super junction device are integrated.Schottky metal 460 directly contacts with source area 440 with epitaxial loayer 410.In order to reduce leakage current, below the schottky metal between the grid 430 460, directly form an extremely shallow P implant layer 450.According to the same sampling technology shown in Fig. 3 A-1 to 3F-1, the termination structure of preparation shown in Fig. 2-1.
Fig. 8 represents to have the profile of the another kind of super-junction semiconductor power device 400 ' that is similar to the design feature shown in Fig. 7 E.Unique difference is, P-doping column 415-P ' extends downwards in epitaxial loayer 410, extends to the far place, top, bottom of the epitaxial loayer 410 that distance and base substrate N+ layer 405 have a common boundary always.
Although with regard to existing preferred embodiment, the present invention has done detailed description, and should understand these contents should be as limitation.For example, gate oxide can expand to the more gate-dielectric of broad sense, can with hard mask for example the oxide of nitride or deposition replace field oxide.After reading foregoing, for those skilled in the art, various changes and modifications undoubtedly will be apparent.Therefore, should think that appending claims contains whole variations and the correction in true intention of the present invention and the scope.
Claims (23)
1. a semiconductor power device that is arranged in the Semiconductor substrate that contains active element district and terminator is characterized in that, comprising:
A grid that constitutes by the patterned polysilicon layer on the end face that is arranged on described Semiconductor substrate;
A patterned field oxide is arranged in the described terminator, and in the described active element zone of described patterned polysilicon layer one gap area on leaving the end face of described Semiconductor substrate;
Be arranged on this tagma of the doping in the described Semiconductor substrate, this tagma is from beginning abundant diffusion with zone below the described end face that described gap area is alignd, and extends to described patterned polysilicon layer and the following zone of described patterned field oxide;
Be enclosed in the impure source district in described this tagma, and its conduction type is opposite with described this tagma; And
Be enclosed in described high concentration body-doped region in this tagma of source area, and its doping content ratio is round the doping content height in described this tagma of described source area.
2. semiconductor power device as claimed in claim 1 is characterized in that, also comprises:
A patterned schottky metal layer, occupied before covering by the described field oxide in the described active element zone, subsequently from the zone that the end face of described Semiconductor substrate is removed, wherein said patterned schottky metal layer also part extends in the described gap area, so that contact described this tagma and described source area, form described semiconductor power device integrated Schottky diode in described active element zone.
3. semiconductor power device as claimed in claim 2 is characterized in that, also comprises:
Shallow body-doped region is arranged on and is located immediately near described this tagma, described schottky metal layer below, and described this tagma of the depth ratio of shallow body-doped region is much shallow.
4. semiconductor power device as claimed in claim 2 is characterized in that, described Semiconductor substrate comprises that a N-type epitaxial loayer is used to carry the described body-doped region of the P-type conduction type of the described source area that surrounds N-type conduction type.
5. semiconductor power device as claimed in claim 2 is characterized in that, described Semiconductor substrate comprises a P-type epitaxial loayer, is used to carry the described body-doped region of the N-type conduction type of the described source area that surrounds P-type conduction type.
6. semiconductor power device as claimed in claim 2 is characterized in that, described semiconductor power device also comprises a metal oxide semiconductor field effect tube power device.
7. semiconductor power device as claimed in claim 2 is characterized in that, described semiconductor power device also comprises a N-NMOS N-channel MOS N field effect transistor power device that is positioned on the N-N-type semiconductor N substrate.
8. semiconductor power device as claimed in claim 2 is characterized in that, described semiconductor power device also comprises a P-NMOS N-channel MOS N field effect transistor power device that is arranged on the P-N-type semiconductor N substrate.
9. semiconductor power device as claimed in claim 2 is characterized in that, described semiconductor power device also comprises a kind of igbt power device.
10. semiconductor power device as claimed in claim 2, it is characterized in that, described semiconductor power device also comprises the igbt power device that is arranged on the N-N-type semiconductor N substrate, described N-N-type semiconductor N substrate comprises the P-type bottom layer that has N-type doped region, described N-type doped region is arranged on the Semiconductor substrate place, the integrated schottky diode described in the corresponding described active element district.
11. semiconductor power device as claimed in claim 2, it is characterized in that, described semiconductor power device also comprises a super-junction semiconductor power device, and described super-junction semiconductor power device contains alternating N-type and P-type doping column in the Semiconductor substrate that is arranged in below described body-doped region.
12. semiconductor power device as claimed in claim 2, it is characterized in that, described semiconductor power device also comprises a super-junction semiconductor power device that is arranged in the N-N-type semiconductor N substrate, Semiconductor substrate comprises the P-type column that is positioned at the below, described bulk doped district that is made of P-type alloy, and N-type column is between described P-type column.
13. a method that is used for preparing in Semiconductor substrate the semiconductor power device that is made of active element district and terminator is characterized in that, comprising:
In the above terminator and described active element district of described Semiconductor substrate end face, the growth field oxide, and form pattern;
On the end face of the described Semiconductor substrate of leaving described field oxide one gap area, deposit a polysilicon layer, and form pattern; And
Bulk doped by no mask is implanted, and forms the bulk doped district in described Semiconductor substrate, fully aligns with slit region, then described bulk doped district is diffused into this tagma in the described Semiconductor substrate.
14. method as claimed in claim 13 is characterized in that, also comprises:
Implant cingens high concentration bulk doped district, described this tagma, its doping content is also higher than the doping content in this tagma; And
Utilize source mask implant source polar region, the conduction type of source area is opposite with described this tagma, and source area is enclosed in described this tagma, and is enclosed by the bulk doped district of described high concentration and to gather around.
15. method as claimed in claim 14 is characterized in that, also comprises:
Above described semiconductor power device, deposit an insulating barrier, and open contact openings, and remove described field oxide with the contacting metal mask; And
The deposition schottky metal layer is filled described contact openings, to contact described this tagma and described source area, in described active element district, forms the integrated schottky diode of described semiconductor power device.
16. method as claimed in claim 14 is characterized in that, also comprises:
Above described semiconductor power device, deposit an insulating barrier, and open contact openings, and remove described field oxide with the contacting metal mask; And
Implant shallow body-doped region, described body-doped region is located immediately at below the described end face of described Semiconductor substrate near being arranged on described this tagma, and the degree of depth of described body-doped region is less than described this tagma.
17. method as claimed in claim 14, it is characterized in that, described implantation body-doped region step comprises, at the N-type epitaxial loayer that is arranged on the N-N-type semiconductor N substrate, P-type alloy is implanted to described bulk doped district, and implants the N-type source area that is enclosed in this tagma of described P-type.
18. method as claimed in claim 14, it is characterized in that, described implantation body-doped region step comprises, at the P-type epitaxial loayer that is arranged on the P-N-type semiconductor N substrate, N-type alloy is implanted to described bulk doped district, and implants the P-type source area that is enclosed in this tagma of described N-type.
19. method as claimed in claim 14 is characterized in that, also comprises the step of making the metal oxide semiconductor field effect tube power device.
20. method as claimed in claim 14 is characterized in that, also comprises the step of making the igbt power device.
21. method as claimed in claim 14, it is characterized in that, also comprise, in N-N-type semiconductor N substrate, make the igbt power device, near the bottom surface of described Semiconductor substrate, implant the P-type bottom that has N-type doped region, the N-type doped region in the described P-type bottom is corresponding with the integrated schottky diode described in the described active element district.
22. method as claimed in claim 14 is characterized in that, also comprises, by forming alternating N-type and P-type doping column in the described Semiconductor substrate below described body-doped region, makes the super-junction semiconductor power device.
23. method as claimed in claim 14, it is characterized in that, also comprise the step of making the super-junction semiconductor power device, by in N-N-type semiconductor N substrate, formation is positioned at the P-type column of the below, described bulk doped district that forms with the doping of P-type alloy, and N-type column is between P-type column.
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| US12/584,151 US8829614B2 (en) | 2009-08-31 | 2009-08-31 | Integrated Schottky diode in high voltage semiconductor device |
| US12/584,151 | 2009-08-31 |
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| TWI817120B (en) * | 2021-05-14 | 2023-10-01 | 國立臺灣大學 | Embedded Schottky Asymmetric Superjunction Power Semiconductor |
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Also Published As
| Publication number | Publication date |
|---|---|
| US8829614B2 (en) | 2014-09-09 |
| CN102005452B (en) | 2012-10-10 |
| TW201110318A (en) | 2011-03-16 |
| TWI411097B (en) | 2013-10-01 |
| US20110049564A1 (en) | 2011-03-03 |
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