CN103811545A - Power device for improving morphology of diffusion region and manufacture method thereof - Google Patents

Power device for improving morphology of diffusion region and manufacture method thereof Download PDF

Info

Publication number
CN103811545A
CN103811545A CN 201210438533 CN201210438533A CN103811545A CN 103811545 A CN103811545 A CN 103811545A CN 201210438533 CN201210438533 CN 201210438533 CN 201210438533 A CN201210438533 A CN 201210438533A CN 103811545 A CN103811545 A CN 103811545A
Authority
CN
Grant status
Application
Patent type
Prior art keywords
layer
region
diffusion region
epitaxial layer
power device
Prior art date
Application number
CN 201210438533
Other languages
Chinese (zh)
Other versions
CN103811545B (en )
Inventor
乐双申
徐旭东
李旺勤
Original Assignee
比亚迪股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025Channel region of field-effect devices
    • H01L29/1029Channel region of field-effect devices of field-effect transistors
    • H01L29/1033Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234Bipolar junction transistors [BJT]
    • H01L29/66325Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333Vertical insulated gate bipolar transistors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712Vertical DMOS transistors, i.e. VDMOS transistors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/72Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395Vertical transistors, e.g. vertical IGBT
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors

Abstract

The invention provides a power device for improving morphology of a diffusion region and a manufacture method thereof. The power device comprises a substrate, an epitaxial layer, a buried layer, and a source region. The buried layer between the source region and the epitaxial layer is a conducting channel region. A prediffusion region is formed in the epitaxial layer close to the conducting channel region. The power device further comprises a gate dielectric layer, a gate electrode, a dielectric layer, a front metal layer, a back diffusion region, and a back metal layer. According to the power device for improving morphology of the diffusion region, the prediffusion region enables the buried layer to be smoothly expanded towards the epitaxial layer so as to improve the morphology of the diffusion region at the edge of the channel, and optimize the electric field distribution of the power device under high temperature and high voltage. Therefore, the electric leakage level of the power device under high temperature and high voltage is reduced; and the thermal reliability of power devices such as MOSFET, IGBT, and the like can be substantially improved. The power device satisfies operating requirements in high temperature and large power environments. The manufacturing process of the power device is completely compatible with that of a conventional power device. The power device is simple in structure, convenient in manufacture, and has improved production efficiency and rate of finished products.

Description

一种改善扩散区域形貌的功率器件及其制造方法 A power device and a method of improving diffusion region topography

技术领域 FIELD

[0001] 本发明属于基本电气元件领域,涉及半导体器件的制备,特别涉及一种在栅氧化层做完之后注入一层浅层低浓度的扩散区域来改善扩散区域形貌的功率器件及其制造方法。 [0001] The present invention belongs to the field of basic electrical components, it involves preparing a semiconductor device, particularly to a shallow implantation diffusion layer of low concentration region after the gate oxide layer is done to improve the morphology of the diffusion region and a manufacturing power devices method.

背景技术 Background technique

[0002] 目前,功率MOSFET和IGBT的正面工艺主要包括如下步骤:以N型衬底上制备的器件为例进行说明,在N型衬底上,先用光刻技术定义出有源区,然后生长栅氧化层,再注入N型杂质改善器件J-FET效应,然后沉积多晶硅,用光刻定义并刻蚀出图形,并在没有多晶硅和栅氧化层的区域注入P型离子并驱入形成P-扩散区,在P-扩散区分别用光刻定义并注入P型离子和N型离子形成P+区和N+区,然后在上面生长硼磷硅玻璃当作正面栅极、漏极的隔离层,接着用光刻定义出接触孔并刻蚀掉隔离层,淀积上AlSi层并用光刻定义出连接线及栅极、漏极金属层,刻蚀金属后再做最外面的表面钝化层,最后光刻定义出封装接触孔。 [0002] Currently, the positive power MOSFET and IGBT technology include the following steps: preparing a device on a N-type substrate as an example, on the N type substrate to define an active region by photolithography, and then growing a gate oxide layer, and then N-type impurities implanted to improve the J-FET effect device, polysilicon is deposited and defined by photolithography and etched pattern, and P-type ions implanted in the polysilicon region and the gate oxide layer without and drive-in to form the P - diffusion region in the P- diffusion regions are defined by photolithography and ion implantation of P-type and N-type ions to form the P + region and the N + region, and then grown as borophosphosilicate glass above the front gate, the drain of the isolation layer, then contact holes are defined by photolithography and etching away the spacer layer, AlSi layer was deposited over the cable and define a gate, a drain metal layer by photolithography, and then etching the metal to make the outermost surface of the passivation layer, Finally, the package lithographically-defined contact holes.

[0003] 在以上现有技术中,由于P-扩散区域的表层有一层比衬底浓的N型区域,在P型扩散的时候由于浓度问题导致表面的P型掺杂不容易横向扩散而造成P型区域的形貌不是很理想,从而导致器件在可靠性测试过程中容易造成表面漏电而失效。 [0003] In the above prior art, since the surface layer of P- doped region of the substrate than the concentration of N-type regions, when the concentration of the P-type diffusion problems caused due to the P-type doping of the surface is not easily caused by lateral diffusion morphology of the P-type region is not very satisfactory, thereby causing the surface of the device is likely to cause leakage reliability testing and failure. 现有的改善方法有增加P-BODY区的杂质浓度使得PN结两侧的P型浓度大于N型浓度,从而改善P型的扩散之后的形貌。 The conventional method for improving an increase in impurity concentration of the P-BODY P-type region such that both sides of the PN junction is greater than the concentration of N-type concentration, thereby improving the morphology of the P-type diffusion later. 还有一种提高热可靠性的方法,在栅区和发射极之间设置的隔离层为氮化硅和掺磷氮化硅组成复合薄膜,这种方法虽然能够提高器件的热稳定性,但是没有从根本上解决器件表面附近扩散区域形貌不理想、复合中心多、漏电大的问题。 There is also a method of improving the reliability of heat in the gate and emitter electrodes disposed between the barrier layer is silicon nitride and phosphorus-doped silicon nitride composite film, although this method can improve the thermal stability of the device, but not solution diffusion region near the surface morphology of the device is not over, recombination centers, large leakage problem fundamentally.

发明内容 SUMMARY

[0004] 本发明旨在至少解决现有技术中存在的技术问题,特别创新地提出了一种改善扩散区域形貌的功率器件及其制造方法。 [0004] The present invention aims to solve at least the problems in the prior art technology, particularly the innovation put forward power device and a manufacturing method of improving diffusion region topography.

[0005] 为了实现本发明的上述目的,根据本发明的第一个方面,本发明提供了一种改善扩散区域形貌的功率器件,包括衬底及其上形成的外延层,所述外延层的掺杂类型与所述衬底的掺杂类型相同;在所述外延层内形成有埋层,所述埋层的上表面与外延层的上表面位于同一平面,所述埋层的掺杂类型与所述外延层的掺杂类型相反;在所述埋层内形成有源区,所述源区的上表面与所述外延层的上表面位于同一平面,所述源区的掺杂类型与所述外延层的掺杂类型相同;在所述外延层内形成有预扩散区,所述预扩散区与所述埋层连接,且所述预扩散区的上表面与所述外延层的上表面位于同一平面,所述预扩散区的掺杂类型与所述埋层的掺杂类型相同;在所述外延层的上表面上形成有栅介质层和栅极,所述栅介质层和栅极覆盖在埋层及所述源区的一部分之上 [0005] To achieve the above object of the present invention, according to a first aspect of the present invention, the present invention provides an improved diffusion region morphology power device, comprising a substrate and an epitaxial layer formed thereon, said epitaxial layer doping type and the same doping type of the substrate; within the epitaxial layer is formed with a buried layer, the upper surface of the upper surface of the epitaxial layer and the buried layer located on the same plane, said doped buried layer said opposite doping type as the epitaxial layer; forming an active region in the buried layer, the upper surface of the source region and the upper surface of the epitaxial layer in the same plane, the doping type of the source region the same type of doping of the epitaxial layer; pre-formed with a diffusion region within said epitaxial layer, the diffusion region connected to the pre-buried layer, and the upper surface of the pre-diffused region of said epitaxial layer located in the same plane on the surface of the pre-doping type and same doping type as the buried diffusion region; forming a gate dielectric layer and a gate on an upper surface of the epitaxial layer, and the gate dielectric layer a gate overlying a portion of the buried layer and the source region ;在所述栅极和外延层之上形成有介质层和正面金属层;在所述衬底之下形成有背面扩散区;以及在所述背面扩散区之下形成有背面金属层。 ; Formed over the epitaxial layer and the gate dielectric layer and a front metal layer; back surface diffusion region is formed beneath the substrate; and a metal layer formed on the back surface beneath the back surface of the diffusion region. [0006] 本发明采用预扩散区,使埋层向外延层平缓扩展,本发明改善了沟道边缘扩散区域的形貌,特别是在N型外延层中制备P型导电沟道的情形,由于采用预扩散区使沟道表面的P型载流子浓度提高,有利于扩散区P型掺杂的扩散,最终使得P型扩散区的形貌向N型外延层平缓延伸,从而优化了器件在高温高压下的电场分布,从而降低器件在高温高压下的漏电水平,能够大幅提高功率M0SFET、IGBT等功率器件的热可靠性。 [0006] The present invention uses a pre-diffusion region so that the buried layer into the epitaxial layer gradual expansion, the present invention improves the morphology of the channel diffusion region of the edge, particularly in the case of the preparation of P-type conductivity in the channel N type epitaxial layer, since the use of the P-type diffusion region pre carrier concentration of the channel to improve the surface is conducive to diffusion doped P-type diffusion region, such that the final morphology of the P-type diffusion region N type epitaxial layer extending flat, in order to optimize the device the electric field distribution at high temperature and pressure, thereby reducing the level of the drain of the device at high temperature and pressure, the heat can be significantly improved reliability of the power M0SFET, IGBT and other power devices. 适合高温、大功率环境下工作的需要。 Suitable for high temperature, high-power needs work environment.

[0007] 在本发明的一种优选实施例中,所述埋层内包括有与所述源区相连的导电沟道区和注入扩散区,所述导电沟道区位于源区与所述预扩散区之间且导电沟道区的上表面与所述外延层的上表面位于同一平面,所述注入扩散区位于源区的下方,所述导电沟道区与所述注入扩散区的掺杂类型与所述埋层的掺杂类型相同。 [0007] In one preferred embodiment of the present invention, including the buried conductive region and the channel region and the implanted source diffusion region connected to the conductive channel region is a source region and the inner layer is pre- and the upper surface of the conductive channel region is located between the diffusion region and the upper surface of the epitaxial layer in the same plane, the implanted region is located below the source diffusion region, said conductive region and the channel-doped diffusion region implantation of the same doping type as the buried layer.

[0008] 在本发明的另一种优选实施例中,所述导电沟道区与所述预扩散区相连。 [0008] In another preferred embodiment of the present invention, the channel region is connected to the conducting pre-diffusion region.

[0009] 本发明的导电沟道区与预扩散区相连,提高了导电沟道区边缘的载流子浓度,降低了埋层内掺杂粒子横向扩展的阻力,从而使埋层在形成过程中其内的掺杂粒子能够向外延层横向平缓扩展,改善了沟道边缘扩散区域的形貌,优化了器件在高温高压下的电场分布,降低器件在高温高压下的漏电水平。 [0009] The conduction channel region of the present invention is connected to the pre-diffusion region, the carrier concentration increased conduction channel edge regions to reduce the particles in the buried layer doped lateral extension of resistance, so that the buried layer is formed in the process particles doped therein transversely to the gradual expansion of the epitaxial layer, the edge of the channel improves the morphology of the diffusion region, optimized field devices distributed at high temperature and pressure, reducing the level of the drain of the device at high temperature and pressure.

[0010] 在本发明的一种优选实施例中,所述导电沟道区的深度小于所述注入扩散区和源区的深度之和。 [0010] In one preferred embodiment of the present invention, the depth of the conduction channel region is less than the injection region and the source diffusion region and the depth.

[0011] 在本发明的另一种优选实施例中,所述导电沟道区为轻掺杂,所述注入扩散区为 [0011] In another preferred embodiment of the present invention, the conductive channel region is lightly doped, the diffusion region is implanted

重掺杂。 Heavily doped.

[0012] 本发明通过控制导电沟道区的深度以及注入扩散区和源区的深度之和,并通过将埋层进行不均匀的掺杂,能够降低器件的导通电阻,提高器件的耐压水平。 [0012] The present invention, by controlling the depth of the conduction channel region and the source diffusion region and the injection zone and the depth, and non-uniform doping the buried layer, can reduce the on-resistance of the device, improve the withstand voltage of the device Level.

[0013] 在本发明的一种优选实施例中,所述预扩散区沿外延层深度方向的宽度逐渐变小。 [0013] In one preferred embodiment of the present invention, the pre-diffusion region becomes gradually smaller in the width direction of the depth of the epitaxial layer.

[0014] 在本发明的另一种优选实施例中,所述预扩散区沿外延层深度的剖面为锲形。 [0014] In another preferred embodiment of the present invention, the pre-diffusion area along the depth of the epitaxial layer is a cross-sectional wedge.

[0015] 本发明在外延层的上表面处,该预扩散区较宽,随着向外延层内部深入,预扩散区的宽度逐渐变小,从而使预扩散区越靠近外延层表面的载流子浓度越高,越靠近外延层表面,埋层内掺杂粒子的横向扩展阻力降低越明显。 [0015] The present invention, at the upper surface of the epitaxial layer, the pre-diffusion region wide, deep into the interior of the epitaxial layer with a width pre-diffusion region becomes gradually smaller, such that the pre-diffused region closer to the carrier surface of the epitaxial layer the higher the concentration, the closer the surface of the epitaxial layer, the buried layer of doped particle scale resistance is reduced more significantly.

[0016] 在本发明的一种优选实施例中,所述预扩散区的深度为0-5000A,所述预扩散区的浓度为E10-E13。 Depth [0016] In one preferred embodiment of the present invention, the pre-diffusion region is 0-5000A, the pre-concentration diffusion region of E10-E13.

[0017] 在本发明的另一种优选实施例中,所述介质层由二氧化硅和硼磷硅玻璃形成。 [0017] In another preferred embodiment of the present invention, the dielectric layer is formed of silicon dioxide and borophosphosilicate glass.

[0018] 本发明介质层能够提高器件的工作可靠性,适合高温、大功率环境下的需要。 [0018] The dielectric layer of the present invention can improve the reliability of the device, suitable for high temperature, high power requirements under environment.

[0019] 为了实现本发明的上述目的,根据本发明的第二个方面,本发明提供了一种改善扩散区域形貌的功率器件的制造方法,其包括如下步骤: [0019] To achieve the above object of the present invention, according to a second aspect of the present invention, the present invention provides a method of manufacturing a diffusion region to improve the morphology of the power device, comprising the steps of:

[0020] S1:提供衬底并在所述衬底上形成外延层,所述外延层的掺杂类型与所述衬底的掺杂类型相同; [0020] S1: providing a substrate and forming an epitaxial layer on the substrate, the epitaxial layer doping type and the same doping type of the substrate;

[0021] S2:在所述外延层之上形成栅介质层和栅极; [0021] S2: forming a gate dielectric layer and a gate on the epitaxial layer;

[0022] S3:所述外延层内形成预扩散区和埋层,所述埋层的掺杂类型与所述外延层的掺杂类型相反,所述预扩散区的掺杂类型与所述埋层的掺杂类型相同,其中,所述预扩散区位于所述外延层和所述埋层之间且位于栅介质层之下,所述预扩散区的上表面与所述外延层的上表面位于同一平面,所述埋层的上表面与外延层的上表面位于同一平面; [0022] S3: The pre-formed buried layer diffusion region and the epitaxial layer, the buried layer of the opposite doping type and a doping type of the epitaxial layer, the pre-doping type diffusion region and said buried doped layer of the same type, wherein the pre-diffused region in said gate dielectric layer and located below the pre-epitaxial layer between said buried layer and the upper surface of the diffusion region and the upper surface of the epitaxial layer located in the same plane, the upper surface of the buried layer on the surface of the epitaxial layer is located in the same plane;

[0023] S4:在所述埋层内形成有源区,所述源区的掺杂类型与所述外延层的掺杂类型相同,其中,所述源区的上表面与所述外延层的上表面位于同一平面; [0023] S4: forming the buried layer in the active region, the source region doping type and doping type of the epitaxial layer is the same, wherein an upper surface of said source region and said epitaxial layer located in the same plane on the surface;

[0024] S5:在所述栅极和源区之上形成介质层,并在所述介质层之上形成正面金属层,所述正面金属层通过所述接触孔与所述源区相连; [0024] S5: forming a dielectric layer over the gate electrode and the source region, and forming a metal layer over the front dielectric layer, said front metal layer through the contact hole connected to the source region;

[0025] S6:在所述衬底之下形成背面扩散区,所述背面扩散区为重掺杂; [0025] S6: forming a diffusion region beneath the back surface of the substrate, the back surface of the diffusion region is heavily doped;

[0026] S7:在所述背面扩散区之下形成有背面金属层。 [0026] S7: backside metal layer is formed below the back surface of the diffusion region.

[0027] 本发明的制造方法通过预扩散区使得制作的器件具有优良的热稳定性,能够大幅提高MOSFET、IGBT等功率器件的热可靠性,并且制造过程与现有的功率器件工艺完全兼容,具有结构简单、制造方便等显著特点,提高了生产效率和成品率。 A method for producing [0027] The present invention is such that the diffusion zone by pre-fabricated device having excellent thermal stability, thermal reliability can be greatly improved MOSFET, IGBT power devices and the like, and the manufacturing process is fully compatible with existing technology power devices, It has a simple structure, easy manufacturing, and other notable features, improve production efficiency and yield.

[0028] 在本发明的一种优选实施例中,当所述埋层包括导电沟道区和注入扩散区时,所述步骤S51具体包括以下步骤: [0028] In one preferred embodiment of the present invention, when the buried layer comprises a conductive channel region and the diffusion region implantation, the step S51 comprises steps of:

[0029] 在所述外延层内形成埋层的区域全部进行轻掺杂; Region [0029] formed within the buried layer all of a lightly doped epitaxial layer;

[0030] 在所述埋层的注入扩散区进行重掺杂。 [0030] implanted in the heavily doped buried layer diffusion region.

[0031] 本发明通过将埋层进行不均匀的掺杂,能够降低器件的导通电阻,提高器件的耐压水平。 [0031] The present invention is carried out by the non-uniform doped buried layer, the device can be reduced on-resistance and improve the level of pressure of the device.

[0032] 在本发明的另一种优选实施例中,所述步骤S3具体包括以下步骤: [0032] In another preferred embodiment of the present invention, the step S3 comprises the following steps:

[0033] S31:在栅介质层之下的外延层内形成预扩散区; [0033] S31: forming a pre-diffusion regions in the epitaxial layer beneath the gate dielectric layer;

[0034] S51:在外延层内形成埋层。 [0034] S51: buried layer formed in the epitaxial layer.

[0035] 在本发明的再一种优选实施例中,所述步骤S3具体包括以下步骤: [0035] In a further preferred embodiment of the present invention, the step S3 comprises the following steps:

[0036] S51:在外延层内形成埋层; [0036] S51: buried layer formed in the epitaxial layer;

[0037] S31:在栅介质层之下的外延层内形成预扩散区。 [0037] S31: forming a pre-diffusion regions in the epitaxial layer beneath the gate dielectric layer.

[0038] 本发明可以在埋层之前形成预扩散区,也可以在埋层之后形成预扩散区,提高了制备过程的灵活性。 [0038] The present invention may be pre-formed prior to the buried layer diffusion region may be formed after the pre-diffused buried layer regions, improving the flexibility of the manufacturing process.

[0039] 本发明的附加方面和优点将在下面的描述中部分给出,部分将从下面的描述中变得明显,或通过本发明的实践了解到。 [0039] Additional aspects and advantages of the invention will be set forth in part in the description which follows, from the following description in part be apparent from, or learned by practice of the present invention.

附图说明 BRIEF DESCRIPTION

[0040] 本发明的上述和/或附加的方面和优点从结合下面附图对实施例的描述中将变得明显和容易理解,其中: [0040] The foregoing and / or other aspects and advantages of the invention will be described with reference to embodiments in conjunction with the embodiments become apparent and more readily appreciated below, wherein:

[0041] 图1是本发明改善扩散区域形貌的功率器件的一种优选实施方式的结构示意图; [0041] FIG. 1 is a schematic structural diagram of a preferred embodiment of a diffusion region of a power device of the embodiment of the present invention improves the topography;

[0042] 图2-图8是图1中所示改善扩散区域形貌的功率器件的工艺步骤示意图。 [0042] FIG. 2-8 is a process step to improve the diffusion region of the power device 1 shown in FIG topography FIG. 附图标记: Reference numerals:

[0043] I衬底;2外延层;3预扩散区;4导电沟道区;5注入扩散区;6源区;7栅介质层;8栅极;9 二氧化硅层;10硼磷硅玻璃层;11正面金属层;12背面扩散区;13背面金属层。 [0043] I substrate; epitaxial layer 2; 3 pre-diffusion region; a conductive channel region 4; 5 implanted diffusion region; a source region 6; 7 gate dielectric layer; gate 8; a silicon dioxide layer 9; 10 borophosphosilicate glass layer; front side 11 of the metal layer; back surface diffusion region 12; backside metal layer 13.

具体实施方式 detailed description

[0044] 下面详细描述本发明的实施例,所述实施例的示例在附图中示出,其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。 [0044] Example embodiments of the present invention is described in detail below, exemplary embodiments of the embodiment shown in the accompanying drawings, wherein same or similar reference numerals designate the same or similar elements or elements having the same or similar functions. 下面通过参考附图描述的实施例是示例性的,仅用于解释本发明,而不能理解为对本发明的限制。 By following with reference to the embodiments described are exemplary only for explaining the present invention and should not be construed as limiting the present invention.

[0045] 在本发明的描述中,需要理解的是,术语“纵向”、“横向”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底” “内”、“外”等指示的方位或位置关系为基于附图所 [0045] In the description of the present invention, it is to be understood that the term "longitudinal", "lateral", "upper", "lower", "front", "rear", "left", "right", "vertical orientation or positional relationship indicated by the straight "," horizontal "," top "," bottom "," inner "," outer ", it is based on the drawings

示的方位或位置关系,仅是为了便于描述本发明和简化描述,而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作,因此不能理解为对本发明的限制。 Orientation or positional relationship shown, merely for convenience of description of the invention and to simplify the description, but does not indicate or imply that the device or element referred to must have a particular orientation in a particular orientation structure and operation, can not be construed as the present invention. limit.

[0046] 在本发明的描述中,除非另有规定和限定,需要说明的是,术语“安装”、“相连”、“连接”应做广义理解,例如,可以是机械连接或电连接,也可以是两个元件内部的连通,可以是直接相连,也可以通过中间媒介间接相连,对于本领域的普通技术人员而言,可以根据具体情况理解上述术语的具体含义。 [0046] In the present description, unless otherwise specified or limited, it is noted that the term "mounted," "connected to", "connected" are to be broadly understood, for example, it may be a mechanical or electrical connection, It may be in communication the interior of the two elements, may be directly connected, can also be connected indirectly through an intermediary, to those of ordinary skill in the art, to be understood that the specific meanings depending on the circumstances.

[0047] 图1是本发明改善扩散区域形貌的功率器件的一种优选实施方式的结构示意图,图中仅仅是示意的给出了各区域的尺寸,具体的尺寸可以根据器件参数的要求进行设计。 [0047] FIG. 1 is a schematic structural diagram of a preferred embodiment of a diffusion region of a power device of the embodiment of the present invention to improve the morphology of the figures are illustrative only shows the dimensions of each region, specific dimensions may be device parameters according to the requirements design. 从图中可见,该改善扩散区域形貌的功率器件包括衬底1,该衬底I可以是制备功率MOSFET或IGBT的任何衬底材料,具体可以是但不限于SO1、硅、锗、砷化镓,在本实施方式中,优选采用硅,该衬底I为轻掺杂,其掺杂类型为N型,在该衬底I上形成有外延层2,该外延层2的掺杂类型与衬底I的掺杂类型相同,该外延层2的掺杂类型为N型。 Be seen, the diffusion region to improve the morphology of the power device comprises a substrate 1 from the figure, the substrate may be any substrate material I Preparation of a power MOSFET or IGBT, specifically but not limited to S01, silicon, germanium, gallium arsenide gallium, in the present embodiment, preferably silicon, lightly doped the substrate I is a doping type is N-type epitaxial layer 2 is formed on the substrate I, type doped epitaxial layer 2 and the same doping type as the substrate I, the type epitaxial layer 2 is doped N-type. 在外延层2内形成有埋层,埋层的掺杂类型与外延层2的掺杂类型相反,即该埋层为P型掺杂,该埋层包括导电沟道区4和注入扩散区5,外延层2相对于埋层部分地暴露。 Is formed with a buried layer, the buried layer of the opposite doping types and doping type epitaxial layer 2, i.e., the P-type buried layer is doped, and the buried layer 4 comprises injecting a conductive diffusion region in a channel region within the epitaxial layer 25 epitaxial layer 2 is partially exposed to the buried layer. 在本发明的一种优选实施方式中,该埋层为均匀掺杂,在本发明的另外一种优选实施方式中,该埋层为非均匀掺杂,埋层的导电沟道区4为轻掺杂,注入扩散区5为重掺杂。 In a preferred embodiment of the present invention, the buried layer is uniformly doped, in another preferred embodiment of the present invention, the non-uniform doped buried layer, the buried layer is a conductive channel region 4 is light doped, implanted diffusion region 5 is heavily doped. 在埋层内形成有源区6,源区6的掺杂类型与外延层2的掺杂类型相同,即该源区6暴露于外延层2的上表面,该源区6为重掺杂,源区6的掺杂类型与外延层2的掺杂类型相同,即源区6的掺杂类型与埋层的掺杂类型相反,在本实施方式中,该源区6的掺杂类型为N型,源区6与外延层2之间的埋层为导电沟道区4。 Forming an active region in the buried layer 6, the same doping type as the source region 6 and the epitaxial layer doping type 2, i.e., the source region 6 is exposed to the upper surface of the epitaxial layer 2, the heavily doped source regions 6, 6 of the same doping type epitaxial layer doping type source region 2, i.e., doping type opposite the doping type source region and the buried layer 6, in the present embodiment, the source region 6 is doped N type type source region 6 and the buried layer between the epitaxial layer is a conductive channel region 4.

[0048] 具体地,在外延层2内形成有预扩散区3,该预扩散区3与埋层连接,且预扩散区3的上表面与外延层2的上表面位于同一平面,该预扩散区3的掺杂类型与埋层的掺杂类型相同,即预扩散区3的掺杂类型与外延层2的掺杂类型相反,具体的,该预扩散区3为P型掺杂,其从外延层2的上表面深入到外延层2内部,其厚度为0-5000A,其浓度为E10-E13。 [0048] In particular, with a pre-diffusion region 3 is formed in the epitaxial layer 2, the pre-diffusion region 3 is connected to the buried layer, and the upper surface of the upper surface of the epitaxial layer 3 2 of the pre-diffused region in the same plane, the pre-diffusion the same doping type doping type buried layer region 3, i.e., the pre-doping type opposite doping type diffusion region 2 of the epitaxial layer 3, specifically, the pre-diffusion of P-type doped region 3, from which 2 the upper surface of the epitaxial layer deep into the epitaxial layer 2 having a thickness of 0-5000A, a concentration of E10-E13. 需要说明的是,在本发明的实施例中,预扩散区3可先于埋层形成,也可晚于埋层形成。 Incidentally, in the embodiment of the present invention, the pre-diffusion region 3 may be formed on the first buried layer, the buried layer may be formed in the later.

[0049] 具体地,导电沟道区4和注入扩散区5形成在外延层2与源区6之间,且注入扩散区5位于源区6之下。 [0049] Specifically, the channel region 4 and the injection conductive diffusion region 5 is formed between the epitaxial layer 2 and the source region 6, and implantation diffusion region 5 located under the source region 6. 那么,该预扩散区3位于与导电沟道区4相连的外延层2内,该预扩散区3可以与导电沟道区4相连,也可以与导电沟道区4不相连。 Then, the pre-diffusion region 3 is connected to an epitaxial layer 4 with the conductive region inside the channel 2, the channel regions may be connected to the conductive diffusion region 3 of the pre-4, may not be connected to the conductive channel region 4. 如图1所示,所述导电沟道区4的深度小于所述注入扩散区5和源区6的深度之和。 1, the depth of the conduction channel region 4 is smaller than the implantation region 5 and the source diffusion region 6 and the sum of the depth.

[0050] 由于越靠近埋层的表面,掺杂粒子的横向扩展阻力越大,在本实施方式中,预扩散区3沿外延层2深度方向的宽度逐渐变小,即在外延层2的上表面处,该预扩散区3较宽,随着向外延层2内部深入,预扩散区3的宽度逐渐变窄,优选情况下,预扩散区3沿外延层深度方向的剖面为锲形。 [0050] Since the surface closer to the buried layer, doped particles larger scale resistance, in the present embodiment, a width of 3 along the depth direction of the epitaxial layer 2 is pre-diffusion region becomes gradually smaller, i.e. on the epitaxial layer 2 at the surface, the pre-wide diffusion region 3, with the depth of the epitaxial layer 2 to the inside width of the pre-diffused region 3 is gradually narrowed, preferably, the pre-diffusion region 3 in the depth direction of the cross section of the epitaxial layer wedge. 由于在外延层2的上表面处,该预扩散区3较宽,随着向外延层内部深入,预扩散区3的宽度逐渐变窄,从而使预扩散区3越靠近外延层2表面的载流子浓度越高,埋层内掺杂粒子的横向扩展阻力降低越明显。 Since the upper surface of the epitaxial layer 2, the pre-wide diffusion region 3, with the depth of the epitaxial layer to the inside width of the pre-diffused region 3 is gradually narrowed, so that the pre-diffused region 3 closer to the carrier surface of the epitaxial layer 2 the higher the carrier concentration, doping scale particles in the buried layer resistance decreased more significantly. 通过采用与埋层掺杂类型相同的预扩散区3,提高了导电沟道区边缘的载流子浓度,降低了埋层内掺杂粒子横向扩展的阻力,从而使埋层在形成过程中其内的掺杂粒子能够向外延层横向平缓扩展,改善了沟道边缘扩散区域的形貌,优化了器件在高温高压下的电场分布,降低器件在高温高压下的漏电水平。 The buried layer is doped by employing the same type of pre-diffusion region 3, the carrier concentration increases the conduction channel region edges, reduced particle doped buried layer scale resistance, so that the buried layer is formed in the course of which doping particles in the gradual extension transversely to the epitaxial layer, the edges of the channel improves the morphology of the diffusion region, optimized field devices distributed at high temperature and pressure, reducing the level of the drain of the device at high temperature and pressure. 在外延层2内还可以形成有隔离区,用于功率器件之间的隔离,该隔离区与预扩散区3分别位于埋层的两侧,其可以与埋层相连,也可以与埋层不相连。 In the epitaxial layer 2 may be formed with an isolation region for isolating between the power device, the isolation region and the diffusion region 3 are pre-buried layer located on both sides, which can be connected to the buried layer, the buried layer may not connected. 该隔离区可以为场氧区或深槽隔离区,在本实施方式中,优选采用场氧区进行隔离。 The isolation region may be a deep trench isolation regions or field oxide regions, in the present embodiment is preferably used for the isolation field oxide region.

[0051] 在本实施方式中,在埋层及源区6的一部分之上形成有栅介质层7,在本发明另外的优选实施方式中,在导电沟道区4及其之间的外延层2和源区6的一部分之上形成有栅介质层7,在本发明另外的优选实施方式中,也可以只在导电沟道区4之上形成栅介质层7,在该栅介质7之上形成有栅极8,在栅极8之上以及未被栅极8和栅介质层7覆盖的外延层2之上覆盖有一层介质层,该介质层上具有贯通至源区的接触孔,在该接触孔内填充有正面金属层11,该正面金属层11通过接触孔与源区6相连。 [0051] In the present embodiment, the gate dielectric layer is formed over a portion of the buried layer 7 and the source region 6, in a further preferred embodiment of the present invention, the epitaxial layer and the channel region 4 between the conductive 2 and a portion of the source region 6 is formed over the gate dielectric layer 7, in a further preferred embodiment of the present invention, the gate dielectric layer 7 may be formed only over the conductive channel region 4, over the gate dielectric 7 a gate 8, as well as over the gate 8 on the dielectric layer 2 is not covered with a gate electrode 8 and the gate dielectric layer covering the epitaxial layer 7, having a through hole to the source region of the contact layer on the medium, the the contact hole is filled with a positive metal layer 11, metal layer 11 is connected to the front side to the source region through the contact hole 6. 栅介质层7可以是制备晶体管中使用的任何栅介质材料,可以为但不限于高K介质、二氧化硅,在本实施方式中,优选采用二氧化硅。 Gate dielectric layer 7 may be any transistor in the gate dielectric material is prepared for use, but may be limited to a high K dielectric, silicon dioxide, in the present embodiment, silica is preferably used. 栅极8可以为但不限于多晶硅栅极或金属栅极,在本实施方式中,优选采用多晶硅栅极。 The gate 8 may be, but is not limited to the polysilicon gate or a metal gate, in the present embodiment, the polysilicon gate is preferably used. 介质层可以为但不限于硅的氧化物、硅的氮化物、硅的氮氧化物、硼磷硅玻璃,在本实施方式中,优选米用一层二氧化娃层9和一层硼磷娃玻璃层10共同形成。 Dielectric layer may be, but is not limited to silicon oxide, silicon nitride, silicon oxynitride, borophosphosilicate glass, in the present embodiment, preferably with a layer of rice baby dioxide layer 9 and a layer of boron phosphorous doll 10 together form a glass layer. 在衬底I之下形成有背面扩散区12,背面扩散区12为重掺杂,掺杂类型可以与衬底I的掺杂类型相同,也可以与衬底I的掺杂类型相反,当背面扩散区12的掺杂类型与衬底I的掺杂类型相同,即为N型掺杂时,为MOSFET器件;当背面扩散区12的掺杂类型与衬底I的掺杂类型相反,即为P型掺杂时,为I GBT器件,在背面扩散区12之下形成有背面金属层13,在本发明的一种优选实施方式中,该背面金属层13包括三层金属,依次为钛、镍、金或者钛、镍、银。 I is formed below the substrate back surface diffusion region 12, the back diffusion region 12 is heavily doped, dopant types may be the same doping type as the substrate I may be opposite to the doping type of the substrate I, when the back surface the same doping type doping type diffusion region 12 and the substrate I, namely N-type doping, is a MOSFET device; I when the opposite doping type doping type diffusion regions 12 and the back surface of the substrate, i.e. P-type doping, I GBT device is formed under the back surface of the diffusion region 12 with a backside metal layer 13, in one preferred embodiment of the present invention, the back metal layer 13 comprises three layers of metal, followed by titanium, nickel, gold or titanium, nickel and silver.

[0052] 本发明还提出了一种改善扩散区域形貌的功率器件的制造方法,图2-图8是图1中所示改善扩散区域形貌的功率器件的工艺步骤示意图,所述方法包括如下步骤: [0052] The present invention also proposes a method for producing a diffusion region to improve power device topography, 2-8 improving diffusion region topography power device shown in Figure 1 a schematic view of the process step, said method comprising the steps of:

[0053] Sll:提供衬底I并在衬底I上形成外延层2,该外延层2与衬底I的掺杂类型相同; [0053] Sll: I providing a substrate and forming an epitaxial layer on a substrate I 2, the epitaxial layer 2 and the substrate I of the same doping type;

[0054] S21:在外延层2之上形成栅介质层7 ; [0054] S21: epitaxial layer forming a gate over the second dielectric layer 7;

[0055] S31:在栅介质层7之下的外延层2内形成预扩散区3,该预扩散区3与衬底I的掺杂类型相反; [0055] S31: epitaxial layer 2 is formed beneath the gate dielectric layer 7 of the pre-diffused region 3, the pre-doping type diffusion region 3 and the opposite substrate I;

[0056] S41:在栅介质层7之上形成栅极8 ; [0056] S41: gate dielectric layer is formed over the gate electrode 7 8;

[0057] S51:在外延层2内形成埋层,埋层的掺杂类型与外延层2的掺杂类型相反,即埋层的掺杂类型与预扩散区3的掺杂类型相同,埋层包括导电沟道区4和注入扩散区5,其中,预扩散区3位于外延层2和埋层之间,外延层相对于埋层部分地暴露。 [0057] S51: epitaxial layer 2 is formed in the buried layer, the buried layer of the opposite doping type doping type epitaxial layer 2, i.e., the pre-doping type diffusion region buried layer 3 of the same doping type, a buried layer 4 and includes a conductive channel region implanted diffusion region 5, wherein, the pre-diffusion region 3 is located between the epitaxial layer 2 and the buried layer, the epitaxial layer to the buried layer partially exposed.

[0058] S61:在埋层内形成有源区6,该源区6为重掺杂,其掺杂类型的掺杂类型与外延层2的掺杂类型相同,其中,导电沟道区4和注入扩散区5形成在外延层2与源区6之间,且注入扩散区5位于源区6之下。 [0058] S61: the active region 6 is formed in the buried layer, the heavily doped source region 6, the same type of doping type doped epitaxial layer 2 of type dopant, wherein the conductive channel region 4 and implanted diffusion region 5 is formed between the epitaxial layer 2 and the source region 6, and implantation diffusion region 5 located under the source region 6.

[0059] S71:在栅极8和源区6之上形成介质层,介质层上具有贯通至源区6的接触孔; [0059] S71: forming a dielectric layer over the gate electrode 8 and the source region 6, having a contact hole to the source region through the dielectric layer 6;

[0060] S81:在介质层之上形成正面金属层11,该正面金属层11通过接触孔与源区6相连; [0060] S81: forming a metal layer over the front dielectric layer of the front surface of the metal layer 11 through the contact hole 11 is connected to the source region 6;

[0061] S91:在衬底I之下形成背面扩散区12,该背面扩散区12为重掺杂;[0062] SlOl:在背面扩散区12之下形成有背面金属层13。 [0061] S91: forming a diffusion region beneath the back surface of the substrate I 12, the back surface 12 is a heavily doped diffusion region; [0062] SlOl: backside metal layer 13 is formed under the back surface of the diffusion region 12.

[0063] 在步骤Sll中:如图2所示,提供衬底I,该衬底I可以是制备功率MOSFET或IGBT的任何衬底材料,具体可以是但不限于SO1、硅、锗、砷化镓,在本实施方式中,优选采用硅,该衬底I为轻掺杂,在该衬底I上形成有外延层2,该外延层2与衬底I的掺杂类型相同,即可以均为N型,形成该外延层2的方法可以为但不限于化学气相淀积,在外延层2内还可以形成有隔离区,该隔离区可以为场氧区或深槽隔离区,在本实施方式中,优选采用场氧区进行隔离。 [0063] In the step Sll: 2, I provide a substrate, the substrate may be any substrate material I Preparation of a power MOSFET or IGBT, specifically but not limited to S01, silicon, germanium, gallium arsenide gallium, in the present embodiment, preferably silicon, the substrate I is lightly doped epitaxial layer 2 is formed on the substrate I, I the same doping type as the substrate and the epitaxial layer 2, i.e., can both N-type epitaxial layer 2 is formed of the method may be but not limited to chemical vapor deposition, in the epitaxial layer 2 may be formed with a further isolation region, the isolation region may be a deep trench isolation region or a field oxide region, the present embodiment embodiment is preferably used for the isolation field oxide region.

[0064] 在步骤S21中:如图3所示,在外延层I之上形成栅介质层7,该栅介质层7可以是制备晶体管中使用的任何栅介质材料,可以为但不限于高K介质,二氧化硅,在本实施方式中,优选采用二氧化硅,形成栅介质层的具体方法可以为但不限于化学气相淀积。 [0064] In step S21: 3, forming a gate dielectric layer over the I epitaxial layer 7, the gate dielectric layer 7 may be any transistor in the gate dielectric material is prepared for use, it may be, but not limited to high K medium specific method silica, in the present embodiment, silica is preferably used to form a gate dielectric layer may be, but not limited to chemical vapor deposition. 在本发明的一个实施例中,也可在该步骤中形成栅极8,或者,在本发明的其他实施例中,也可在步骤S4中形成。 In one embodiment of the present invention may also be formed in this step, the gate electrode 8, or may be formed in a step S4, in other embodiments of the present invention.

[0065] 在步骤S31中,如图4所示,在栅介质层7之下的外延层2内形成预扩散区3,该预扩散区3的掺杂类型与外延层2的掺杂类型相反,即该预扩散区3为P型掺杂,且预扩散区3的上表面与外延层2的上表面位于同一平面,其从外延层2的上表面深入到外延层内部,其深度为0-5000A,其浓度为E10-E13,形成预扩散区的具体方法为光刻,在掩膜掩蔽的情况下进行离子注入,并扩散,退火的方法。 [0065] In step S31, as shown, the epitaxial layer beneath the gate dielectric layer 7 2 3 pre-diffusion region 4 is formed, instead, the pre-doping type diffusion region 3 and the doping type epitaxial layer 2 , i.e., the pre-diffusion region 3 is P-doped and the upper surface of the upper surface of the epitaxial layer 2 is pre-diffusion region 3 located in the same plane, which is from the upper surface of the epitaxial layer 2 deep into the epitaxial layer to a depth of 0 -5000A, at a concentration of E10-E13, the specific method of pre-diffusion region is formed in a photolithography, ion implantation is masked in the case of a mask, and the diffusion annealing method.

[0066] 在步骤S41中,如图5所示,在栅介质层7之上形成栅极8,该栅极8可以为但不限于多晶硅栅极或金属栅极,在本实施方式中,优选采用多晶硅栅极,形成栅极的具体方法可以为但不限于化学气相淀积。 [0066] In step S41, FIG. 5, the gate electrode 8 is formed over the gate dielectric layer 7, the gate 8 may be but not limited to polysilicon gate or a metal gate, in the present embodiment, it is preferred specific methods polysilicon gate, forming the gate may be but not limited to chemical vapor deposition.

[0067] 在步骤S51中,如图6所示,在外延层2内形成埋层,该埋层与预扩散区3相连,该预扩散区3的掺杂类型与埋层的掺杂类型相同,埋层为P型掺杂,该埋层包括导电沟道区4和注入扩散区5,在本发明的一种优选实施方式中,该埋层为均匀掺杂,在本发明的另外一种优选实施方式中,该埋层为非均匀掺杂,埋层的导电沟道区4为轻掺杂,注入扩散区5为重掺杂,形成该非均匀掺杂的埋层的步骤为:首先,在外延层内形成埋层的区域全部进行轻掺杂,掺杂类型为P型;然后,在埋层的注入扩散区5进行重掺杂,掺杂类型为P型。 [0067] In step S51, the same type of doping as shown in FIG. 6, the buried layer is formed in the epitaxial layer 2, which is connected to the pre-diffused buried layer region 3, the pre-doping type diffusion region buried layer 3 , P-doped buried layer, the buried layer comprising a conductive channel region 4 and the injection diffusion region 5, in a preferred embodiment of the present invention, the buried layer is uniformly doped, the present invention in another in a preferred embodiment, the buried layer is non-uniformly doped, conductive region buried layer 4 of the channel is lightly doped, implanted diffusion region 5 is heavily doped, forming the buried layer is non-uniform doping steps of: firstly , the buried layer region is formed in all of the epitaxial layer is lightly doped, dopant type is P type; then implanted in the diffusion region 5 is heavily doped buried layer, doped type is P type. 形成埋层的方法具体为光刻,在掩膜掩蔽的情况下进行离子注入,并扩散,退火的方法。 The method of forming a buried layer in particular photolithography, ion implantation is masked in the case of a mask, and the diffusion annealing method.

[0068] 在步骤S61中,如图7所示,在埋层内形成有源区6,该源区6暴露于外延层2的上表面,该源区6为重掺杂,其掺杂类型为N型,形成源区6的具体方法为光刻,在掩膜掩蔽的情况下进行离子注入,并扩散,退火的方法。 [0068] In step S61, shown in Figure 7, the active region 6 is formed in the buried layer, the source region 6 is exposed to the upper surface of the epitaxial layer 2, the heavily doped source regions 6, type doped N-type, the specific method for forming the source region 6 as photolithography, ion implantation is masked in the case of a mask, and the diffusion annealing method.

[0069] 在步骤S71中,如图8所示,在栅极8以及未被栅极8和栅介质层7覆盖的外延层2之上形成介质层,该介质层上具有贯通至源区的接触孔,该介质层可以为但不限于硅的氧化物、硅的氮化物、硅的氮氧化物、硼磷硅玻璃,在本实施方式中,优选采用二氧化硅层9和硼磷硅玻璃层10。 [0069] In step S71, as shown, the dielectric layer is formed over the gate 8 and the gate electrode 8 and the epitaxial layer is not the gate dielectric layer 728 is covered with a through to the source region on the dielectric layer a contact hole, the dielectric layer may be, but is not limited to silicon oxide, silicon nitride, silicon oxynitride, borophosphosilicate glass, in the present embodiment, the silicon dioxide layer 9 is preferably used and borophosphosilicate glass layer 10. 在步骤S81中,在介质层之上形成正面金属层11,该正面金属层11通过接触孔与源区6相连。 In step S81, the metal layer is formed on the front dielectric layer 11 is connected to the front side metal layer 11 through the contact hole to the source region 6. 在本实施方式中,在正面金属层11之上还可以形成钝化层,该钝化层的材料具体可以为但不限于二氧化硅。 In the present embodiment, the metal layer 11 on the front passivation layer may also be formed, particularly a material of the passivation layer may be, but is not limited to silicon dioxide.

[0070] 在步骤S91和步骤SlOl中,在衬底I之下形成背面扩散区12,该背面扩散区12为重掺杂,其掺杂类型可以与衬底I的掺杂类型相同,也可以与衬底I的掺杂类型相反,当背面扩散区12的掺杂类型与衬底I的掺杂类型相同时,为MOSFET器件,当背面扩散区12的掺杂类型与衬底I的掺杂类型相反时,为I GBT器件,形成背面扩散区的具体方法为光刻,在掩膜掩蔽的情况下进行离子注入,并扩散,退火的方法。 [0070] In step S91 and step SlOl formed under the back surface of the substrate I diffusion regions 12, the back surface of a heavily doped diffusion region 12, which may be the same doping type doping type of the substrate I may be and doping type of the substrate opposite to I, when the back surface of the diffusion region and the doping type of the substrate 12 is the same doping type I, is a MOSFET device, when the back surface of the substrate doping type diffusion region 12 doped I opposite type specific method for device I GBT, the back diffusion region is formed as photolithography, ion implantation is masked in the case of a mask, and the diffusion annealing method. 在背面扩散区12之下形成有背面金属层1,该背面金属层13包括三层金属,依次为钛、镍、金或者钛、镍、银。 Diffusion regions formed under the back surface of the metal layer 12 has a back surface, the back surface 13 comprises three metal layer is a metal, followed by titanium, nickel, gold or titanium, nickel and silver. 当进行完第八步后,即得到图1所示的器件结构。 After an eighth step when carried out, to obtain the device structure shown in FIG.

[0071] 在本实施方式中,步骤S21和步骤S41可以在步骤S61和步骤S71之间进行,即可以先在外延层2内形成预扩散区3,该预扩散区3的掺杂类型与衬底I的掺杂类型相反,即为P型;然后在外延层2内形成埋层,该埋层与预扩散区3相连,埋层的掺杂类型与衬底的掺杂类型相反,即为P型;随后在埋层内形成有源区6,该源区6为重掺杂,其掺杂类型与衬底I的掺杂类型相同,即为N型;再后,在外延层2之上形成栅介质层7,在栅介质层7之上形成栅极8。 [0071] In the present embodiment, step S21 and step S41 may be performed between step S61 and step S71, the pre i.e. diffusion region 3 can be formed in the first epitaxial layer 2, the pre-doping type diffusion region and the substrate 3 the end opposite to the doping type I, that is P-type; buried layer is then formed in the epitaxial layer 2, which is connected to the buried diffusion region 3 and the pre-layer, a doping type opposite the doping type of the substrate and the buried layer, namely P-type; followed by active region 6 is formed in the buried layer, the heavily doped source region 6, the same doping type I and type doped substrate, that is N-type; after another, in the epitaxial layer 2 7 is formed on the gate dielectric layer, gate electrode 8 is formed over the gate dielectric layer 7.

[0072] 在本发明另外的优选实施方式中,也可以将步骤S41移到步骤S31之前,即形成栅介质层7和栅极8后,再形成预扩散区3。 [0072] In a further preferred embodiment of the present invention, it may be prior to step S41 to step S31, i.e., forming a gate dielectric layer 7 and the gate 8, and then pre-diffusion region 3 is formed.

[0073] 在本发明另外的优选实施方式中,还可以步骤S31和步骤S51之间进行互换,即先在外延层2中形成埋层,之后在外延层2内形成预扩散区3。 [0073] In a further preferred embodiment of the present invention, the step may also be interchanged between S31 and step S51, i.e., the first buried layer is formed in the epitaxial layer 2, after pre-diffusion region 3 is formed in the epitaxial layer 2.

[0074] 根据本发明的制造方法,在本发明的一种优选实施方式中,改善扩散区域形貌的IGBT的制备方法为:首先,在轻掺杂的η型硅衬底I上通过外延生长法形成η型外延层2,本实施方式中,以在η型衬底上制作动态随机存储器单元为例,对于P型衬底上制备的器件,按照相反的掺杂类型掺杂即可。 [0074] According to the production method of the present invention, in a preferred embodiment of the present invention, the improved method of preparing an IGBT diffusion region topography as follows: First, on a lightly doped η-type silicon substrate by epitaxial growth I method η -type epitaxial layer 2 is formed, according to the present embodiment, in fabricating a DRAM cell on the η-type substrate as an example, for the devices fabricated on the P-type substrate, in the opposite doping type to the doping. 然后,在η型外延层上按照预定的器件结构利用化学气相淀积法淀积二氧化硅作为栅介质层7,随后利用化学气相淀积法淀积η型杂质掺杂的多晶娃,通过光刻和蚀刻工艺形成器件的栅极8 ;随后,在η型外延层上光刻、注入P型杂质,并经高温热处理扩散形成P-型薄层,即预扩散层3,在本实施方式中,注入源可以采用Bll或BF2,注入剂量在Ε12量级,输入能量为10〜50Kev ;再后,依次采用离子注入方法从栅极的两侧分别注入P-及根据预定结构注入P+,并经高温热处理形成P-导电沟道区4和P+注入扩散区5 ;然后,注入N+杂质,形成源区6 ;在功率器件的表面淀积介质层,包括二氧化硅层9和硼磷硅玻璃层10,并按照预定结构光刻、刻蚀出金属接触孔,随后,在功率器件的表面淀积金属层,并按照预定结构光刻并刻蚀形成正面金属层11 ;然后,将器件背面减薄,在掩膜掩蔽 Then, in the η-type epitaxial layer according to a predetermined device structure using chemical vapor deposition depositing silicon dioxide as the gate dielectric layer 7, deposited η-type impurity-doped polycrystalline followed by the baby using a chemical vapor deposition process, by photolithography and etching processes form a gate device 8; then, η-type epitaxial layer in the photolithography, implanting the P-type impurity, and a high temperature diffusion heat treatment formed a thin layer of P- type, i.e., pre-diffusion layer 3, in the present embodiment , the injection may be employed Bll source or BF2, is injected in a dose Ε12 order of input energy is 10~50Kev; after another, sequentially P- ion implantation and implantation method according to a predetermined injection from both sides of the gate structures are P +, and conducting high temperature heat treatment is formed by P- channel region 4 and the P + diffusion region 5 is implanted; then, N + impurity implanted to form the source regions 6; depositing a dielectric layer on a surface of the power device, comprising a silicon dioxide layer 9 and borophosphosilicate glass layer 10, and in accordance with a predetermined structure lithography, etching the metal contact, and then, the surface of the power device deposited metal layer, and photolithography and etching in accordance with a predetermined configuration front metal layer 11 is formed; then, the backside of the device Save thin, masking the mask 情况下进行离子注入P型杂质,并扩散,退火,形成背面扩散区12 ;最后,在背面扩散区12之下淀积钛、镍、金形成有背面金属层13。 Case where P-type impurity ion implantation and diffusion, annealing, diffusion region 12 formed in the back surface; and finally, depositing a titanium diffusion regions 12 under the rear surface, nickel, gold, a metal layer 13 formed on the back surface. 本实施方式通过采用P型预扩散区3,使沟道表面的P型掺杂浓度提高,比较有利与P-埋层的横向扩散,最终使得P-埋层向η型外延层横向延伸,改善了扩散形貌。 Embodiment of the present embodiment by using the pre-P-type diffusion region 3, the P-type surface channel doping concentration is increased, more favorable lateral diffusion of the buried layer and P-, such that the final P- buried layer extends laterally η-type epitaxial layer, to improve the diffusion morphology.

[0075] 在本发明的制造方法中,通过扩散区使得制作的器件具有优良的热稳定 [0075] In the manufacturing method of the present invention, by making the diffusion region such that the device has excellent thermal stability

[0076] 性,能够大幅提高MOSFET、IGBT等功率器件的热可靠性,并且制造过程与现有的功率器件工艺完全兼容,具有结构简单、制造方便等显著特点,提高了生产效率和成品率。 [0076] resistance, thermal reliability can be greatly improved MOSFET, IGBT power devices and the like, and the manufacturing process is fully compatible with existing technology power device having a simple structure, easy manufacturing, and other notable features, improve production efficiency and yield.

[0077] 在本说明书的描述中,参考术语“一个实施例”、“一些实施例”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本发明的至少一个实施例或示例中。 [0077] In the description of the present specification, reference to the term "one embodiment," "some embodiments", "an example", "a specific example", or "some examples" means that a description of the exemplary embodiment or embodiments described a particular feature, structure, material, or characteristic is included in at least one embodiment of the present invention, embodiments or examples. 在本说明书中,对上述术语的示意性表述不一定指的是相同的实施例或示例。 In the present specification, a schematic representation of the above terms necessarily referring to the same embodiment or example. 而且,描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。 Furthermore, the particular features, structures, materials, or characteristics described embodiments or examples may be at any one or more in a proper manner.

[0078] 尽管已经示出和描述了本发明的实施例,本领域的普通技术人员可以理解:在不脱离本发明的原理和宗旨的情况下可以对这些实施例进行多种变化、修改、替换和变型,本发明的范围由权利要求及其等同物限定。 [0078] While there has been illustrated and described embodiments of the present invention, those of ordinary skill in the art can be appreciated: that various changes may be made to these embodiments without departing from the principles and spirit of the invention, modifications, substitutions and modifications, the scope of the present invention is defined by the claims and their equivalents.

Claims (13)

  1. 1.一种改善扩散区域形貌的功率器件,其特征在于,包括: 衬底及其上形成的外延层,所述外延层的掺杂类型与所述衬底的掺杂类型相同; 在所述外延层内形成有埋层,所述埋层的上表面与外延层的上表面位于同一平面,所述埋层的掺杂类型与所述外延层的掺杂类型相反; 在所述埋层内形成有源区,所述源区的上表面与所述外延层的上表面位于同一平面,所述源区的掺杂类型与所述外延层的掺杂类型相同; 在所述外延层内形成有预扩散区,所述预扩散区与所述埋层连接,且所述预扩散区的上表面与所述外延层的上表面位于同一平面,所述预扩散区的掺杂类型与所述埋层的掺杂类型相同; 在所述外延层的上表面上形成有栅介质层和栅极,所述栅介质层和栅极覆盖在埋层及所述源区的一部分之上; 在所述栅极和外延层之上形成有介质层和正面金属层 1. A method of improving diffusion region morphology power device, characterized by comprising: a substrate and an epitaxial layer formed thereon, the doping type of the substrate with the same doping type epitaxial layer; in the said buried layer is formed, the upper surface of the upper surface of the epitaxial layer and the buried layer located on the same plane, and the buried layer of the opposite doping type and doping type of the epitaxial layer within the epitaxial layer; said buried layer the active region is formed, the upper surface of the source region and the upper surface of the epitaxial layer in the same plane, the doping type source region and the doping type of the epitaxial layer is the same; the epitaxial layer pre-diffusion region is formed, the pre-diffusion region and the buried layer is connected, and the upper surface of the pre-surface of the epitaxial layer, the diffusion region located in the same plane, the pre-doping type diffused region same doping type as said buried layer; forming a gate dielectric layer and a gate on an upper surface of the epitaxial layer, the gate dielectric layer and a gate electrode overlying a portion of the buried layer, and said source region; in the gate and the epitaxial layer is formed on the front side with a dielectric layer and a metal layer 在所述衬底之下形成有背面扩散区;以及在所述背面扩散区之下形成有背面金属层。 Diffusion regions formed beneath the back surface of said substrate; and forming a back surface of the back surface of the metal layer under the diffusion region.
  2. 2.如权利要求1所述的改善扩散区域形貌的功率器件,其特征在于,所述埋层内包括有与所述源区相连的导电沟道区和注入扩散区,所述导电沟道区位于源区与所述预扩散区之间且导电沟道区的上表面与所述外延层的上表面位于同一平面,所述注入扩散区位于源区的下方,所述导电沟道区与所述注入扩散区的掺杂类型与所述埋层的掺杂类型相同。 2. The improved morphology diffusion region of the power device as claimed in claim 1, wherein said inner layer comprises a conductive buried channel region and the implanted source diffusion region and the region connected to the conductive channel region located in the source region and the upper surface of the conductive and pre-channel region located in the same plane with the upper surface of the epitaxial layer between the diffusion region, the diffusion region below the implantation of the source region, the channel region and the conductive the same implantation doping type doping type diffusion region and said buried layer.
  3. 3.如权利要求2所述的改善扩散区域形貌的功率器件,其特征在于,所述导电沟道区与所述预扩散区相连。 Diffusion region to improve the morphology of the power device as claimed in claim 2, wherein said conductive channel region connected to the pre-diffusion region.
  4. 4.如权利要求2所述的改善扩散区域形貌的功率器件,其特征在于,所述导电沟道区的深度小于所述注入扩散区和源区的深度之和。 Diffusion region 4. To improve the morphology of the power device as claimed in claim 2, wherein a depth of the conduction channel region is less than the injection region and the source diffusion region and the depth.
  5. 5.如权利要求2所述的改善扩散区域形貌的功率器件,其特征在于,所述导电沟道区为轻掺杂,所述注入扩散区为重掺杂。 The improved diffusion region of the power device topography as claimed in claim 2, wherein the conductive channel region is lightly doped, the diffusion region is heavily doped implanted.
  6. 6.如权利要求1-5任意一项所述的改善扩散区域形貌的功率器件,其特征在于,所述预扩散区沿外延层深度方向的宽度逐渐变小。 1-5 improve the diffusion region 6. The morphology of the power device of any one of the preceding claims, characterized in that the pre-diffusion region becomes gradually smaller in the width direction of the depth of the epitaxial layer.
  7. 7.如权利要求6所述的改善扩散区域形貌的功率器件,其特征在于,所述预扩散区沿外延层深度的剖面为锲形。 7. To improve diffusion region topography of the power device as claimed in claim 6, wherein the pre-epitaxial diffusion region along the cross-sectional depth of wedge.
  8. 8.如权利要求6所述的改善扩散区域形貌的功率器件,其特征在于,所述预扩散区的深度为0-5000A,所述预扩散区的浓度为E10-E13。 Diffusion region to improve the morphology of the power device as claimed in claim 6, wherein the depth of said diffusion region is pre-0-5000A, the pre-concentration diffusion region of E10-E13.
  9. 9.如权利要求1所述的改善扩散区域形貌的功率器件,其特征在于,所述介质层包括二氧化硅层和硼磷硅玻璃层。 Diffusion region to improve the morphology of the power device as claimed in claim 1, wherein said dielectric layer comprises silicon dioxide layer and a layer of borophosphosilicate glass.
  10. 10.一种改善扩散区域形貌的功率器件的制造方法,其特征在于,包括如下步骤: S1:提供衬底并在所述衬底上形成外延层,所述外延层的掺杂类型与所述衬底的掺杂类型相同; S2:在所述外延层之上形成栅介质层和栅极; S3:所述外延层内形成预扩散区和埋层,所述埋层的掺杂类型与所述外延层的掺杂类型相反,所述预扩散区的掺杂类型与所述埋层的掺杂类型相同,其中,所述预扩散区位于所述外延层和所述埋层之间且位于栅介质层之下,所述预扩散区的上表面与所述外延层的上表面位于同一平面,所述埋层的上表面与外延层的上表面位于同一平面; S4:在所述埋层内形成有源区,所述源区的掺杂类型与所述外延层的掺杂类型相同,其中,所述源区的上表面与所述外延层的上表面位于同一平面; S5:在所述栅极和源区之上形成介质层,并在所述介质层之上 10. A method for manufacturing a diffusion region of a power device to improve morphology, characterized by comprising the steps of: S1: providing a substrate and forming an epitaxial layer on the substrate, the type of doping of the epitaxial layer and same doping type as said substrate; S2: forming a gate dielectric layer and a gate on the epitaxial layer; S3: the pre-formed buried layer diffusion region and the epitaxial layer, the doping type buried layer the epitaxial layer of the opposite doping type, the pre-doping type and the same doping type as the buried diffusion region, wherein the pre-positioned between said diffusion region and said epitaxial layer and buried layer gate dielectric layer located below the upper surface of the pre-diffused region of the upper surface of the epitaxial layer in the same plane, the upper surfaces of said epitaxial layer, the buried layer is located in the same plane; S4: buried in the layer formed in the active region, the source region doping type and doping type of the epitaxial layer is the same, wherein an upper surface of the source region and the upper surface of the epitaxial layer in the same plane; S5: in the gate and the source region is formed over the dielectric layer, and over the dielectric layer 成正面金属层,所述正面金属层通过所述接触孔与所述源区相连; 56:在所述衬底之下形成背面扩散区,所述背面扩散区为重掺杂; 57:在所述背面扩散区之下形成有背面金属层。 A metal layer to the front, the front metal layer through the contact hole is connected with the source regions; 56: back surface of the diffusion region is formed beneath the substrate, the back surface of the diffusion region is heavily doped; 57: in the under the back surface of said back surface metal layer are formed diffusion regions.
  11. 11.如权利要求10所述的改善扩散区域形貌的功率器件的制造方法,其特征在于,所述步骤S3具体包括以下步骤: S31:在栅介质层之下的外延层内形成预扩散区; S51:在外延层内形成埋层。 Manufacturing method for improving the morphology of the diffusion region 11. The power device as claimed in claim 10, wherein said step S3 comprises the following steps: S31: forming a pre-diffusion regions in the epitaxial layer beneath the gate dielectric layer ; S51: buried layer formed in the epitaxial layer.
  12. 12.如权利要求10所述的改善扩散区域形貌的功率器件的制造方法,其特征在于,所述步骤S3具体包括以下步骤: S51:在外延层内形成埋层; S31:在栅介质层之下的外延层内形成预扩散区。 A method for producing improved morphology diffusion region 12. The power device as claimed in claim 10, wherein said step S3 comprises the following steps: S51: a buried layer formed in the epitaxial layer; S31: the gate dielectric layer diffusion regions formed under the pre-epitaxial layer.
  13. 13.如权利要求11或12所述的改善扩散区域形貌的功率器件的制造方法,其特征在于,当所述埋层包括导电沟道区和注入扩散区时,所述步骤S51具体包括以下步骤: 在所述外延层内形成埋层的区域全部进行轻掺杂; 在所述埋层的注入扩散区进行重掺杂。 The method of manufacturing a power device topography improved diffusion regions 11 or 12 as claimed in claim 13, wherein, when the conduction channel region comprises a buried layer and a diffusion region implantation, the step S51 comprises the following steps of: forming a buried layer region within the lightly doped epitaxial layer for all; in the heavily doped buried layer diffusion region implantation.
CN 201210438533 2012-11-06 2012-11-06 A power device and a method of improving diffusion region topography CN103811545B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 201210438533 CN103811545B (en) 2012-11-06 2012-11-06 A power device and a method of improving diffusion region topography

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN 201210438533 CN103811545B (en) 2012-11-06 2012-11-06 A power device and a method of improving diffusion region topography

Publications (2)

Publication Number Publication Date
CN103811545A true true CN103811545A (en) 2014-05-21
CN103811545B CN103811545B (en) 2017-09-29

Family

ID=50708051

Family Applications (1)

Application Number Title Priority Date Filing Date
CN 201210438533 CN103811545B (en) 2012-11-06 2012-11-06 A power device and a method of improving diffusion region topography

Country Status (1)

Country Link
CN (1) CN103811545B (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5728593A (en) * 1994-12-29 1998-03-17 Samsung Electronics Co., Ltd. Power insulated-gate transistor having three terminals and a manufacturing method thereof
US6420225B1 (en) * 1999-04-01 2002-07-16 Apd Semiconductor, Inc. Method of fabricating power rectifier device
CN102487050A (en) * 2010-12-03 2012-06-06 比亚迪股份有限公司 Power semiconductor device and method for manufacturing the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5728593A (en) * 1994-12-29 1998-03-17 Samsung Electronics Co., Ltd. Power insulated-gate transistor having three terminals and a manufacturing method thereof
US6420225B1 (en) * 1999-04-01 2002-07-16 Apd Semiconductor, Inc. Method of fabricating power rectifier device
CN102487050A (en) * 2010-12-03 2012-06-06 比亚迪股份有限公司 Power semiconductor device and method for manufacturing the same

Also Published As

Publication number Publication date Type
CN103811545B (en) 2017-09-29 grant

Similar Documents

Publication Publication Date Title
CN102800591A (en) Preparation method for FS-IGBT device
CN102117827A (en) Parasitic vertical PNP device in bipolar complementary metal oxide semiconductor (BiCMOS) process
CN101499422A (en) Production method for inner transparent collecting electrode IGBT with polysilicon as service life control layer
CN101488526A (en) N type SOI lateral double-diffused metal-oxide semiconductor transistor
CN102034707A (en) Method for manufacturing IGBT
CN102088029A (en) PNP bipolar transistor in SiGe BiCMOS technology
CN102044563A (en) LDMOS (laterally diffused metal oxide semiconductor) device and manufacturing method thereof
CN101969072A (en) Consumption type N-type lateral double-diffusion metal-oxide semiconductor for reducing voltage
CN102194885A (en) N-type buried-channel silicon carbide metal oxide semiconductor field effect transistor (DEMOSFET) device and preparation method thereof
CN101452967A (en) Schottky barrier diode device and manufacturing method thereof
CN102044560A (en) Ultrahigh frequency silicon and germanium heterojunction bipolar transistor
CN102931090A (en) Manufacturing method for super junction metal oxide semiconductor field effect transistor (MOSFET)
US20110012132A1 (en) Semiconductor Device
CN202042487U (en) Semiconductor device with super-junction structure
JP2014075582A (en) Semiconductor device and method of manufacturing semiconductor device
CN102097465A (en) Parasitic vertical PNP triode in BiCMOS process and manufacturing method thereof
CN103035727A (en) Radio frequency (RF) laterally diffused metal oxide semiconductor (LDMOS) component and manufacture method
CN102184963A (en) LDMOS (Laterally Diffused Metal Oxide Semiconductor) device with transverse composite buffer layer structure
CN101488525A (en) P type SOI lateral double-diffused metal-oxide semiconductor transistor
CN103178087A (en) Ultra-high voltage LDMOS (Laterally Diffused Metal Oxide Semiconductor) device structure and production method thereof
CN101924138A (en) MOS (Metal Oxide Semiconductor) device structure for preventing floating-body effect and self-heating effect and preparation method thereof
CN101515547A (en) Method for manufacturing hyperconjugation VDMOS device
CN103199018A (en) Manufacturing method of field blocking type semiconductor device and device structure
CN103050532A (en) RF LDMOS (ratio frequency laterally diffused metal oxide semiconductor) device and manufacture method of RF LDMOS device
CN102110709A (en) Parasitic vertical PNP triode in bipolar complementary metal oxide semiconductor (BiCMOS) process and manufacturing method thereof

Legal Events

Date Code Title Description
C06 Publication
C10 Entry into substantive examination
GR01