CN104716178A - LDMOS device with deep hole and manufacturing method of LDMOS device - Google Patents
LDMOS device with deep hole and manufacturing method of LDMOS device Download PDFInfo
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- CN104716178A CN104716178A CN201310675661.XA CN201310675661A CN104716178A CN 104716178 A CN104716178 A CN 104716178A CN 201310675661 A CN201310675661 A CN 201310675661A CN 104716178 A CN104716178 A CN 104716178A
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Abstract
The invention discloses an LDMOS device with a deep hole. A drift region is arranged in a silicon substrate or an epitaxial layer, and a body region is arranged in the drift region. A filling structure is arranged in the drift region. A gate oxide layer is arranged on all silicon materials. A polycrystalline silicon gate is arranged on part of the gate oxide layer. The filling structure is made of a monocrystal silicon material, is vertical, and is vertically divided into two parts, the top of the first part makes contact with the bottom of the gate oxide layer, and the side wall of the first part is surrounded by the drift region. The side wall and the bottom of the second part are surrounded by the silicon substrate or the epitaxial layer. The polycrystalline silicon gate is horizontally divided into two parts, the first part is spaced from the gate oxide layer and located over part of the body region, and the second part is spaced from the gate oxide layer and located over part of the drift region. The second part of the polycrystalline silicon gate is spaced from the gate oxide layer and located over part of the filling structure or the whole filling structure. By the adoption of the LDMOS device, breakdown voltages can be increased, and meanwhile on resistance is reduced.
Description
Technical field
The application relates to a kind of semiconductor device, particularly relates to a kind of LDMOS(laterally diffused MOS transistor) device.
Background technology
Refer to Fig. 1, this is a kind of cross-sectional view of existing LDMOS device.In p-type silicon substrate (or epitaxial loayer) 100, have N-shaped drift region 101 and p-type body district 102, both sides can contact with each other, and also can not contact.There is isolation structure 103 and N-shaped drain electrode 107 that side contacts with each other in drift region 101.Isolation structure 103 is the dielectric materials such as such as silica, adopts selective oxidation (LOCOS) or shallow-trench isolation (STI) manufacture technics.In tagma 102, have N-shaped source electrode 106 and draw-out area, p-type body district 108, both sides can contact with each other, and also can not contact.Gate oxide 104 is had on silicon materials (comprising silicon substrate 100, drift region 101, tagma 102, source electrode 106, drain electrode 107, draw-out area, tagma 108) except isolation structure 103.On the isolation structure 103 of part and the gate oxide 104 of part, there is polysilicon gate 105.This polysilicon gate 105 can be divided into three parts in the horizontal direction, Part I is separated by gate oxide 104 directly over part tagma 102, Part II is separated by gate oxide 104 directly over part drift region 101, and Part III is separated by isolation structure 103 directly over part drift region 101.The doping type of the Each part of above-mentioned LDMOS device becomes on the contrary, is also feasible.
The structure of the LDMOS device shown in Fig. 1 can be deformed into shown in Fig. 1 a, and difference is only that N-shaped drift region 101 does not contact with the side in p-type body district 102, and centre has p-type silicon substrate (or epitaxial loayer) 100 to isolate.
In above-mentioned LDMOS device, if the side in N-shaped drift region 101 and p-type body district 102 contacts, then the PN junction that both are formed operationally bears the high pressure between source, leakage.If N-shaped drift region 101 does not contact with the side in p-type body district 102, then the PIN structural formed together with the silicon substrate (or epitaxial loayer) 100 of centre both operationally bears the high pressure between source, leakage.
Refer to Fig. 4 and Fig. 5, they show respectively the Electric Field Distribution of device architecture shown in Fig. 1 and Fig. 1 a.In the diagram, electric field distribution triangular in shape, the electric field strength highest point of depletion region is positioned at gate oxide 104 and drift region 101 intersection.In Figure 5, electric field is distribution triangular in shape also, and the electric field strength highest point of depletion region is positioned at three's intersection of gate oxide 104, silicon substrate (or epitaxial loayer) 100, drift region 101.When intersection electric field reaches the avalanche breakdown critical electric field of silicon materials, device starts avalanche breakdown occurs, and now in whole depletion region, carries out the puncture voltage that integration just obtains device to electric field, Fig. 4 and Fig. 5 equals leg-of-mutton area.
For LDMOS device, high puncture voltage requires thick light dope epitaxial loayer, long drift region, low-doped drift region, and low conducting resistance then requires thin heavy doping epitaxial loayer, short drift region, highly doped drift region.Obviously, the low on-resistance of LDMOS device and high-breakdown-voltage are the technical indicators of a pair needs balance.In order to improve device withstand voltage, the doping content reducing drift region can be selected, and this can bring adverse effect to conducting resistance.
Summary of the invention
Technical problems to be solved in this application are to provide a kind of LDMOS device with deep hole, can obtain higher puncture voltage on the one hand, can obtain lower conducting resistance on the other hand, thus improve the performance of device.
For solving the problems of the technologies described above, the LDMOS device that the application has a deep hole has the drift region of the second doping type in the silicon substrate or epitaxial loayer of the first doping type, has the tagma of the first doping type in drift region; In silicon substrate or epitaxial loayer and drift region, there is interstitital texture; There is gate oxide on all silicon materials, on the gate oxide of part, there is polysilicon gate;
Described interstitital texture is the single crystal silicon material of the first doping type, and in vertical shape, in the vertical direction is divided into two parts; The top of Part I and the bottom connection of gate oxide touch, the sidewall of Part I surround by drift region; The sidewall of Part II and bottom all by silicon substrate or epitaxial loayer surround;
Described polysilicon gate is divided into two parts in the horizontal direction; Part I is separated by gate oxide directly over part tagma, and Part II is separated by gate oxide directly over part drift region; The Part II of polysilicon gate is also separated by gate oxide directly over part or all of interstitital texture.
The manufacture method that the application has the LDMOS device of deep hole comprises the steps:
1st step, injects the impurity of the second doping type in the silicon substrate or epitaxial loayer of the first doping type, forms drift region;
2nd step, adopt photoetching and etching technics in drift region, etch multiple groove or hole, the bottom in these grooves or hole is passed through drift region and drops in silicon substrate or epitaxial loayer;
3rd step, in groove or hole, adopt selective epitaxial process to grow the monocrystalline silicon of the first doping type by trench fill completely, the monocrystalline silicon in these grooves is exactly interstitital texture;
4th step, injects the impurity of the first doping type in drift region, forms tagma;
5th step, adopts thermal oxide growth technique to grow gate oxide on all silicon materials surfaces;
6th step, first at whole wafer deposition one deck polysilicon, then adopts photoetching and etching technics to etch to form polysilicon gate to this layer of polysilicon;
7th step, adopts photoetching and ion implantation technology in drift region and tagma, inject the impurity of the second doping type simultaneously, forms drain electrode and the source electrode of the second doping type respectively; Photoetching and ion implantation technology is adopted in tagma, also to inject the impurity of the first doping type to form draw-out area, tagma.
The LDMOS device of the application introduces deep trench or deep hole in drift region, the monocrystalline silicon of the first doping type is filled in deep trench or deep hole, the drift region that these monocrystalline silicon interstitital textures are deep into the second doping type is inner, thus introduces extra electric field in the inside of drift region.The extra electric field introduced can make drift region fully exhaust, and is conducive to the puncture voltage improving LDMOS device.Therefore, the doping content of drift region can be improved, while reduction puncture voltage, improve conducting resistance, obtain both balances, finally improve device performance.
Accompanying drawing explanation
Fig. 1 is a kind of cross-sectional view of existing LDMOS device;
Fig. 1 a is the one distortion of Fig. 1;
Fig. 2 is the cross-sectional view with the LDMOS device of deep hole of the application;
Fig. 2 a is the one distortion of Fig. 2;
Fig. 3 a ~ Fig. 3 f is each step generalized section with the manufacture method of the LDMOS device of deep hole of the application;
Fig. 4 is the Electric Field Distribution schematic diagram of device architecture shown in Fig. 1;
Fig. 5 is the Electric Field Distribution schematic diagram of device architecture shown in Fig. 1 a;
Fig. 6 is the Electric Field Distribution schematic diagram of device architecture shown in Fig. 2.
Description of reference numerals in figure:
100 is silicon substrate or epitaxial loayer; 101 is drift region; 102 is tagma; 103 is isolation structure; 104 is gate oxide; 105 is grid; 106 is source electrode; 107 is drain electrode; 108 is draw-out area, tagma; 200 is groove or hole; 201 is interstitital texture.
Embodiment
Refer to Fig. 2, this is the cross-sectional view with the LDMOS device of deep hole of the application.In p-type silicon substrate (or epitaxial loayer) 100, there is N-shaped drift region 101.There is p-type body district 102 in drift region 101.In silicon substrate 100 and drift region 101, there is interstitital texture 201.Interstitital texture 201, in vertical column (if in hole) or vertical wall shape (if in the trench), is the single crystal silicon material of p-type doping.Interstitital texture 201 in the vertical direction can be divided into two parts, and the top of Part I and the bottom connection of gate oxide 104 touch, the sidewall of Part I surround by drift region 101, the bottom of Part I is connected with the top of Part II; The sidewall of Part II and bottom all surround by silicon substrate 100.There is N-shaped drain region 107 in drift region 101.All interstitital textures 201 all do not contact with tagma 102, also all do not contact with drain region 107.In tagma 102, have N-shaped source region 106 and draw-out area, p-type body district 108, both sides can contact with each other, and also can not contact.All silicon materials have gate oxide 104 on (comprising silicon substrate 100, drift region 101, tagma 102, source electrode 106, drain electrode 107, draw-out area, tagma 108, interstitital texture 201).On the gate oxide 104 of part, there is polysilicon gate 105.This polysilicon gate 105 can be divided into two parts in the horizontal direction, Part I is separated by gate oxide 104 directly over part tagma 102, Part II is separated by gate oxide 104 directly over part drift region 101, and Part I is connected in the horizontal direction with Part II.The Part II of polysilicon gate 105 is also separated by gate oxide 104 and directly over part or all of interstitital texture 201.The doping type of the Each part of above-mentioned LDMOS device becomes on the contrary, is also feasible.
The structure of the LDMOS device shown in Fig. 2 can be deformed into shown in Fig. 2 a, and difference is only that N-shaped drift region 101 no longer surrounds p-type body district 102, but adjacent with p-type body district 102.Both sides can contact with each other, also can not contact and by centre have p-type silicon substrate (or epitaxial loayer) 100 isolate.
Compared with existing LDMOS device, the application eliminates isolation structure, has increased the interstitital texture of p-type monocrystalline silicon newly.Described interstitital texture runs through drift region and is deep into the inside of silicon substrate, and the extra electric field between itself and N-shaped drift region can make drift region fully exhaust, and is conducive to bearing high pressure.Since the LDMOS device this with deep hole can obtain higher puncture voltage, so just suitably can improve the doping content of drift region, although can puncture voltage be reduced like this, but still higher than the puncture voltage of existing LDMOS device, and the conducting resistance lower than existing LDMOS device can be obtained.
Refer to Fig. 6, it illustrates the Electric Field Distribution of device architecture shown in Fig. 2.In fig. 2, because the monocrystalline silicon interstitital texture 201 in deep hole is p-type doping, p-type impurity wherein can form depletion region in N-shaped drift region 101, and drift region 101 just can be made all to exhaust under lower than silicon materials avalanche critical field.When maximum electric field in depletion region is close to avalanche critical field, the voltage uniform between drain electrode 107 to tagma 104 is distributed in the drift region 101 on the right side of tagma 102, and depleted region electric field is trapezoidal profile.Under the condition that doping content is close, the area of whole trapezoid area much larger than the area of traditional structure intermediate cam shape, namely will can reach higher device electric breakdown strength under the condition of identical doping content.Shown in Fig. 2 a, the Electric Field Distribution of device is identical with it.
The manufacture method with the LDMOS device of deep hole of the application comprises the steps:
1st step, refers to Fig. 3 a, implant n-type impurity in p-type silicon substrate (or epitaxial loayer) 100, forms N-shaped drift region 101.
2nd step, refers to Fig. 3 b, adopts photoetching and etching technics to etch in drift region 101 and forms multiple groove 200.The bottom of these grooves 200 is passed through drift region 101 and drops in silicon substrate 100.These grooves 200 also can change hole into.
3rd step, refers to Fig. 3 c, and groove 200 is filled full by the monocrystalline silicon adopting selective epitaxial process to grow p-type doping in groove 200, and the monocrystalline silicon in these grooves 200 is exactly interstitital texture 201.Owing to being from p-type silicon substrate upwards epitaxially grown monocrystalline silicon, thus grown monocrystalline silicon is also p-type doping.
Described selective epitaxial process first grows mask layer (silicon dioxide or silicon nitride) at silicon chip surface exactly, then on mask layer, open with photoetching and etching technics the surface that window exposes silicon materials, last only at the silicon materials come out epitaxial growth monocrystalline silicon on the surface, at other by mask layer overlay area then not growing single-crystal silicon.
4th step, refers to Fig. 3 d, implanted with p-type impurity in N-shaped drift region 101, forms p-type body district 102.This p-type body district 102 is as the channel region of LDMOS device.
The order of above-mentioned 2nd ~ 3 steps, the 4th step can be exchanged.
5th step, refers to Fig. 3 e, adopts thermal oxide growth technique to grow gate oxide 104 on whole silicon chip (comprising silicon substrate 100, drift region 101, interstitital texture 201, tagma 102) surface.
6th step, refers to Fig. 3 f, first at whole wafer deposition one deck polysilicon, then adopts photoetching and etching technics to etch to form polysilicon gate 105 to this layer of polysilicon.This polysilicon gate 105 is divided into two parts in the horizontal direction, and Part I is separated by gate oxide 104 directly over part tagma 102, and Part II is separated by gate oxide 104 directly over part drift region 101.The Part II of polysilicon gate 105 is also separated by gate oxide 104 and covering directly over part or all of interstitital texture 201.
7th step, refers to Fig. 2, and implant n-type impurity while of adopting photoetching and ion implantation technology in drift region 101 and tagma 102, forms N-shaped drain electrode 107 and N-shaped source electrode 106 respectively in drift region 101 and tagma 102.Photoetching and ion implantation technology is adopted in tagma 102, to go back implanted with p-type impurity to form draw-out area, p-type body district 108.
If change drift region 101 and tagma 102 into adjacent structure, so described method the 4th step changes into: implanted with p-type impurity in p-type silicon substrate 100, forms p-type body district 102.This p-type body district 102 is as the channel region of LDMOS device.
This p-type body district 102 can contact with each other with the side of N-shaped drift region 101, thus forms a PN junction.
Or this p-type body district 102 also can not contact with the side of N-shaped drift region 101, because the doping content in p-type body district is much larger than p-type silicon substrate, thus this p-type body district 102 and N-shaped drift region 101 form PIN structural together with the p-type silicon substrate 100 of centre.
These are only the preferred embodiment of the application, and be not used in restriction the application.For a person skilled in the art, the application can have various modifications and variations.Within all spirit in the application and principle, any amendment done, equivalent replacement, improvement etc., within the protection range that all should be included in the application.
Claims (6)
1. there is a LDMOS device for deep hole, there is the drift region of the second doping type in the silicon substrate or epitaxial loayer of the first doping type, it is characterized in that, there is the tagma of the first doping type in drift region; In silicon substrate or epitaxial loayer and drift region, there is interstitital texture; There is gate oxide on all silicon materials, on the gate oxide of part, there is polysilicon gate;
Described interstitital texture is the single crystal silicon material of the first doping type, and in vertical shape, in the vertical direction is divided into two parts; The top of Part I and the bottom connection of gate oxide touch, the sidewall of Part I surround by drift region; The sidewall of Part II and bottom all by silicon substrate or epitaxial loayer surround;
Described polysilicon gate is divided into two parts in the horizontal direction; Part I is separated by gate oxide directly over part tagma, and Part II is separated by gate oxide directly over part drift region; The Part II of polysilicon gate is also separated by gate oxide directly over part or all of interstitital texture.
2. the LDMOS device with deep hole according to claim 1, is characterized in that, drift region changes into and do not surround tagma, but adjacent with tagma.
3. there is a manufacture method for the LDMOS device of deep hole, it is characterized in that, comprise the steps:
1st step, injects the impurity of the second doping type in the silicon substrate or epitaxial loayer of the first doping type, forms drift region;
2nd step, adopt photoetching and etching technics in drift region, etch multiple groove or hole, the bottom in these grooves or hole is passed through drift region and drops in silicon substrate or epitaxial loayer;
3rd step, in groove or hole, adopt selective epitaxial process to grow the monocrystalline silicon of the first doping type by trench fill completely, the monocrystalline silicon in these grooves is exactly interstitital texture;
4th step, injects the impurity of the first doping type in drift region, forms tagma;
5th step, adopts thermal oxide growth technique to grow gate oxide on all silicon materials surfaces;
6th step, first at whole wafer deposition one deck polysilicon, then adopts photoetching and etching technics to etch to form polysilicon gate to this layer of polysilicon;
7th step, adopts photoetching and ion implantation technology in drift region and tagma, inject the impurity of the second doping type simultaneously, forms drain electrode and the source electrode of the second doping type respectively; Photoetching and ion implantation technology is adopted in tagma, also to inject the impurity of the first doping type to form draw-out area, tagma.
4. the manufacture method with the LDMOS device of deep hole according to claim 3, is characterized in that, described method the 4th step changes into, injects the impurity of the first doping type in silicon substrate or epitaxial loayer, forms the tagma adjacent with drift region.
5. the manufacture method with the LDMOS device of deep hole according to claim 3 or 4, is characterized in that, the order of described method 2nd ~ 3 step, the 4th step is exchanged.
6. the manufacture method with the LDMOS device of deep hole according to claim 3, is characterized in that, in described method the 7th step, the order of N-shaped ion implantation, p-type ion implantation is exchanged.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107248495A (en) * | 2017-06-20 | 2017-10-13 | 上海华力微电子有限公司 | A kind of method that high-aspect-ratio isolation is formed in energetic ion injection technology |
| CN108682691A (en) * | 2018-05-25 | 2018-10-19 | 矽力杰半导体技术(杭州)有限公司 | The manufacturing method and semiconductor devices of transverse diffusion metal oxide semiconductor device |
| CN114695511A (en) * | 2020-12-30 | 2022-07-01 | 无锡华润上华科技有限公司 | Lateral diffusion metal oxide semiconductor device and manufacturing method thereof |
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| US20030193067A1 (en) * | 2001-04-16 | 2003-10-16 | Min-Hwan Kim | High voltage lateral DMOS transistor having low on-resistance and high breakdown voltage |
| US20040222461A1 (en) * | 2000-06-09 | 2004-11-11 | Andre Peyre-Lavigne | Lateral semiconductor device with low on-resistance and method of making the same |
| CN1947259A (en) * | 2004-04-30 | 2007-04-11 | 飞思卡尔半导体公司 | High current MOS device with avalanche protection and method of operation |
| DE102005046007A1 (en) * | 2005-09-26 | 2007-04-12 | Infineon Technologies Ag | Lateral compensation semiconductor component for use as high voltage transistor, has coupling layers for connection of compensation cells with each other, where layers are of p-type conduction and are in connection with source region |
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| US20040222461A1 (en) * | 2000-06-09 | 2004-11-11 | Andre Peyre-Lavigne | Lateral semiconductor device with low on-resistance and method of making the same |
| US20030193067A1 (en) * | 2001-04-16 | 2003-10-16 | Min-Hwan Kim | High voltage lateral DMOS transistor having low on-resistance and high breakdown voltage |
| CN1947259A (en) * | 2004-04-30 | 2007-04-11 | 飞思卡尔半导体公司 | High current MOS device with avalanche protection and method of operation |
| DE102005046007A1 (en) * | 2005-09-26 | 2007-04-12 | Infineon Technologies Ag | Lateral compensation semiconductor component for use as high voltage transistor, has coupling layers for connection of compensation cells with each other, where layers are of p-type conduction and are in connection with source region |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107248495A (en) * | 2017-06-20 | 2017-10-13 | 上海华力微电子有限公司 | A kind of method that high-aspect-ratio isolation is formed in energetic ion injection technology |
| CN107248495B (en) * | 2017-06-20 | 2020-01-24 | 上海华力微电子有限公司 | Method for forming high aspect ratio isolation in high-energy ion implantation process |
| CN108682691A (en) * | 2018-05-25 | 2018-10-19 | 矽力杰半导体技术(杭州)有限公司 | The manufacturing method and semiconductor devices of transverse diffusion metal oxide semiconductor device |
| CN114695511A (en) * | 2020-12-30 | 2022-07-01 | 无锡华润上华科技有限公司 | Lateral diffusion metal oxide semiconductor device and manufacturing method thereof |
| CN114695511B (en) * | 2020-12-30 | 2023-11-24 | 无锡华润上华科技有限公司 | Lateral diffusion metal oxide semiconductor device and manufacturing method thereof |
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Application publication date: 20150617 |