CN107248495B - Method for forming high aspect ratio isolation in high-energy ion implantation process - Google Patents
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- 238000002955 isolation Methods 0.000 title claims abstract description 38
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- 239000010410 layer Substances 0.000 claims abstract description 117
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
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Abstract
The invention provides a method for forming high aspect ratio isolation in a high-energy ion implantation process, which comprises the following steps: the method comprises the following steps: preparing a silicon substrate, and sequentially arranging a silicon substrate epitaxial layer, a grinding stop layer and a mask pattern layer from bottom to top above the silicon substrate; step two: etching a silicon groove with a high depth-to-width ratio on the structure, wherein the bottom of the groove is positioned on the silicon substrate and is close to the epitaxial layer of the silicon substrate; step three: selectively epitaxially growing a single-layer or multi-layer monocrystalline silicon on the outer side of the structure, wherein the monocrystalline silicon fills the whole groove; step four: and chemically and mechanically grinding the epitaxial growth monocrystalline silicon above the groove, stopping on the grinding stop layer, and finally removing the residual grinding stop layer. The invention can overcome the depth limit of the high-energy ion implantation process and the CD or depth-to-width ratio limit of photoetching, and can solve the technical problem that the photodiode pixel unit of a CMOS image sensor product is pushed to be smaller in size and deeper.
Description
Technical Field
The present invention relates to the field of semiconductor integrated circuit fabrication, and more particularly, to a method for forming high aspect ratio isolation in a high energy ion implantation process.
Background
Fig. 1a and 1b are process flow diagrams of conventional ion implantation isolation, in which a substrate epitaxial layer 31 and an implantation sacrificial layer 11 are disposed on a silicon substrate 10 in fig. 1a, a mask pattern layer 21 is disposed on the implantation sacrificial layer 11 at intervals, the structure shown in fig. 1a is subjected to ion implantation to form the structure shown in fig. 1b, and the substrate epitaxial layer 31 and the implantation layer 32 are disposed on the silicon substrate 10 at intervals. However, in some high-energy implantation isolation processes, the line width (space) has been required to be 0.15um, the photoresist height reaches 4um thickness, and the aspect ratio has been larger than 20, which has exceeded the limit of the conventional photolithography process; under the process requirement of the high aspect ratio, a tri-layer technology is generally adopted, and the pattern of the photoresist is transferred to the lower injection barrier layer by utilizing the selection ratio change of the photoresist, the hard mask layer and the injection barrier layer in etching. However, when the ratio of the thickness of the implant block to the critical dimension is too large, a taper or bowling ball topography is likely to occur. If the injection blocking layer is too thick, the hard mask layer is easy to have the problem of edge over-etching, so that the injection blocking layer has a burr phenomenon at the edge of the graph; while the limits of high energy implanters have limited some deep well applications such as deep well isolation of CMOS image sensor photodiodes.
Disclosure of Invention
The invention provides a method for forming high aspect ratio isolation in a high-energy ion implantation process, which can overcome the depth limit of the high-energy ion implantation process and the CD or aspect ratio limit of photoetching and solve the technical problem that a photodiode pixel unit of a CMOS (complementary metal oxide semiconductor) image sensor product is pushed to be smaller in size and deeper.
In order to achieve the above object, the present invention provides a method for forming high aspect ratio isolation in a high-energy ion implantation process, comprising the following steps:
the method comprises the following steps: preparing a silicon substrate, and sequentially arranging a silicon substrate epitaxial layer, a grinding stop layer and a mask pattern layer from bottom to top above the silicon substrate;
step two: etching a silicon groove with a high depth-to-width ratio on the structure, wherein the bottom of the groove is positioned on the silicon substrate and is close to the epitaxial layer of the silicon substrate;
step three: selectively epitaxially growing a single-layer or multi-layer monocrystalline silicon on the outer side of the structure, wherein the monocrystalline silicon fills the whole groove;
step four: and chemically and mechanically grinding the epitaxial growth monocrystalline silicon above the groove, stopping on the grinding stop layer, and finally removing the residual grinding stop layer.
Further, the polishing stop layer is silicon dioxide or silicon nitride.
Further, the mask pattern layer is a photoresist for one exposure.
Furthermore, the mask pattern layer is a pattern formed by one-time exposure and etching, and the film quality is an oxide film or a nitride film.
Further, the depth-to-width ratio of the etched groove is greater than 10: 1.
furthermore, the etching depth of the groove is 1-2 um larger than the thickness of the silicon substrate epitaxial layer, and the bottom of the groove is formed below the silicon substrate epitaxial layer.
Further, the single-layer monocrystalline silicon and the silicon substrate epitaxial layers are different in doping type.
Furthermore, the doping types of the first layer of the multilayer monocrystalline silicon and the epitaxial layer of the silicon substrate are the same, and the critical dimension of the groove after the epitaxy is finished is consistent with the target dimension.
Furthermore, in the fourth step, the monocrystalline silicon does not fill the whole trench, a gap is reserved in the trench for depositing a dielectric film, and the dielectric film fills the whole trench.
Further, the dielectric film is silicon dioxide.
Further, the dielectric film deposition process is a thermal oxidation method, or atomic layer deposition, or a spin coating method.
The method for forming the high aspect ratio isolation in the high-energy ion implantation process can overcome the depth limit of the high-energy ion implantation process and the CD or aspect ratio limit of photoetching, and can solve the technical problem that the photodiode pixel unit of a CMOS image sensor product is pushed to be smaller in size and deeper. The depth of deep P well isolation can reach 6um, and the P well isolation size can be reduced to 0.1 um.
Drawings
Fig. 1a and 1b are flow charts of isolation by ion implantation in the prior art.
Fig. 2a to 2d are flow charts of a method for forming high aspect ratio isolation according to a first preferred embodiment of the present invention.
Fig. 3a to 3e are flow charts of a method for forming high aspect ratio isolation according to a second preferred embodiment of the present invention.
Detailed Description
The following description will be given with reference to the accompanying drawings, but the present invention is not limited to the following embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is noted that the drawings are in greatly simplified form and that non-precision ratios are used for convenience and clarity only to aid in the description of the embodiments of the invention.
Taking the pixel isolation process of a CMOS image sensor as an example, a pixel area chip with an isolation depth of 5um and an isolation layer with a critical dimension of 0.15um needs to be manufactured, and the following are two embodiments of the present invention:
referring to fig. 2a to 2d, fig. 2a to 2d are flow charts of a method for forming high aspect ratio isolation according to a first preferred embodiment of the present invention. The invention provides a method for forming high aspect ratio isolation in a high-energy ion implantation process, which comprises the following steps:
the method comprises the following steps: preparing a silicon substrate, and sequentially arranging a silicon substrate epitaxial layer, a grinding stop layer and a mask pattern layer from bottom to top above the silicon substrate;
step two: etching a silicon groove with a high depth-to-width ratio on the structure, wherein the bottom of the groove is positioned on the silicon substrate and is close to the epitaxial layer of the silicon substrate;
step three: selectively epitaxially growing a single-layer or multi-layer monocrystalline silicon on the outer side of the structure, wherein the monocrystalline silicon fills the whole groove;
step four: and chemically and mechanically grinding the epitaxial growth monocrystalline silicon above the groove, stopping on the grinding stop layer, and finally removing the residual grinding stop layer.
The method mainly comprises four major steps, and the specific process steps and the notes are as follows:
1. the hard mask layer material and thickness for high aspect ratio trench etch are determined by selecting both oxide and nitride films in general, since the selectivity ratio of these two film qualities for silicon etch can typically reach 50: 1 or even higher. The photoresist can be used directly as a mask for silicon etching if the contradiction between the thickness and the critical dimension of the photoresist can be solved, but a dielectric film is needed below the photoresist because the photoresist can prevent monocrystalline silicon from growing on the surface of the silicon wafer during selective epitaxial growth and can also serve as a grinding stop layer during the planarization of the silicon wafer.
According to a preferred embodiment of the present invention, the polishing stop layer is silicon dioxide or silicon nitride, the mask pattern layer is a photoresist formed by a single exposure, and further, the mask pattern layer is a pattern formed by a single exposure and etching, and the film is an oxide film or a nitride film.
Referring to fig. 2a, a silicon substrate epitaxial layer 301, a polishing stop layer 102, and a mask patterning layer 201 are sequentially disposed on a silicon substrate 100 from bottom to top. Firstly, preparing a silicon substrate 100, and epitaxially growing a silicon substrate epitaxial layer 301 on the silicon substrate, wherein the silicon substrate epitaxial layer is generally deeper than the target isolation depth, so that when a subsequent back silicon wafer is ground, a sufficient process window can be ensured, and 6um is selected in the preferred embodiment; the doping type of the silicon substrate epitaxial layer 301 is N type, a grinding stop layer 102 is selectively grown above the epitaxial layer, the film needs to have a certain chemical mechanical grinding selection ratio on silicon, silicon oxide or silicon nitride is preferred, the thickness needs to be determined according to the height of silicon epitaxially grown on the silicon wafer by a trench epitaxial growth process, and the preferred thickness is 500-1000A.
As shown in fig. 2a, a mask patterning layer 201 is formed. The existing commercial high aspect ratio trench etching equipment can achieve a very high selection ratio even for photoresist, the mask pattern layer 201 can be formed directly by the photoresist, and can also be formed into a hard mask layer pattern by an etching process, generally speaking, two types of oxide films and nitride films are selected, if the mask layer pattern layer is the photoresist, the thickness is slightly thicker, the critical dimension of the example is selected to be 0.21um, and the thickness can be selected to be between 4000A and 6000A in consideration of the resolution of the photoresist; if a silicon oxide or silicon nitride hard mask layer is selected, the thickness of the mask patterning layer 201 may be reduced to 1500-2000A.
2. And etching the silicon groove with high depth-to-width ratio. The difficulty of this step is related to the critical dimension of the silicon trench and the etching depth, and the smaller the critical dimension is, the deeper the depth is, the greater the difficulty is. The depth is somewhat determined by the device requirements. The pixel size is reduced to reduce the chip area and reduce the cost, but the Full Well Capacitance (FWC) is reduced at the same time, and the method of compensating the FWC is to push the photodiode well to the lower side of the silicon wafer, taking the deep P-well isolation of the mainstream CMOS image sensor at present as an example, about 2um is generally required, but the technical development trend is to push the depth to be deeper, for example, 3um to 4 um. The commercial high aspect ratio etching equipment is mature, and the etching aspect ratio can reach 100: 1. referring to fig. 2b, according to the preferred embodiment of the present invention, the depth-to-width ratio of the etched trench is greater than 10: 1. the etching depth of the groove is 1-2 um larger than the thickness of the silicon substrate epitaxial layer, and the bottom of the groove is formed below the silicon substrate epitaxial layer.
As shown in fig. 2b, a high aspect ratio silicon trench etch is performed. The difficulty of this step is related to the critical dimension of the silicon trench and the etching depth, and the smaller the critical dimension is, the deeper the depth is, the greater the difficulty is. Currently, a bosch process is generally adopted for high aspect ratio etching, which is an etching method in which deposition and etching are alternately performed, and the aspect ratio of the process can even reach 100: 1, the gas used in the etching step is generally SF6 etching gas, and the gas C4F8 is used in the deposition step; after the etching process, if the subsequent epitaxial growth is influenced by the etching damage on the side wall, a high-temperature repairing step can be added before the epitaxial growth.
3. The selective epitaxial growth is carried out after the high-aspect-ratio silicon groove is formed, and a layer of dielectric film is reserved on the surface of the silicon chip, so that a thin film cannot grow above the silicon chip, monocrystalline silicon can grow along the etched side wall and the etched bottom plane, and the selective epitaxial growth is not growth of a nucleation mechanism and is insensitive to the high-aspect-ratio pattern. An additional benefit of selective epitaxy is that the doping concentration of the monocrystalline silicon in the trench can be controlled in the lateral direction. For example, according to the conventional method, if the critical dimension of the pattern of the deep well isolation is 0.1um, the pattern of the high-energy implantation must be 0.1um, but with the method of the present invention, the pattern of the etching must not be 0.1um, for example, the etching can be 0.16um, two-step doping is performed during the epitaxial growth, the first step is to grow 300A N-type doped epitaxial layer (the same as the N-type doping of the photodiode), the second step is to fill up the P-type doped epitaxial layer (the same as the P-type doping of the high-energy implantation), and the final effect is the same as the effect of the 0.1um high-energy implantation.
During the final growth of the seal, part of defects may be generated by the epitaxial growth, which may affect the isolation effect of the device, and the seal portion may be selectively processed by thermal oxidation or other oxidation growth methods.
Referring to fig. 2c, according to a preferred embodiment of the present invention, the single-layer single-crystal silicon and the silicon substrate epitaxial layer have different doping types, the doping types of the first layer of the multi-layer single-crystal silicon and the silicon substrate epitaxial layer are the same, and the critical dimension of the trench after the epitaxy is finished is the same as the target dimension. A trench epitaxial growth layer 303 is formed in the trench structure.
After removing the residual polish stop layer 102, a trench epitaxial growth layer 303 is formed using an epitaxial growth process to grow doped monocrystalline silicon, which is required to fill the trench portions, as shown in fig. 2 c. At this time, a layer of grinding stop layer 102 is reserved on the surface of the silicon wafer, so that a thin film cannot grow above the silicon wafer, monocrystalline silicon can grow along the etched side wall and the etched bottom plane, and the silicon wafer is insensitive to a pattern with a high aspect ratio because selective epitaxy is not the growth of a nucleation mechanism. An additional benefit of selective epitaxy is that the doping concentration of the monocrystalline silicon in the trench can be controlled in the lateral direction. For example, according to the traditional method, if the key dimension of the pattern of the deep well isolation is 0.15um, the photoetching pattern of high-energy injection is required to be 0.15um, but by using the method of the invention, the photoetching pattern for etching does not need to be 0.15um, the photoetching key dimension of the embodiment is 0.21um, the epitaxial growth is carried out in two steps, the first step is to grow the 300A N-type doped epitaxial layer, and the N-type doping of the silicon substrate is the same; the second step is to fill up the P-type doped epitaxial layer (same as the P-type doping of the high-energy implantation in the conventional method), and the final effect is the same as that of the high-energy implantation of 0.15 um.
4. After the selective epitaxial growth is finished, a part of monocrystalline silicon protrudes in a groove area, the silicon wafer needs to be flattened by using a chemical mechanical grinding process, grinding is stopped on a dielectric film on the surface of the silicon wafer, and then the dielectric film is removed by a wet method. Resulting in the structure shown in figure 2 d.
As shown in fig. 2d, after the selective epitaxial growth is finished, a portion of the epitaxial growth layer 303 of the trench of the single crystal silicon protrudes in the trench region, it is necessary to planarize the silicon wafer by using a chemical mechanical polishing process, polish the silicon wafer to stop on the polishing stop layer 102 on the surface of the silicon wafer, and then remove the polishing stop layer 102 by a wet process.
Referring to fig. 3a to 3e, fig. 3a to 3e are flow charts of a method for forming high aspect ratio isolation according to a second preferred embodiment of the present invention. The invention provides a method for forming high aspect ratio isolation in a high-energy ion implantation process, which comprises the following steps:
the method comprises the following steps: preparing a silicon substrate, and sequentially arranging a silicon substrate epitaxial layer, a grinding stop layer and a mask pattern layer from bottom to top above the silicon substrate;
step two: etching a silicon groove with a high depth-to-width ratio on the structure, wherein the bottom of the groove is positioned on the silicon substrate and is close to the epitaxial layer of the silicon substrate;
step three: selectively epitaxially growing a single-layer or multi-layer monocrystalline silicon on the outer side of the structure, wherein the monocrystalline silicon does not fill the whole groove, and a gap is reserved in the groove;
step four: depositing a dielectric film in the gap of the groove, wherein the dielectric film fills the whole groove
Step five: and chemically and mechanically grinding the epitaxial growth monocrystalline silicon above the groove, stopping on the grinding stop layer, and finally removing the residual grinding stop layer.
According to a preferred embodiment of the present invention, the dielectric film is silicon dioxide. The dielectric film deposition process is a thermal oxidation method, atomic layer deposition or a spin coating method.
The process steps of the second preferred embodiment of the present invention before the deep trench epitaxial growth are identical to those of the previous embodiment, as shown in fig. 3a and 3 b. There are some variations in the steps of the epitaxial growth, as shown in fig. 3c and 3d, the first step is to grow 300A of an N-doped epitaxial layer, which is the same as the N-doping of the silicon substrate; a second step of growing a 600A P-doped epitaxial layer (same as the P-type doping of the high-energy implantation in the traditional method); in the third step, a dielectric isolation layer 304 is grown to fill the whole trench, and in this embodiment, the dielectric isolation layer 304 only needs to be grown for more than 200A to fill the trench, so that many processes can be selected, such as a thermal oxidation method, a high temperature annealing process in an oxygen environment, or an atomic layer deposition process. These processes have good step coverage and high aspect ratio fill capability, but it should be noted that the oxidation process consumes a portion of the P-type doped epitaxial layer in the trench, so the P-type doping concentration in the second step needs to be increased.
As shown in fig. 3d, after the selective epitaxial growth is finished, a part of the monocrystalline silicon trench epitaxial growth layer 303 and the dielectric isolation layer 304 in the trench region will protrude, the silicon wafer needs to be planarized by using a chemical mechanical polishing process, and polishing is stopped on the polishing stop layer 102 on the surface of the silicon wafer, and due to the existence of the oxide film of the dielectric isolation layer 304, the film quality of the polishing stop layer 102 is better to be selected by using a nitride film having a polishing selection ratio to the dielectric isolation layer 304; even if the same material is selected for the oxide film, the protruding dielectric isolation layer 304 is removed when the polish stop layer 102 is finally removed by wet etching.
In summary, the method for forming high aspect ratio isolation in a high-energy ion implantation process provided by the invention can overcome the depth limit of the high-energy ion implantation process and the CD or aspect ratio limit of lithography, and can solve the technical problem that the photodiode pixel unit of a CMOS image sensor product is pushed to be smaller in size and deeper. The depth of deep P well isolation can reach 6um, and the P well isolation size can be reduced to 0.1 um.
Although the present invention has been described with reference to the preferred embodiments, it is not intended to be limited thereto. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the protection scope of the present invention should be determined by the appended claims.
Claims (9)
1. A method for forming high aspect ratio isolation in a high energy ion implantation process, comprising the steps of:
the method comprises the following steps: preparing a silicon substrate, and sequentially arranging a silicon substrate epitaxial layer, a grinding stop layer and a mask pattern layer from bottom to top above the silicon substrate;
step two: etching the silicon substrate with a high depth-to-width ratio to form a silicon groove, wherein the bottom of the groove is positioned on the silicon substrate and is close to the epitaxial layer of the silicon substrate;
step three: selectively epitaxially growing a single-layer or multi-layer monocrystalline silicon on the outer side of the silicon substrate, wherein the monocrystalline silicon does not fill the whole groove, a gap is reserved in the groove for depositing a dielectric film, and the whole groove is filled with the dielectric film; the doping types of the first layer of the multilayer monocrystalline silicon and the epitaxial layer of the silicon substrate are the same, and the key size of the groove after the epitaxy is finished is consistent with the target size;
step four: and chemically and mechanically grinding the epitaxial growth monocrystalline silicon above the groove, stopping on the grinding stop layer, and finally removing the residual grinding stop layer.
2. The method of claim 1, wherein the polishing stop layer is silicon dioxide or silicon nitride.
3. The method of claim 1, wherein the mask pattern layer is a photoresist that is exposed at one time.
4. The method of claim 1, wherein the mask pattern layer is a pattern formed by one exposure and etching, and the film is an oxide film or a nitride film.
5. The method of claim 1, wherein the trench is etched to a depth-to-width ratio greater than 10: 1.
6. the method of claim 1, wherein the trench etch depth is 1um-2um greater than the silicon substrate epitaxial layer thickness, and the bottom of the trench is formed below the silicon substrate epitaxial layer.
7. The method of claim 1, wherein the single layer of single crystal silicon and the epitaxial layer of the silicon substrate are doped differently.
8. The method of claim 7, wherein the dielectric film is silicon dioxide.
9. The method for forming high aspect ratio isolation in high energy ion implantation process according to claim 8, wherein the dielectric film deposition process is a thermal oxidation method or an atomic layer deposition or a spin coating method.
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| CN101887847A (en) * | 2009-05-13 | 2010-11-17 | 上海华虹Nec电子有限公司 | Method for forming monocrystal silicon structure with alternated P types and N types |
| CN104716178A (en) * | 2013-12-11 | 2015-06-17 | 上海华虹宏力半导体制造有限公司 | LDMOS device with deep hole and manufacturing method of LDMOS device |
| CN104658914A (en) * | 2015-02-15 | 2015-05-27 | 上海华虹宏力半导体制造有限公司 | Deep trench manufacturing method capable of improving morphology, and deep trench |
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