CN107248495A - A kind of method that high-aspect-ratio isolation is formed in energetic ion injection technology - Google Patents
A kind of method that high-aspect-ratio isolation is formed in energetic ion injection technology Download PDFInfo
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- CN107248495A CN107248495A CN201710471715.9A CN201710471715A CN107248495A CN 107248495 A CN107248495 A CN 107248495A CN 201710471715 A CN201710471715 A CN 201710471715A CN 107248495 A CN107248495 A CN 107248495A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
Abstract
The present invention proposes a kind of method that high-aspect-ratio isolation is formed in energetic ion injection technology, comprises the following steps：Step one：Prepare silicon chip, and set gradually above the silicon chip silicon chip epitaxial layer, polish stop layer, mask graph layer from down to up；Step 2：Silicon of high aspect ratio etching groove is carried out to said structure, channel bottom is located at silicon chip and close to silicon chip epitaxial layer；Step 3：Selective epitaxial growth individual layer or multilayer monocrystalline silicon on the outside of said structure, the monocrystalline silicon fill up whole groove；Step 4：Epitaxial growth monocrystalline silicon above cmp groove, is stopped in the polish stop layer, finally removes remaining polish stop layer.The present invention can overcome energetic ion injection technology depth limit and the CD or the depth-to-width ratio limit of photoetching, can solve the technical barrier that the optical diode pixel cell of CMOS image sensor products is promoted toward smaller szie, deeper depth.
Description
Technical field
The present invention relates to formed in semiconductor integrated circuit manufacture field, and more particularly to a kind of energetic ion injection technology
The method of high-aspect-ratio isolation.
Background technology
Fig. 1 a, Fig. 1 b are to be provided with base on silicon chip 10 in the process chart that existing ion implanting is isolated, Fig. 1 a
Mask pattern layer 21 is arranged at intervals with piece epitaxial layer 31 and injection sacrifice layer 11, the injection sacrifice layer 11, to shown in Fig. 1 a
Structure progress ion implanting processing, which is formed on structure shown in Fig. 1 b, silicon chip 10, is intervally distributed with substrate epitaxial layer 31 and implanted layer
32.But in the technique that some high energy ion implantations are isolated, line width (space) has required 0.15um, and photoresist highly reaches
4um thickness, depth-to-width ratio has been above 20, and this requires the limit for having been over conventional lithography process；In this high-aspect-ratio
Technological requirement under, the general technology using tri-layer, using etching to photoresist, hard mask layer, implant blocking layer this three
Selection between layer is than change, in the pattern transfer of photoresist to following implant blocking layer.But when implant blocking layer
When the ratio of thickness and critical size is too big, the pattern of taper or bowling is easy for occurring.If implant blocking layer
Too thick, the problem of edge over etching easily occurs in hard mask layer causes implant blocking layer burr phenomena occur in pattern edge；Together
When high energy ion implantation machine the limit also limit some deep trap applications, the deep trap isolation of such as CMOS image sensors optical diode.
The content of the invention
The present invention proposes a kind of method that high-aspect-ratio isolation is formed in energetic ion injection technology, can overcome high energy from
Sub- injection technology depth limit and the CD or the depth-to-width ratio limit of photoetching, can solve the light two of CMOS image sensor products
The technical barrier that pole pipe pixel cell is promoted toward smaller szie, deeper depth.
In order to achieve the above object, the present invention proposes to form the side of high-aspect-ratio isolation in a kind of energetic ion injection technology
Method, comprises the following steps：
Step one：Prepare silicon chip, and set gradually silicon chip epitaxial layer from down to up above the silicon chip, grind
Stop-layer, mask graph layer；
Step 2：Silicon of high aspect ratio etching groove is carried out to said structure, channel bottom is located at silicon chip and close to silicon substrate
Piece epitaxial layer；
Step 3：Selective epitaxial growth individual layer or multilayer monocrystalline silicon on the outside of said structure, the monocrystalline silicon are filled up
Whole groove；
Step 4：Epitaxial growth monocrystalline silicon above cmp groove, is stopped in the polish stop layer, most
Remaining polish stop layer is removed afterwards.
Further, the polish stop layer is silica or silicon nitride.
Further, the mask graph layer is the photoresist of single exposure.
Further, the figure that the mask graph layer is formed for single exposure and etching, film quality is oxide-film or nitrogen
Change film.
Further, the depth-to-width ratio after the etching groove is more than 10：1.
Further, the big 1um-2um of the etching groove depth ratio silicon chip epitaxy layer thickness, forms the channel bottom
Below silicon chip epitaxial layer.
Further, the individual layer monocrystalline silicon and silicon chip epitaxial layer are different doping types.
Further, the first layer of the multilayer monocrystalline silicon is identical with silicon chip epitaxial layer doping type, after extension terminates
Groove critical size it is consistent with target size.
Further, monocrystalline silicon does not fill up whole groove in the step 4, and space is reserved in the trench to be used to sink
Product deielectric-coating, the deielectric-coating fills up whole groove.
Further, the deielectric-coating is silica.
Further, the deielectric-coating depositing operation is thermal oxidation method or ald or spin-coating method.
The method that high-aspect-ratio isolation is formed in energetic ion injection technology proposed by the present invention, can overcome energetic ion
Injection technology depth limit and the CD or the depth-to-width ratio limit of photoetching, can solve the pole of light two of CMOS image sensor products
The technical barrier that pipe pixel cell is promoted toward smaller szie, deeper depth.The depth of deep p-well isolation can reach 6um, p-well every
0.1um can be reduced to from size.
Brief description of the drawings
Fig. 1 a and Fig. 1 b show the process chart that ion implanting in the prior art is isolated.
Fig. 2 a~Fig. 2 d show the method flow diagram of the formation high-aspect-ratio isolation of the first preferred embodiment of the invention.
Fig. 3 a~Fig. 3 e show the method flow diagram of the formation high-aspect-ratio isolation of the second preferred embodiment of the invention.
Embodiment
The embodiment of the present invention is provided below in conjunction with accompanying drawing, but the invention is not restricted to following embodiment.Root
According to following explanation and claims, advantages and features of the invention will become apparent from.It should be noted that, accompanying drawing is using very simple
The form of change and use non-accurately ratio, be only used for conveniently, lucidly aid in illustrating the embodiment of the present invention purpose.
By taking the pixel isolation technique of CMOS image sensors as an example, it is now desired to make isolation depth 5um, separation layer is crucial
Size 0.15um pixel region chip, the following is two embodiments of the present invention：
Refer to Fig. 2 a~Fig. 2 d, Fig. 2 a~Fig. 2 d show the formation high-aspect-ratio of the first preferred embodiment of the invention every
From method flow diagram.The method that the present invention proposes formation high-aspect-ratio isolation in a kind of energetic ion injection technology, including under
Row step：
Step one：Prepare silicon chip, and set gradually silicon chip epitaxial layer from down to up above the silicon chip, grind
Stop-layer, mask graph layer；
Step 2：Silicon of high aspect ratio etching groove is carried out to said structure, channel bottom is located at silicon chip and close to silicon substrate
Piece epitaxial layer；
Step 3：Selective epitaxial growth individual layer or multilayer monocrystalline silicon on the outside of said structure, the monocrystalline silicon are filled up
Whole groove；
Step 4：Epitaxial growth monocrystalline silicon above cmp groove, is stopped in the polish stop layer, most
Remaining polish stop layer is removed afterwards.
This method mainly divides four big step, and concrete technology step and points for attention are as follows:
1. determine the hardmask layer and thickness of high aspect ratio trench quite etching, it is however generally that selective oxidation film and nitride film
Two kinds, because both film quality can typically reach 50 for the selection ratio of silicon etching：1 even more high.If the thickness of photoresistance
It can solve to select with the contradiction of critical size directly to use photoresistance as the mask of silicon etching, but photoresistance bottom is also
It is to need deielectric-coating, because it can be prevented in silicon chip surface growing single-crystal silicon when selective epitaxial growth, while
The stop-layer of grinding is served as when planarization silicon chip.
According to present pre-ferred embodiments, the polish stop layer is silica or silicon nitride, the mask graph
Layer is the photoresist of single exposure, further, the figure that the mask graph layer is formed for single exposure and etching, and film quality is
Oxide-film or nitride film.
Fig. 2 a are refer to, the top of silicon chip 100 sets gradually silicon chip epitaxial layer 301, grinding and stopped from down to up
Layer 102, mask graph layer 201.Prepare silicon chip 100, one layer of silicon chip epitaxial layer 301 of epitaxial growth in the above, one first
As can be deeper than target isolation depth, so in follow-up back side silicon chip grinding, can guarantee that enough process windows,
6um is selected in this preferred embodiment；The doping type selection N-type of silicon chip epitaxial layer 301, growth selection one above epitaxial layer
Layer polish stop layer 102, this layer film needs have certain cmp selection ratio, preferably silica or nitridation to silicon
Silicon, thickness is needed according to the decision of the height of groove epitaxial growth technology silicon of epitaxial growth above silicon chip, and preferred thickness is
500-1000A。
As shown in Figure 2 a, mask graph layer 201 is formed.It is existing commercialization high aspect ratio trench quite etching apparatus even for
For photoresist, very high selection ratio can also be reached, mask graph layer 201 can be that photoresist is directly formed, can also be through
Over etching technique formation hard mask layer figure, it is however generally that two kinds of selective oxidation film and nitride film, if photoresist, thickness will
It is slightly thicker, this example critical size selection 0.21um, it is contemplated that the resolution ratio of photoresist, thickness can select 4000A to arrive
Between 6000A；If selection is silica or silicon nitride hardmask layer, mask graph 201 thickness of layer can drop to 1500-
2000A。
2. carry out silicon of high aspect ratio etching groove.The difficulty of this step and the critical size of silicon trench and etching depth phase
Close, critical size is smaller, and depth is deeper, and difficulty is bigger.How much depth is determined by requirement on devices.Pixel Dimensions reduce be for
Diminution chip area, reduces cost, but can reduce full trap electric capacity (FWC) simultaneously, and compensation FWC method is exactly the pole of light two
Pipe trap by taking the deep p-well isolation of current main stream of CMOS image sensor as an example, typically requires 2um or so, still toward pushing away below silicon chip
Technology trends are promoted toward deeper depth such as 3um-4um.The high aspect ratio equipment of business is very now
Ripe, etching depth-to-width ratio can reach 100：1.Fig. 2 b are refer to, according to present pre-ferred embodiments, after the etching groove
Depth-to-width ratio be more than 10：1.The big 1um-2um of the etching groove depth ratio silicon chip epitaxy layer thickness, forms the channel bottom
Below silicon chip epitaxial layer.
As shown in Figure 2 b, silicon of high aspect ratio etching groove is carried out.The difficulty of this step and the critical size of silicon trench and
Etching depth is related, and critical size is smaller, and depth is deeper, and difficulty is bigger.Current high aspect ratio typically uses bosch works
Skill, this is a kind of lithographic method of deposition and etching alternately, and the depth-to-width ratio of this technique even can reach 100：1, carve
The gas that erosion step is used is generally SF6 etching gas, and deposition step uses C4F8 gases；After etching technics, on the wall of side such as
Fruit worries etching injury influence subsequently epitaxial growing, can increase by a step high temperature before epitaxial growth and repair step.
3. selective epitaxial growth occurs after high-aspect-ratio silicon trench is formed, at this moment silicon chip surface also retains one layer
Deielectric-coating, can so ensure above silicon chip will not growing film, and monocrystalline silicon can be along the side wall and base plane after etching
Growth, because selective epitaxial is not the growth of Review On The Nucleation Mechanism, its figure to high-aspect-ratio is insensitive.Selective epitaxial it is another
An outer benefit is that the doping concentration of monocrystalline silicon in groove can be controlled along horizontal direction.Such as according to the conventional method, it is deep
The graphics critical dimension of trap isolation is if it is desired to accomplish 0.1um, and the litho pattern of high energy ion implantation must just accomplish 0.1um, still
With the method for the present invention, the litho pattern of etching is just not necessarily intended to accomplish 0.1um, and for example etching can accomplish 0.16um,
Adulterated in two steps when epitaxial growth, the epitaxial layer of the first one-step growth 300A n-type doping (and the n-type doping of optical diode
It is identical), second step fills up the epitaxial layer (the p-type doping with high energy ion implantation is identical) of p-type doping, and final effect and 0.1um are high
The effect that can be injected is identical.
When last growth sealing, general epitaxial growth has segmental defect generation, may influence device every
From effect, it can select to handle closure part using thermal oxide or other oxidation growth modes.
Fig. 2 c are refer to, according to present pre-ferred embodiments, the individual layer monocrystalline silicon and silicon chip epitaxial layer are different
Doping type, the first layer of the multilayer monocrystalline silicon is identical with silicon chip epitaxial layer doping type, and the groove after extension terminates is closed
Key size is consistent with target size.Groove epitaxially grown layer 303 is formed in the groove structure.
As shown in Figure 2 c, remove after residual polish stop layer 102, the monocrystalline silicon of doping is grown using epitaxial growth technology
Groove epitaxially grown layer 303 is formed, it needs to fill up trench portions.At this moment silicon chip surface also retains one layer of polish stop layer
102, can so ensure above silicon chip will not growing film, and monocrystalline silicon can give birth to along the side wall after etching and base plane
Long, because selective epitaxial is not the growth of Review On The Nucleation Mechanism, its figure to high-aspect-ratio is insensitive.Selective epitaxial is in addition
One benefit is that the doping concentration of monocrystalline silicon in groove can be controlled along horizontal direction.Such as according to the conventional method, deep trap
The graphics critical dimension of isolation is if it is desired to accomplish 0.15um, and the litho pattern of high energy ion implantation must just accomplish 0.15um, still
Using the method for the present invention, the litho pattern of etching avoids the need for accomplishing 0.15um, the selection of this example photoetching critical size
0.21um, adulterates in two steps when epitaxial growth, the epitaxial layer of the first one-step growth 300A n-type doping, and silicon chip N
Type doping is identical；Second step fills up the epitaxial layer (the p-type doping with traditional method high energy ion implantation is identical) of p-type doping, finally
Effect it is identical with the effect of 0.15um high energy ion implantations.
After 4. selective epitaxial growth terminates, in trench region, some monocrystalline silicon can be protruded, it is necessary to using chemical machinery
Grinding technics planarizes silicon chip, and grinding is stopped on the deielectric-coating of silicon chip surface, and then wet method removes this layer dielectric.Formed
Structure shown in Fig. 2 d.
As shown in Figure 2 d, in the groove epitaxial growth of some monocrystalline silicon of trench region after selective epitaxial growth terminates
Layer 303 can be protruded, it is necessary to planarize silicon chip using chemical mechanical milling tech, and grinding stops at the polish stop layer of silicon chip surface
On 102, then wet method removes this layer of polish stop layer 102.
Refer to Fig. 3 a~Fig. 3 e, Fig. 3 a~Fig. 3 e show the formation high-aspect-ratio of the second preferred embodiment of the invention every
From method flow diagram.The method that the present invention proposes formation high-aspect-ratio isolation in a kind of energetic ion injection technology, including under
Row step：
Step one：Prepare silicon chip, and set gradually silicon chip epitaxial layer from down to up above the silicon chip, grind
Stop-layer, mask graph layer；
Step 2：Silicon of high aspect ratio etching groove is carried out to said structure, channel bottom is located at silicon chip and close to silicon substrate
Piece epitaxial layer；
Step 3：Selective epitaxial growth individual layer or multilayer monocrystalline silicon on the outside of said structure, the monocrystalline silicon are not filled out
Full whole groove, reserves space in the trench；
Step 4：The deposition medium film in the space of the groove, the deielectric-coating fills up whole groove
Step 5：Epitaxial growth monocrystalline silicon above cmp groove, is stopped in the polish stop layer, most
Remaining polish stop layer is removed afterwards.
According to present pre-ferred embodiments, the deielectric-coating is silica.The deielectric-coating depositing operation is thermal oxide
Method or ald or spin-coating method.
Processing step and previous embodiment complete phase of second preferred embodiment of the invention before deep trench epitaxial growth
Together, as shown in Figure 3 a, 3 b.There are some changes the step of epitaxial growth, as shown in Fig. 3 c and Fig. 3 d, the first one-step growth 300A
N-type doping epitaxial layer, it is identical with the n-type doping of silicon chip；Second one-step growth 600A p-type doping epitaxial layer (and pass
The p-type doping of the method high energy ion implantation of system is identical)；3rd one layer of one-step growth buffer layer 304 fills up whole groove, this implementation
Buffer layer 304, which only needs to growth more than 200A, in example can just fill up groove, it is possible to which the technique of selection is a lot, than
High-temperature annealing process under such as thermal oxidation method, oxygen atmosphere, or atom layer deposition process.This several technique has well
Step coverage, the filling capacity with high-aspect-ratio, it is however noted that the method for oxidation can consume a part of ditch
The epitaxial layer of groove p-type doping, so the p-type doping concentration of second step needs increase.
As shown in Figure 3 d, in some monocrystalline silicon trench epitaxially grown layer of trench region after selective epitaxial growth terminates
303 and buffer layer 304 can protrude, it is necessary to using chemical mechanical milling tech planarize silicon chip, grinding stop at silicon chip table
In the polish stop layer 102 in face, because the film quality with the presence of the oxide-film of buffer layer 304, polish stop layer 102 selects to adopt
There is the nitride film of grinding selectivity ratio relatively good with to buffer layer 304；Even if selecting the oxide-film of phase same material, last wet
When method removes polish stop layer 102, prominent buffer layer 304 can be also removed.
In summary, in energetic ion injection technology proposed by the present invention formed high-aspect-ratio isolation method, can with gram
Energetic ion injection technology depth limit and the CD or the depth-to-width ratio limit of photoetching are taken, the production of CMOS image sensors can be solved
The technical barrier that the optical diode pixel cell of product is promoted toward smaller szie, deeper depth.The depth of deep p-well isolation can reach
6um, p-well isolation size can be reduced to 0.1um.
Although the present invention is disclosed above with preferred embodiment, so it is not limited to the present invention.Skill belonging to of the invention
Has usually intellectual in art field, without departing from the spirit and scope of the present invention, when can be used for a variety of modifications and variations.Cause
This, the scope of protection of the present invention is defined by those of the claims.
Claims (11)
1. the method for high-aspect-ratio isolation is formed in a kind of energetic ion injection technology, it is characterised in that comprise the following steps：
Step one：Prepare silicon chip, and set gradually silicon chip epitaxial layer from down to up above the silicon chip, grind stopping
Layer, mask graph layer；
Step 2：Silicon of high aspect ratio etching groove is carried out to said structure, channel bottom is located at silicon chip and close to outside silicon chip
Prolong layer；
Step 3：Selective epitaxial growth individual layer or multilayer monocrystalline silicon on the outside of said structure, the monocrystalline silicon are filled up entirely
Groove；
Step 4：Epitaxial growth monocrystalline silicon above cmp groove, stops in the polish stop layer, finally goes
Except remaining polish stop layer.
2. the method for high-aspect-ratio isolation is formed in energetic ion injection technology according to claim 1, it is characterised in that
The polish stop layer is silica or silicon nitride.
3. the method for high-aspect-ratio isolation is formed in energetic ion injection technology according to claim 1, it is characterised in that
The mask graph layer is the photoresist of single exposure.
4. the method for high-aspect-ratio isolation is formed in energetic ion injection technology according to claim 1, it is characterised in that
The figure that the mask graph layer is formed for single exposure and etching, film quality is oxide-film or nitride film.
5. the method for high-aspect-ratio isolation is formed in energetic ion injection technology according to claim 1, it is characterised in that
Depth-to-width ratio after the etching groove is more than 10：1.
6. the method for high-aspect-ratio isolation is formed in energetic ion injection technology according to claim 1, it is characterised in that
The big 1um-2um of the etching groove depth ratio silicon chip epitaxy layer thickness, forms the channel bottom and is located at silicon chip epitaxial layer
Lower section.
7. the method for high-aspect-ratio isolation is formed in energetic ion injection technology according to claim 1, it is characterised in that
The individual layer monocrystalline silicon and silicon chip epitaxial layer are different doping types.
8. the method for high-aspect-ratio isolation is formed in energetic ion injection technology according to claim 1, it is characterised in that
The first layer of the multilayer monocrystalline silicon is identical with silicon chip epitaxial layer doping type, extension terminate after groove critical size and mesh
Dimensioning is consistent.
9. the method for high-aspect-ratio isolation is formed in energetic ion injection technology according to claim 1, it is characterised in that
Monocrystalline silicon does not fill up whole groove in the step 4, and space is reserved in the trench is used for deposition medium film, the medium
Film fills up whole groove.
10. forming the method for high-aspect-ratio isolation in energetic ion injection technology according to claim 9, its feature exists
In the deielectric-coating is silica.
11. forming the method for high-aspect-ratio isolation in energetic ion injection technology according to claim 9, its feature exists
In the deielectric-coating depositing operation is thermal oxidation method or ald or spin-coating method.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111573616A (en) * | 2020-04-24 | 2020-08-25 | 中国电子科技集团公司第十三研究所 | Composite type high depth-to-width ratio groove standard sample plate and preparation method |
| CN113299739A (en) * | 2021-05-21 | 2021-08-24 | 江苏东海半导体科技有限公司 | Power device epitaxial structure and manufacturing method thereof |
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| CN104658914A (en) * | 2015-02-15 | 2015-05-27 | 上海华虹宏力半导体制造有限公司 | Deep trench manufacturing method capable of improving morphology, and deep trench |
| CN104716178A (en) * | 2013-12-11 | 2015-06-17 | 上海华虹宏力半导体制造有限公司 | LDMOS device with deep hole and manufacturing method of LDMOS device |
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| CN111573616A (en) * | 2020-04-24 | 2020-08-25 | 中国电子科技集团公司第十三研究所 | Composite type high depth-to-width ratio groove standard sample plate and preparation method |
| CN111573616B (en) * | 2020-04-24 | 2024-02-13 | 中国电子科技集团公司第十三研究所 | Composite high aspect ratio groove standard template and preparation method thereof |
| CN113299739A (en) * | 2021-05-21 | 2021-08-24 | 江苏东海半导体科技有限公司 | Power device epitaxial structure and manufacturing method thereof |
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| CN107248495B (en) | 2020-01-24 |
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