CN103456675A - Shallow trench isolation structure manufacturing method and semiconductor device - Google Patents
Shallow trench isolation structure manufacturing method and semiconductor device Download PDFInfo
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- CN103456675A CN103456675A CN2012101831802A CN201210183180A CN103456675A CN 103456675 A CN103456675 A CN 103456675A CN 2012101831802 A CN2012101831802 A CN 2012101831802A CN 201210183180 A CN201210183180 A CN 201210183180A CN 103456675 A CN103456675 A CN 103456675A
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Abstract
The invention relates to a shallow trench isolation structure manufacturing method and a semiconductor device. The shallow trench isolation structure manufacturing method comprises the steps that a semiconductor substrate is provided; a dielectric layer is formed on the semiconductor substrate; the dielectric layer is etched to form at least two trenches which are wide on the upper portion and narrow on the lower portion; packing structure are formed in the trenches; the packing structures are changed into materials the same as the materials of the semiconductor substrate so that the packing structure can serve as active areas, and the dielectric layer between the packing structures serves as a shallow trench isolation structure. The shallow trench isolation structure manufacturing method is novel; the shallow trench isolation structure which is narrow on the upper portion and wide on the lower portion is used for manufacturing more devices in a specific area with a small size; meanwhile, a latch-up effect cannot occur easily, so that more effective electrical isolation is realized to meet the requirement of a semiconductor device manufacturing process for higher and higher packaging density and integration.
Description
Technical field
The present invention relates to integrated circuit and manufacture field, particularly relate to a kind of manufacture method and semiconductor device of fleet plough groove isolation structure.
Background technology
Along with the semiconductor technology develop rapidly, feature sizes of semiconductor devices significantly reduces, and semiconductor fabrication process is had higher requirement, and one of them challenging problem is exactly effectively insulation blocking between device.After manufacturing process enters the deep sub-micron technique node, the following element of 0.25 μ m adopts shallow trench isolation from (shallow trench isolation, STI) structure as the isolation between the MOS device active region mostly.
Please refer to Figure 1A ~ 1D, the generalized section of its each step corresponding construction that is existing a kind of sti structure manufacture method.
As shown in Figure 1A, at first, provide Semiconductor substrate 100, and form hard mask layer 101 on described Semiconductor substrate 100, described hard mask layer 101 is for example silicon nitride (Si
3n
4).
As shown in Figure 1B, then, dry etching hard mask layer 101 and Semiconductor substrate 100 form isolated groove 102 in described Semiconductor substrate 100, described isolated groove 102 is generally inverted trapezoidal structure wide at the top and narrow at the bottom, so that the bottom of subsequent deposition process time isolation groove 102 is easy to deposition.
As shown in Figure 1 C, then, in the interior formation substrate of described isolated groove 102 oxide layer 103, substrate oxide layer 103 is for example silica.
As shown in Fig. 1 D, then, utilize chemical vapor deposition (CVD) technique at the interior filling dielectric medium 104 of described isolated groove 102, also formed dielectric medium 104 simultaneously on described hard mask layer 101, described dielectric medium 104 is for example silica (SiO
2), then utilize cmp (CMP) technique to carry out planarization, remove hard mask layer 101 with and the dielectric medium of top, thereby form sti structure 200 in isolated groove 102.
Yet the sti structure 200 formed due to existing technique is generally structure wide at the top and narrow at the bottom, has taken more area, continues to dwindle at device feature size, after manufacturing process enters the nanoscale technology, is difficult to meet design requirement; And existing sti structure is unfavorable for increasing the length of parasitic PNP or npn bipolar transistor base, thereby be unfavorable for reducing current amplification factor, cause being prone to breech lock (latch up) effect.
Summary of the invention
The object of the present invention is to provide a kind of manufacture method of new fleet plough groove isolation structure, realize that specific small size zone makes more devices, adopts up-narrow and down-wide structure to make the more difficult generation of latch-up simultaneously.
For achieving the above object, a kind of manufacture method of fleet plough groove isolation structure comprises: semi-conductive substrate is provided; Form dielectric layer on described Semiconductor substrate; The described dielectric layer of etching forms at least two grooves wide at the top and narrow at the bottom; Form interstitital texture in described groove; And change described interstitital texture into the material identical with described Semiconductor substrate, so that described interstitital texture is as active area, the dielectric layer between described interstitital texture is as fleet plough groove isolation structure.
Alternatively, form dielectric layer on described Semiconductor substrate after, also comprise: form etching barrier layer and hard mask layer on described dielectric layer.
Alternatively, the step of at least two grooves wide at the top and narrow at the bottom of the described dielectric layer formation of etching comprises: the described hard mask layer of etching, etching barrier layer and dielectric layer form at least two the first grooves; And the dielectric layer of the described hard mask layer of etching, etching barrier layer and segment thickness, forming at least two the second grooves, described the second groove is communicated with the first groove, and the cross-sectional width of described the second groove is greater than the cross-sectional width of the first groove.
Alternatively, the step of at least two grooves wide at the top and narrow at the bottom of the described dielectric layer formation of etching comprises: the dielectric layer of etching hard mask layer, etching barrier layer and segment thickness forms at least two the first grooves; And the dielectric layer of described the first beneath trenches of etching, forming the second groove, described the second groove is communicated with the first groove, and the cross-sectional width of described the second groove is less than the cross-sectional width of the first groove.
Alternatively, adopt the described dielectric layer of dry etching to form at least two grooves wide at the top and narrow at the bottom.
Alternatively, in described groove, the step of formation interstitital texture comprises: in described groove He on dielectric layer, deposit packing material; And utilize the cmp skill to remove the packing material of described dielectric layer top, form interstitital texture.
Alternatively, described Semiconductor substrate is silicon substrate, and described packing material is polysilicon or amorphous silicon material.
Alternatively, adopt the method for laser molecular beam epitaxy growth to change described interstitital texture into the material identical with described Semiconductor substrate, temperature is 200 ℃ ~ 600 ℃, and the time is 5 seconds ~ 5 hours.
Alternatively, adopt the method for solid-phase epitaxial growth to change described interstitital texture into the material identical with described Semiconductor substrate, temperature is 600 ℃ ~ 900 ℃, and the time is 1 hour ~ 90 hours.
Alternatively, described dielectric layer and hard mask layer are silica, and described etching barrier layer is silicon nitride.
The present invention also protects the semiconductor device formed according to above-mentioned manufacture method, comprising: Semiconductor substrate; Be formed at the dielectric layer on described Semiconductor substrate; The groove wide at the top and narrow at the bottom that the described dielectric layer of etching forms; Be formed at the active area in described groove, the dielectric layer between described active area is fleet plough groove isolation structure.
Owing to having adopted above technical scheme, compared with prior art, the present invention has following beneficial effect: the manufacture method that the invention provides a kind of new fleet plough groove isolation structure, realize that specific small size zone makes more devices, adopt up-narrow and down-wide fleet plough groove isolation structure will increase the length of parasitic PNP or npn bipolar transistor base simultaneously, current amplification factor will reduce, make the more difficult generation of latch-up, thereby reach more effectively electricity isolation, to adapt to the needs of packaging density and the more and more higher process for fabrication of semiconductor device of integrated level.
The accompanying drawing explanation
The generalized section of each step corresponding construction that Figure 1A to Fig. 1 E is existing fleet plough groove isolation structure manufacture method.
The manufacture method flow chart of the fleet plough groove isolation structure that Fig. 2 provides for the embodiment of the present invention
The generalized section of each step corresponding construction of the shallow groove isolation structure manufacturing method that Fig. 3 A to Fig. 3 E provides for the embodiment of the present invention;
Embodiment
Below, by specific instantiation explanation embodiments of the present invention, those skilled in the art can understand other advantages of the present invention and effect easily by the disclosed content of this specification.The present invention can also be implemented or be applied by other different embodiment, and the every details in this specification also can be based on different viewpoints and application, carries out various modifications or change not deviating under spirit of the present invention.
It should be noted that, the diagram provided in the present embodiment only illustrates basic conception of the present invention in a schematic way, satisfy in graphic and only show with assembly relevant in the present invention but not component count, shape and size drafting while implementing according to reality, during its actual enforcement, kenel, quantity and the ratio of each assembly can be a kind of random change, and its assembly layout kenel also may be more complicated.
Please refer to shown in Fig. 2, the manufacture method flow chart of the fleet plough groove isolation structure that it provides for the embodiment of the present invention, the method comprises the following steps:
Step S200, provide semi-conductive substrate;
Step S201 forms dielectric layer on described Semiconductor substrate;
Step S202, the described dielectric layer of etching forms at least two grooves wide at the top and narrow at the bottom;
Step S203 forms interstitital texture in described groove; And
Step S204, change described interstitital texture into the material identical with described Semiconductor substrate, so that described interstitital texture is as active area, the dielectric layer between described interstitital texture is as fleet plough groove isolation structure.
Below in conjunction with generalized section, the present invention is described in more detail, has wherein meaned the preferred embodiments of the present invention, should be appreciated that those skilled in the art can revise the present invention described here, and still realize advantageous effects of the present invention.
At first, execution step S200 and S201, shown in Fig. 3 A, semi-conductive substrate 300 is provided, and forming successively dielectric layer 301, etching barrier layer 302 and hard mask layer 303 on described Semiconductor substrate 300, in the present embodiment, described Semiconductor substrate 300 is silicon substrate, described dielectric layer 301 is preferably silica material with hard mask layer 303, and described etching barrier layer 302 is preferably silicon nitride material.
Then, execution step S202, shown in Fig. 3 B, adopt dry etch process, and the described hard mask layer 303 of etching, etching barrier layer 302 and dielectric layer 301 form at least two the first grooves 305.Then, shown in Fig. 3 C, the dielectric layer 301 of the described hard mask layer 303 of etching, etching barrier layer 302 and segment thickness, form at least two the second grooves 306, described the second groove 306 is communicated with the first groove 305, and the cross-sectional width of described the second groove 306 is greater than the cross-sectional width of the first groove 305, that is, formed isolated groove wide at the top and narrow at the bottom (the first groove and relatively wide the second groove that comprise relative narrower).
As another embodiment of the present invention, described groove wide at the top and narrow at the bottom also can utilize following mode to form: at first, adopt the dielectric layer of dry etch process etching hard mask layer, etching barrier layer and segment thickness, form at least two the first relatively wide grooves; Then, the dielectric layer of described the first beneath trenches of etching, form the second groove of relative narrower, described the second groove is communicated with the first groove, and the cross-sectional width of described the second groove is less than the cross-sectional width of the first groove, formed equally groove wide at the top and narrow at the bottom (comprising the first relatively wide groove and relative narrower the second groove).
It should be noted that, the quantity of groove determines according to the number of the fleet plough groove isolation structure that needs in reality to arrange and the structure of device and the distribution of design, does not do concrete restriction herein.
Then, execution step S203, shown in Fig. 3 D, adopt chemical vapor deposition (CVD) technique to be filled into packing material in described the second groove 306 and the first groove 305, described packing material is for example polysilicon or amorphous silicon material, inevitably, described hard mask layer 303 tops have also formed packing material, then, utilize cmp (CMP) technique to remove the packing material of described hard mask layer 303 and top thereof, thereby formed interstitital texture 307, because the shape of groove is wide at the top and narrow at the bottom, thereby interstitital texture 307 is also structure wide at the top and narrow at the bottom.
Finally, execution step S204, shown in Fig. 3 E, utilize epitaxial growth method to change described interstitital texture 307 into the material identical with described Semiconductor substrate 300, described interstitital texture 307 is as active area 307 ', as fleet plough groove isolation structure 308, because interstitital texture 307 is structure wide at the top and narrow at the bottom, thereby described fleet plough groove isolation structure 308 is up-narrow and down-wide structure to dielectric layer 301 between active area 307 ' (with remaining etching barrier layer 302).
For example, adopt the method for laser molecular beam epitaxy growth (laser induce epi growth), temperature is 200 ℃ ~ 600 ℃, and the time is 5 seconds ~ 5 hours; Perhaps; adopt the method for solid-phase epitaxial growth (solid phase growth); temperature is 600 ℃ ~ 900 ℃; time is 1 hour ~ 90 hours; above-mentioned two kinds of methods all can change polysilicon or amorphous silicon material into monocrystalline silicon; certainly, other can change interstitital texture 307 into the material identical with described Semiconductor substrate 300 all in protection thought of the present invention, repeats no more herein.
Accordingly, the present invention also provides a kind of semiconductor device that utilizes said method to form, and shown in Fig. 3 E, described semiconductor device comprises:
Be formed at the dielectric layer 301 on described Semiconductor substrate 300;
The groove wide at the top and narrow at the bottom that the described dielectric layer 301 of etching forms;
Be formed at the active area 307 ' in described groove, the dielectric layer between described active area 307 ' is as fleet plough groove isolation structure 308, and described interstitital texture 307 is structure wide at the top and narrow at the bottom, thereby described fleet plough groove isolation structure 308 is up-narrow and down-wide structure.
The up-narrow and down-wide fleet plough groove isolation structure that the present invention adopts, to increase the length of parasitic PNP or npn bipolar transistor base than this new construction of original structure, current amplification factor will reduce, thereby make the more difficult generation of latch-up, reach effective electricity isolation purpose; Because fleet plough groove isolation structure 308 tops are narrower, than traditional fleet plough groove isolation structure, the area taken is less, more adapts to the needs of packaging density and the more and more higher process for fabrication of semiconductor device of integrated level simultaneously.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not for limiting the present invention.Any person skilled in the art scholar all can, under spirit of the present invention and category, be modified or be changed above-described embodiment.Therefore, such as in affiliated technical field, have and usually know that the knowledgeable, not breaking away from all equivalence modifications that complete under disclosed spirit and technological thought or changing, must be contained by claim of the present invention.
Claims (11)
1. the manufacture method of a fleet plough groove isolation structure, is characterized in that, comprising:
Semi-conductive substrate is provided;
Form dielectric layer on described Semiconductor substrate;
The described dielectric layer of etching forms at least two grooves wide at the top and narrow at the bottom;
Form interstitital texture in described groove; And
Change described interstitital texture into the material identical with described Semiconductor substrate, so that described interstitital texture is as active area, the dielectric layer between described interstitital texture is as fleet plough groove isolation structure.
2. the manufacture method of fleet plough groove isolation structure according to claim 1, is characterized in that, form dielectric layer on described Semiconductor substrate after, also comprises: form etching barrier layer and hard mask layer on described dielectric layer.
3. the manufacture method of fleet plough groove isolation structure according to claim 2, is characterized in that, the step that the described dielectric layer of etching forms at least two grooves wide at the top and narrow at the bottom comprises:
The described hard mask layer of etching, etching barrier layer and dielectric layer form at least two the first grooves; And
The dielectric layer of the described hard mask layer of etching, etching barrier layer and segment thickness, form at least two the second grooves, and described the second groove is communicated with the first groove, and the cross-sectional width of described the second groove is greater than the cross-sectional width of the first groove.
4. the manufacture method of fleet plough groove isolation structure according to claim 2, is characterized in that, the step that the described dielectric layer of etching forms at least two grooves wide at the top and narrow at the bottom comprises:
The dielectric layer of the described hard mask layer of etching, etching barrier layer and segment thickness, form at least two the first grooves; And
The dielectric layer of described the first beneath trenches of etching, form the second groove, and described the second groove is communicated with the first groove, and the cross-sectional width of described the second groove is less than the cross-sectional width of the first groove.
5. the manufacture method of fleet plough groove isolation structure according to claim 1, is characterized in that, adopts the described dielectric layer of dry etching to form at least two grooves wide at the top and narrow at the bottom.
6. the manufacture method of fleet plough groove isolation structure according to claim 1, is characterized in that, the step that forms interstitital texture in described groove comprises:
Deposit packing material in described groove He on described dielectric layer; And
Utilize the cmp skill to remove the packing material of described dielectric layer top, form interstitital texture.
7. the manufacture method of fleet plough groove isolation structure according to claim 6, is characterized in that, described Semiconductor substrate is silicon substrate, and described packing material is polysilicon or amorphous silicon material.
8. the manufacture method of fleet plough groove isolation structure according to claim 7, it is characterized in that, adopt the method for laser molecular beam epitaxy growth to change described interstitital texture into the material identical with described Semiconductor substrate, temperature is 200 ℃～600 ℃, and the time is 5 seconds～5 hours.
9. the manufacture method of fleet plough groove isolation structure according to claim 1, it is characterized in that, adopt the method for solid-phase epitaxial growth to change described interstitital texture into the material identical with described Semiconductor substrate, temperature is 600 ℃～900 ℃, and the time is 1 hour～90 hours.
10. the manufacture method of fleet plough groove isolation structure according to claim 2, is characterized in that, described dielectric layer and hard mask layer are silica, and described etching barrier layer is silicon nitride.
11. the semiconductor device that the manufacture method according to 1 to 10 any one forms comprises:
Semiconductor substrate;
Be formed at the dielectric layer on described Semiconductor substrate;
The groove wide at the top and narrow at the bottom that the described dielectric layer of etching forms; And
Be formed at the active area in described groove, the dielectric layer between described active area is fleet plough groove isolation structure.
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| CN1354495A (en) * | 2000-09-05 | 2002-06-19 | 索尼株式会社 | Semiconductor film and producing method and equipment, and method for producing single crystal film |
| CN1591780A (en) * | 2003-09-01 | 2005-03-09 | 旺宏电子股份有限公司 | Method for forming PN boundary and once programmable read-only memory structure and mfg. process |
| CN102044542A (en) * | 2009-10-09 | 2011-05-04 | 台湾积体电路制造股份有限公司 | Semiconductor device and manufacturing method thereof |
| CN102064129A (en) * | 2009-11-13 | 2011-05-18 | 英特赛尔美国股份有限公司 | Semiconductor process using mask openings of varying widths to form two or more device structures |
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- 2012-06-05 CN CN2012101831802A patent/CN103456675A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1354495A (en) * | 2000-09-05 | 2002-06-19 | 索尼株式会社 | Semiconductor film and producing method and equipment, and method for producing single crystal film |
| CN1353448A (en) * | 2000-11-11 | 2002-06-12 | 朱承基 | Method for crystallizing silicon layer |
| CN1591780A (en) * | 2003-09-01 | 2005-03-09 | 旺宏电子股份有限公司 | Method for forming PN boundary and once programmable read-only memory structure and mfg. process |
| CN102044542A (en) * | 2009-10-09 | 2011-05-04 | 台湾积体电路制造股份有限公司 | Semiconductor device and manufacturing method thereof |
| CN102064129A (en) * | 2009-11-13 | 2011-05-18 | 英特赛尔美国股份有限公司 | Semiconductor process using mask openings of varying widths to form two or more device structures |
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Application publication date: 20131218 |