CN107516635A - Fin formula field effect transistor and forming method thereof - Google Patents
Fin formula field effect transistor and forming method thereof Download PDFInfo
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- CN107516635A CN107516635A CN201610424017.9A CN201610424017A CN107516635A CN 107516635 A CN107516635 A CN 107516635A CN 201610424017 A CN201610424017 A CN 201610424017A CN 107516635 A CN107516635 A CN 107516635A
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- 238000000034 method Methods 0.000 title claims abstract description 78
- 230000005669 field effect Effects 0.000 title claims abstract description 53
- 238000000926 separation method Methods 0.000 claims abstract description 60
- 239000004065 semiconductor Substances 0.000 claims abstract description 51
- 239000000758 substrate Substances 0.000 claims abstract description 49
- 239000010410 layer Substances 0.000 claims description 136
- 238000002955 isolation Methods 0.000 claims description 85
- 239000011241 protective layer Substances 0.000 claims description 44
- 239000000463 material Substances 0.000 claims description 41
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 23
- 239000000377 silicon dioxide Substances 0.000 claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 4
- 229910052732 germanium Inorganic materials 0.000 claims description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 21
- 230000015572 biosynthetic process Effects 0.000 description 13
- 238000005530 etching Methods 0.000 description 4
- 125000004122 cyclic group Chemical group 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 239000002362 mulch Substances 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000003701 mechanical milling Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- General Physics & Mathematics (AREA)
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- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A kind of fin formula field effect transistor and forming method thereof, wherein method includes：Semiconductor substrate is provided, there is the first initial fin in the Semiconductor substrate；The first groove is formed in the described first initial fin, first groove runs through the first initial fin along perpendicular to the first initial fin bearing of trend；Epitaxial layer is formed in the first initial fin side wall that the first groove exposes；After forming epitaxial layer, full separation layer is filled in first groove；After forming separation layer, the grid structure of the first initial fin is developed across；Source and drain doping area is formed in the first initial fin of the grid structure both sides.Methods described improves the performance of fin formula field effect transistor.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly to a kind of fin formula field effect transistor and forming method thereof.
Background technology
MOS transistor is one of most important element in modern integrated circuits.The basic structure of MOS transistor includes：Half
Conductor substrate；Positioned at the grid structure of semiconductor substrate surface, source region and position in the Semiconductor substrate of grid structure side
Drain region in grid structure opposite side Semiconductor substrate.The operation principle of MOS transistor is：By applying electricity in grid structure
Pressure, is adjusted by the electric current of grid structure bottom channel to produce switching signal.
With the development of semiconductor technology, the MOS transistor of traditional plane formula dies down to the control ability of channel current,
Cause serious leakage current.And fin formula field effect transistor (Fin FET) is a kind of emerging multi-gate device, protrusion is generally comprised
In the fin of semiconductor substrate surface, the top surface of fin described in covering part and the grid structure of sidewall surfaces, positioned at grid
Source region in the fin of pole structure side and the drain region in the fin of grid structure opposite side.
However, the poor-performing for the fin formula field effect transistor that prior art is formed.
The content of the invention
The present invention solves the problems, such as to be to provide a kind of fin formula field effect transistor and forming method thereof, to improve fin field effect
Answer the performance of transistor.
To solve the above problems, the present invention provides a kind of forming method of fin formula field effect transistor, including：Offer is partly led
Body substrate, there is the first initial fin in the Semiconductor substrate；The first groove is formed in the described first initial fin, it is described
First groove runs through the first initial fin along perpendicular to the first initial fin bearing of trend；First exposed in the first groove
Initial fin side wall forms epitaxial layer；After forming epitaxial layer, full separation layer is filled in first groove；Form separation layer
Afterwards, it is developed across the grid structure of the first initial fin；Source and drain is formed in the first initial fin of the grid structure both sides
Doped region.
Optionally, the material of the epitaxial layer is monocrystalline silicon, monocrystalline germanium or monocrystalline SiGe.
Optionally, the technique for forming the epitaxial layer is epitaxial growth technology.
Optionally, the growth rate of the epitaxial layer is the angstrom min of 100 angstrom mins~2000.
Optionally, the material of the separation layer is silica, silicon oxynitride or silicon oxide carbide.
Optionally, the material of the separation layer is high K silica.
Optionally, the top surface of the described first initial fin has protective layer；First groove also extends to protection
In layer and run through protective layer；The forming method of the fin formula field effect transistor also includes：Formed after separation layer and forming grid
Before the structure of pole, the protective layer is removed.
Optionally, the material of the protective layer is silicon nitride, titanium nitride or silicon oxynitride.
Optionally, also there is the isolation structure of the first initial fin side wall of covering in the Semiconductor substrate；First groove
Also extend in isolation structure；The forming method of the fin formula field effect transistor also includes：Formed separation layer after, it is described every
From opening is formed in structure, described be open exposes the partial sidewall of the first initial fin both sides, and the part side exposed
Wall is parallel to the first initial fin bearing of trend；After forming opening, protective layer is removed；After removing protective layer, in outs open
The grid structure of the first initial fin is developed across with the top surface of the first initial fin of part.
Optionally, in addition to：The second initial fin, the second initial fin are formd while the first initial fin is formed
Both ends be connected respectively with the first adjacent initial fin, the first initial fin and the second initial fin structure annular in shape；In shape
During isolation structure, the second initial fin is removed.
Optionally, it is self-alignment duplex pattern chemical industry skill to form the first initial fin and the technique of the second initial fin.
Optionally, forming the method for the isolation structure includes：The first initially isolation is formed on the semiconductor substrate
Structure, the first initial isolation structure cover the side wall of the first initial fin and the second initial fin；Remove the second initial fin
Portion, form the second groove；After forming the second groove, being filled in second groove expires the second initial isolation structure, at the beginning of second
Beginning isolation structure and the first initial isolation structure form isolation structure.
Optionally, in addition to：The the first initial fin of part for removing the second initial fin and being connected with the second initial fin
Portion, form the second groove.
Optionally, forming the method for the isolation structure includes：The first initially isolation is formed on the semiconductor substrate
Structure, the first initial isolation structure cover the side wall of the first initial fin and the second initial fin；Remove the second initial fin
Portion and the first initial fin of part being connected with the second initial fin, form the second groove, and second groove exposes the
The partial sidewall of one initial fin；After forming the second groove, the first initial isolation structure forms isolation structure.
Optionally, the protective layer is located at the top surface of the first initial fin and the second initial fin；The fin field
The forming method of effect transistor also includes：While the second initial fin is removed, the second initial fin top surface is removed
Protective layer.
Optionally, the protective layer is located at the top surface of the first initial fin and the second initial fin；The fin field
The forming method of effect transistor also includes：In the part first for removing the second initial fin and being connected with the second initial fin
While initial fin, the initial fin top of protective layer and corresponding part first of the second initial fin top surface is removed
The protective layer on portion surface.
Optionally, in addition to：While epitaxial layer is formed, in the first initial fin side that second groove exposes
Wall forms additional epitaxial layers.
The present invention also provides a kind of fin formula field effect transistor, including：Semiconductor substrate, have in the Semiconductor substrate
First initial fin；First groove, in the first initial fin；Epitaxial layer, exposed positioned at the first groove first initial
Fin side wall；Separation layer, in the first groove；Grid structure, across the first initial fin；Source and drain doping area, positioned at grid
In first initial fin of structure both sides.
Compared with prior art, technical scheme has advantages below：
The forming method of fin formula field effect transistor provided by the invention, first due to being exposed in the first groove are initial
Fin side wall forms epitaxial layer, hence in so that on the bearing of trend of the first initial fin, the first groove both sides first at the beginning of
The increase of total effective dimensions of beginning fin and epitaxial layer.In the case where the density of grid structure is constant so that source and drain doping area
Form space increase.Because the formation space in source and drain doping area increases so that the source and drain doping between grid structure and separation layer
The pattern in area is influenceed smaller by growing space.So as to which the source and drain doping area reduced between grid structure and separation layer collapses
Degree.Accordingly, stress of the source and drain doping area to respective channels is improved.So that the performance of fin formula field effect transistor
It is improved.
Fin formula field effect transistor provided by the invention, the first initial fin side wall tool due to being exposed in the first groove
There is epitaxial layer, hence in so that on the bearing of trend of the first initial fin, the first initial fin and extension of the first groove both sides
Total effective dimensions increase of layer.In the case where the density of grid structure is constant so that the formation space increase in source and drain doping area.
Because the formation space in source and drain doping area increases so that the pattern in the source and drain doping area between grid structure and separation layer is given birth to
The influence of long spacing is smaller.The degree collapsed so as to the source and drain doping area reduced between grid structure and separation layer.Accordingly,
Improve stress of the source and drain doping area to respective channels.So that the performance of fin formula field effect transistor is improved.
Brief description of the drawings
Fig. 1 to Fig. 3 is a kind of structural representation of fin formula field effect transistor forming process；
Fig. 4 to Figure 26 is the structural representation of fin formula field effect transistor forming process in one embodiment of the invention.
Embodiment
As described in background, the poor-performing of the fin formula field effect transistor formed in the prior art.
Fig. 1 to Fig. 3 is a kind of structural representation of fin formula field effect transistor forming process.
With reference to being the schematic diagram that is obtained along A-A1 lines of cut in Fig. 1 with reference to figure 1 and Fig. 2, Fig. 2, there is provided Semiconductor substrate
100, there is initial fin in Semiconductor substrate 100；Initial fin is cut off along the surface normal direction of Semiconductor substrate 100, will
Initial fin is divided into the first fin 110 and the second fin 111；Isolation structure and separation layer are formed on a semiconductor substrate 100
120, the isolation structure is between adjacent first fin 110, and between adjacent second fin 111, and isolation structure
Top surface is located at the first fin 110 and second less than the first fin 110 and the top surface of the second fin 111, separation layer 120
Between fin 111, and the top surface of separation layer 120 is higher than the first fin 110 and the top surface of the second fin 111.
With reference to figure 3, be developed across the first grid structure 130 of the first fin 110 and across the second fin 111
Two grid structures 131；The first source and drain doping area 140 is formed in the first fin 110 of the both sides of first grid structure 130,
The second source and drain doping area 141 is formed in second fin 111 of two grid structure both sides 131.
The step of forming the first source and drain doping area 140 be：The shape in the first fin 110 of the both sides of first grid structure 130
Into the first depression；The first source and drain material layer is formed in the described first depression, so as to form the first source and drain doping area 140.
The step of forming the second source and drain doping area 141 be：The shape in the second fin 111 of the both sides of second grid structure 131
Into the second depression；The second source and drain material layer is formed in the described second depression, so as to form the second source and drain doping area 141.
However, the poor-performing for the fin formula field effect transistor that the above method is formed, shows：First grid structure 130
The second source and drain between the first source and drain doping area 140, second grid structure 131 and separation layer 120 between separation layer 120 is mixed
Miscellaneous area 141 forms serious collapse phenomenon, and the stress of respective channels is reduced, it has been investigated that, reason is：
With the continuous reduction of characteristic size, the distance between adjacent first grid structure 130 and adjacent second grid
The distance between structure 131 constantly reduces so that the growing space in the first source and drain doping area 140 and the second source and drain doping area 141
Reduce.
In the case of less in the growing space in the first source and drain doping area 140 and the second source and drain doping area 141, first grid
Between the first source and drain doping area 140 and second grid structure 131 and separation layer 120 between structure 130 and separation layer 120
The pattern in the second source and drain doping area 141 had a great influence by growing space.
Specifically, the side side wall of the first depression between first grid structure 130 and separation layer 120 exposes the first fin
Portion 110, and opposite side side wall exposes separation layer 120.Forming first between first grid structure 130 and separation layer 120
During source and drain material layer, it is only capable of being used as the growth first grid using the first fin 110 that the first depression side side wall is exposed
The seed of the first source and drain material layer between pole structure 130 and separation layer 120, cause close to the side of first grid structure 130
The growth rate of first source and drain material layer is more than the growth rate of the first source and drain material layer close to the side of separation layer 120.So as to
Cause the first source and drain doping area 140 between first grid structure 130 and separation layer 120 to be formed seriously to collapse.
Accordingly, the second source and drain doping area 141 between second grid structure 131 and separation layer 120 is caused to be formed seriously
Collapse.
Due to the first source and drain doping area 140 between first grid structure 130 and separation layer 120, second grid structure 131
The second source and drain doping area 141 between separation layer 120 forms serious collapse phenomenon, causes to subtract the stress of respective channels
It is small, so as to cause the degradation of fin formula field effect transistor.
On this basis, the present invention provides a kind of forming method of fin formula field effect transistor, including：Semiconductor lining is provided
Bottom, there is the first initial fin in the Semiconductor substrate；Form the first groove in the described first initial fin, described first
Groove runs through the first initial fin along perpendicular to the first initial fin bearing of trend；Exposed in the first groove first initial
Fin side wall forms epitaxial layer；After forming epitaxial layer, full separation layer is filled in first groove；After forming separation layer, shape
Into the grid structure across the first initial fin；Source and drain doping is formed in the first initial fin of the grid structure both sides
Area.
The first initial fin side wall due to being exposed in the first groove forms epitaxial layer, hence in so that initial first
On the bearing of trend of fin, total effective dimensions increase of the first initial fin and epitaxial layer of the first groove both sides.In grid knot
In the case that the density of structure is constant so that the formation space increase in source and drain doping area.So that between grid structure and separation layer
The pattern in source and drain doping area influenceed by growing space it is smaller so that the performance of fin formula field effect transistor is carried
It is high.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Fig. 4 to Figure 26 is the structural representation of fin formula field effect transistor forming process in one embodiment of the invention.
With reference to reference to figure 4, Fig. 5 and Fig. 6, Fig. 5 be along in Fig. 4 A2-A3 lines of cut obtain profile, Fig. 6 be along
The profile that A4-A5 lines of cut obtain in Fig. 4, there is provided Semiconductor substrate 200, first is formed in the Semiconductor substrate 200
Initial 211 and second initial fin 212 of fin, the both ends of the second initial fin 212 respectively with the first adjacent initial fin 211
Connection, the first initial initial 212 structure in closed ring shape of fin of fin 211 and second.
The Semiconductor substrate 200 provides technique platform to be subsequently formed fin formula field effect transistor.
In the present embodiment, the material of the Semiconductor substrate 200 is monocrystalline silicon.The Semiconductor substrate 200 can also be
Polysilicon or non-crystalline silicon.The material of the Semiconductor substrate 200 can also be the semi-conducting materials such as germanium, SiGe, GaAs.
In the present embodiment, the first initial 211 and second initial fin 212 of fin is served as a contrast by the graphical semiconductor
Bottom 200 and formed.In other embodiments, Ke Yishi：Fin material layer is formed on the semiconductor substrate, then graphically
The fin material layer, so as to form the first initial fin and the second initial fin.
In the present embodiment, the first initial initial 212 rectangular cyclic structure of fin of fin 211 and second.In other implementations
In example, the first initial fin and the second initial fin can also be square cyclic structure or circular annular form structure, and first is initial
Fin and the second initial fin can also be in the cyclic structure of irregular shape.
It should be noted that it is projected in the first initial fin 211 in the projecting figure on the surface of Semiconductor substrate 200, institute
The length direction for stating projecting figure is the bearing of trend of the first initial fin 211.
In the present embodiment, the technique for forming the first initial 211 and second initial fin 212 of fin is self-alignment duplex pattern
Chemical industry skill, specific step include：Sacrifice layer (not shown) is formed on semiconductor substrate 200, in the side wall of the sacrifice layer
Form side wall (not shown)；After forming side wall, sacrifice layer is removed；Then using the side wall as mask etching Semiconductor substrate 200,
Form the first initial 211 and second initial fin 212 of fin.
In the present embodiment, protective layer 220 is formed while the first initial 211 and second initial fin 212 of fin are formed,
The protective layer 220 is located at the top surface of the first initial 211 and second initial fin 212 of fin.
It should be noted that illustrating for convenience, partial protection layer 220 is not shown in Fig. 4, so as to which part first is initial
The top surface of the initial fin 212 of the top surface of fin 211 and part second is exposed.
Specifically, before sacrifice layer is formed, the protected material bed of material (not shown) is formed in the Semiconductor substrate 200；
Sacrifice layer is formed in the Semiconductor substrate 200 and the protected material bed of material；After forming side wall, side wall is located on the protected material bed of material；
Using the side wall as the mask etching protected material bed of material and Semiconductor substrate 200, the first initial 211 and second initial fin of fin is formed
Portion 212 and the protective layer 220 positioned at the first initial initial top surface of fin 212 of fin 211 and second.
The material of the protective layer 220 is silicon nitride, titanium nitride or silicon oxynitride.
The protective layer 220 is act as：During epitaxial layer is subsequently formed, the first initial fin 211 of protection
Top surface, the top surface avoided in the first initial fin 211 form the material of epitaxial layer；(2) it is being subsequently formed separation layer
During so that the top surface of separation layer flushes with the top surface of protective layer, after removing protective layer so that separation layer
Top surface is higher than the top surface of the first initial fin 211.
Then, isolation structure is formed；And during isolation structure is formed, remove the second initial fin.
Lower mask body introduces the forming process of isolation structure.
With reference to reference to figure 7, Fig. 8 and Fig. 9, Fig. 7, to form schematic diagram on the basis of 4, Fig. 8 is to be cut along A2-A3 in Fig. 7
The schematic diagram that line obtains, Fig. 9 are the shape in the Semiconductor substrate 200 along the schematic diagram of A4-A5 lines of cut acquisition in Fig. 7
Into the first initial isolation structure 230, the first initial isolation structure 230 covers the first initial 211 and second initial fin of fin
The side wall in portion 212.
In the present embodiment, the first initial isolation structure 230 covers the first initial 211 and second initial fin of fin
212 side wall, and expose the top surface and side wall of protective layer 220.In other embodiments, the described first initial isolation junction
The top surface and side wall of structure also protective mulch, or the partial sidewall of the first initial isolation structure also protective mulch.
The material of first initial isolation structure 230 is silica, silicon oxynitride or silicon oxide carbide.
In the present embodiment, forming the method for the first initial isolation structure 230 includes：Using depositing operation, such as plasma
Chemical vapor deposition method, low-pressure chemical vapor deposition process or sub-atmospheric pressure chemical vapor deposition method, form covering half
Conductor substrate 200, the first initial fin 211, the first initial isolation structure film of the second initial fin 212 and protective layer 220
(not shown)；Remove the first initial isolation structure higher than the first initial initial top surface of fin 212 of fin 211 and second
Film, form the first initial isolation structure 230.
In the present embodiment, remove first initial higher than the first initial initial top surface of fin 212 of fin 211 and second
The method of isolation structure film includes：It is initial higher than the part first of the top surface of protective layer 220 that technique removal is removed using first
Isolation structure film, the first removal technique have the first precision；After carrying out the first removal technique, it is surplus to remove technique removal using second
Remaining the first initial isolation structure film higher than the first initial initial top surface of fin 212 of fin 211 and second, second removes
Technique has the second precision, and the second precision is more than the first precision.
The first removal technique can be chemical mechanical milling tech.
The second removal technique can be to be etched back to technique.
It is initial higher than the part first of the top surface of protective layer 220 due to removing technique removal using the first of the first precision
Isolation structure film, and the first precision is relatively low, therefore can be carried out with faster process rate, add process efficiency.Due to adopting
It is higher than the first initial initial top table of fin 212 of fin 211 and second with the second removal technique removal of the second precision is remaining
The first initial isolation structure film in face, enabling accurately control the thickness of the first initial isolation structure 230 so that at the beginning of first
Beginning isolation structure 230 covers the side wall of the first initial 211 and second initial fin 212 of fin, and exposes the top of protective layer 220
Portion surface and side wall.
With reference to being the schematic diagram formed on the basis of Fig. 7 with reference to figure 10 and Figure 11, Figure 10, Figure 11 is along A2- in Figure 10
The schematic diagram that A3 lines of cut obtain, remove the second initial fin 212 (with reference to reference to figure 7, Fig. 8 and Fig. 9) and with it is second initial
The initial fin 211 in part first that fin 212 connects, form the second groove 240.
In the initial fin 211 in part first for removing the second initial fin 212 and being connected with the second initial fin 212
While, the initial fin 211 of protective layer 220 and corresponding part first for removing the second initial top surface of fin 212 pushes up
The protective layer 220 on portion surface.
In the present embodiment, second groove 240 exposes the partial sidewall of the first initial fin 211.
It should be noted that in other embodiments, it can only remove the second initial fin and form the second groove, now
Second groove will not expose the side wall of the first initial fin.While the second initial fin of removal forms the second groove,
Remove the protective layer of the second initial fin top surface.
With reference to being the schematic diagram formed on the basis of Figure 10 with reference to figure 12 and Figure 13, Figure 12, Figure 13 is along A2- in Figure 12
The schematic diagram that A3 lines of cut obtain, fills full second initial isolation structure 250 in second groove 240, second initially every
Isolation structure is formed from 250 and first initial isolation structure 230 of structure.
The material of second initial isolation structure 250 is silica, silicon oxynitride or silicon oxide carbide.
It should be noted that in other embodiments, the partial sidewall of the first initial fin is exposed in the second groove
In the case of, without forming the second initial isolation structure in the second groove, only the first initial isolation structure forms isolation structure.
It should be noted that in other embodiments, it is initial second can not to be formed simultaneously in the first initial fin of formation
Fin.Accordingly, during isolation structure is formed, without removing the second initial fin.In the case, isolation junction is formed
The method of structure is：Using depositing operation, such as plasma activated chemical vapour deposition technique, low-pressure chemical vapor deposition process or Asia
Sub-atmospheric CVD technique, in Semiconductor substrate and the first initial fin formed isolation structure material layer, it is described every
Top surface from structural material is higher than the top surface of the first initial fin；Removal is higher than the first initial fin top surface
Isolation structure material layer, formed isolation structure.
With reference to being the schematic diagram formed on the basis of Figure 12 with reference to figure 14, Figure 15 and Figure 16, Figure 14, Figure 15 is along Figure 14
The schematic diagram that middle A2-A3 lines of cut obtain, Figure 16 is the schematic diagram obtained along A4-A5 lines of cut in Figure 14, in the isolation
The first groove 260 is formed in structure, 220 and first initial fin 211 of protective layer, first groove 260 is along perpendicular to
The bearing of trend of one initial fin 211 runs through the first initial fin 211.
Mask layer (not shown) is formed on the isolation structure and protective layer 220, the mask layer defines to be formed
The first groove 260 position, the material of the mask layer can be photoresist；Using the mask layer as mask, using it is each to
Different in nature dry etch process etching isolation structure, 220 and first initial fin 211 of protective layer are until expose Semiconductor substrate
200 surface, form the first groove 260；Then the mask layer is removed.
It should be noted that in the present embodiment, the first groove 260 exposes the surface of Semiconductor substrate 200.In other implementations
In example, the first groove does not expose the surface of Semiconductor substrate, it is necessary to using the mask layer as mask, using anisotropic dry
The first initial fin of etching technics etched portions isolation structure, protective layer and part.
Due to before the first groove 260 is formed, foring isolation structure, the isolation structure covers the first initial fin
211 side wall, relatively flat surface is provided to form the mask layer of definition the first groove 260 position, is advantageous to described cover
The formation of film layer.
It should be noted that in other embodiments, before the first groove is formed, it can not form isolation structure.
While separation layer is subsequently formed between the adjacent first initial fin on the first initial fin bearing of trend
Isolation structure is formed in Semiconductor substrate, or after separation layer is formed, on the first initial fin bearing of trend
Isolation structure is formed in Semiconductor substrate between adjacent first initial fin.
If after separation layer is formed, isolation structure is formed, the top surface of isolation structure is less than the first initial fin 211
Top surface.
With reference to being the schematic diagram formed on the basis of Figure 14 with reference to figure 17 and Figure 18, Figure 17, Figure 18 is along A2- in Figure 17
The schematic diagram that A3 lines of cut obtain, epitaxial layer 280 is formed in the first initial side wall of fin 211 that the first groove 260 exposes.
The material of the epitaxial layer 280 is monocrystalline silicon, monocrystalline germanium or monocrystalline SiGe.
The technique for forming the epitaxial layer 280 is epitaxial growth technology.
The growth rate of the epitaxial layer 280 is 100 angstroms/min~2000 angstrom/min.The growth speed of the epitaxial layer 280
Rate selects the meaning of this scope to be：If the growth rate of the epitaxial layer 280 is too small, cause process efficiency relatively low；It is if described
The growth rate of epitaxial layer 280 is excessive, causes chi of the epitaxial layer 280 on the first initial bearing of trend of fin 211 whard to control
Very little, the epitaxial layer 280 of the both sides of the first groove 260 is easily connected with each other.
The first initial side wall of fin 211 due to being exposed in the first groove 260 forms epitaxial layer 280 so that first
On the initial bearing of trend of fin 211,280 total effective chi of the first initial fin 211 and epitaxial layer of the both sides of the first groove 260
Very little increase.
It should be noted that in other embodiments, the situation of isolation structure is only made up of the first initial isolation structure
Under, while epitaxial layer is formed, additional epitaxial can be also formed in the first initial fin side wall that second groove exposes
Layer (not shown).
The material and formation process of the additional epitaxial layers are no longer described in detail with reference to the material and formation process of epitaxial layer.
With reference to being the schematic diagram formed on the basis of Figure 17 with reference to figure 19, Figure 20 and Figure 21, Figure 19, Figure 20 is along Figure 19
The schematic diagram that middle A2-A3 lines of cut are formed, Figure 21 are the schematic diagram formed along A4-A5 lines of cut in Figure 19, form epitaxial layer
After 280, full separation layer 290 is filled in first groove 260.
Separation layer 290 by the epitaxial layer 280 of the opposite side of 280 and first groove of epitaxial layer 260 of the side of the first groove 260 every
From.
The material of the separation layer 290 is silica, silicon oxynitride or silicon oxide carbide.
When the material of the separation layer 290 is silica, high K (K is more than 3.9) silica can be selected.So that isolation
The isolation performance enhancing of layer 290.
In the present embodiment, the top surface of the separation layer 290 flushes with the top surface of protective layer 220.So that isolation
The top surface of layer 290 is higher than the top surface of the first initial fin 211.Subsequently led in the top surface formation of separation layer 290
After electric structure, conductive structure is in larger distance with the first initial top surface of fin 211, avoids conductive structure and the first initial fin
Short circuit occurs for portion 211.
In other embodiments, the top surface of the separation layer is higher than the top surface of the first initial fin and less than guarantor
The top surface of sheath, or separation layer top surface be higher than protective layer top surface.
It should be noted that in other embodiments, the situation of isolation structure is only made up of the first initial isolation structure
Under, the material that can also fill full separation layer while expiring separation layer in the second groove is filled in the first groove.
Then, with reference to being the schematic diagram formed on the basis of Figure 19 with reference to figure 22 and Figure 23, Figure 22, Figure 23 is along Figure 22
The schematic diagram that middle A2-A3 lines of cut obtain, forms opening 291 in the isolation structure, and the opening 291 is exposed at the beginning of first
The partial sidewall of the both sides of beginning fin 211, and the partial sidewall exposed is parallel to the first initial bearing of trend of fin 211；Shape
Into after opening 291, remove protective layer 220 (with reference to figure 19, Figure 20 and Figure 21).
Then, with reference to being the schematic diagram formed on the basis of 22 with reference to figure 24 and Figure 25, Figure 24, Figure 25 is along in Figure 24
The schematic diagram that A2-A3 lines of cut obtain, is developed across in the top surface of the initial fin 211 of outs open 291 and part first
The grid structure 293 of first initial fin 211.
With reference to figure 26, Figure 26 is the schematic diagram formed on the basis of Figure 25, the first initial fin in the both sides of grid structure 293
Source and drain doping area 295 is formed in portion 211.
Formed source and drain doping area 295 the step of be：Formed in the first initial fin 211 of the both sides of grid structure 293 recessed
Fall into；Source and drain material layer is formed in the depression, so as to form source and drain doping area 295.
The first initial side wall of fin 211 due to being exposed in the first groove 260 (with reference to figure 15) forms epitaxial layer
280, hence in so that on the bearing of trend of the first initial fin 211, the first initial He of fin 211 of the both sides of the first groove 260
Total effective dimensions increase of epitaxial layer 280.In the case where the density of grid structure 293 is constant so that source and drain doping area 295
Form space increase.Because the formation space in source and drain doping area 295 increases so that between grid structure 293 and separation layer 290
The pattern in source and drain doping area 295 is influenceed smaller by growing space.So as to reduce grid structure 293 and separation layer 290 it
Between the degree that collapses of source and drain doping area 295.Accordingly, stress of the source and drain doping area 295 to respective channels is improved.So that
The performance for obtaining fin formula field effect transistor is improved.
Accordingly, the present invention also provides a kind of using above method formation fin formula field effect transistor, with reference to figure 26, bag
Include：Semiconductor substrate 200, there is the first initial fin 211 in the Semiconductor substrate 200；First groove 260 is (with reference to reference
Figure 14, Figure 15 and Figure 16), in the first initial fin 211；Epitaxial layer 280, first exposed positioned at the first groove 260
The initial side wall of fin 211；Separation layer 290, in the first groove 260；Grid structure 293, across the first initial fin 211；
Source and drain doping area 295, in the first initial fin 211 of the both sides of grid structure 293.
Fin formula field effect transistor provided by the invention, the first initial fin side wall tool due to being exposed in the first groove
There is epitaxial layer, hence in so that on the bearing of trend of the first initial fin, the first initial fin and extension of the first groove both sides
Total effective dimensions increase of layer.In the case where the density of grid structure is constant so that the formation space increase in source and drain doping area.
Because the formation space in source and drain doping area increases so that the pattern in the source and drain doping area between grid structure and separation layer is given birth to
The influence of long spacing is smaller.The degree collapsed so as to the source and drain doping area reduced between grid structure and separation layer.Accordingly,
Improve stress of the source and drain doping area to respective channels.So that the performance of fin formula field effect transistor is improved.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, this is not being departed from
In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
The scope of restriction is defined.
Claims (18)
- A kind of 1. forming method of fin formula field effect transistor, it is characterised in that including：Semiconductor substrate is provided, there is the first initial fin in the Semiconductor substrate；The first groove is formed in the described first initial fin, first groove is along perpendicular to the first initial fin extension side To through the first initial fin；Epitaxial layer is formed in the first initial fin side wall that the first groove exposes；After forming epitaxial layer, full separation layer is filled in first groove；After forming separation layer, the grid structure of the first initial fin is developed across；Source and drain doping area is formed in the first initial fin of the grid structure both sides.
- 2. the forming method of fin formula field effect transistor according to claim 1, it is characterised in that the material of the epitaxial layer Expect for monocrystalline silicon, monocrystalline germanium or monocrystalline SiGe.
- 3. the forming method of fin formula field effect transistor according to claim 1, it is characterised in that form the epitaxial layer Technique be epitaxial growth technology.
- 4. the forming method of fin formula field effect transistor according to claim 1, it is characterised in that the life of the epitaxial layer Long speed is the angstrom min of 100 angstrom mins~2000.
- 5. the forming method of fin formula field effect transistor according to claim 1, it is characterised in that the material of the separation layer Expect for silica, silicon oxynitride or silicon oxide carbide.
- 6. the forming method of fin formula field effect transistor according to claim 5, it is characterised in that the material of the separation layer Expect for high K silica.
- 7. the forming method of fin formula field effect transistor according to claim 1, it is characterised in that the first initial fin The top surface in portion has protective layer；First groove also extends in protective layer and runs through protective layer；The fin field effect Answering the forming method of transistor also includes：Formed after separation layer and before grid structure is formed, remove the protective layer.
- 8. the forming method of fin formula field effect transistor according to claim 7, it is characterised in that the material of the protective layer Expect for silicon nitride, titanium nitride or silicon oxynitride.
- 9. the forming method of fin formula field effect transistor according to claim 7, it is characterised in that the Semiconductor substrate On also have covering the first initial fin side wall isolation structure；First groove is also extended in isolation structure；The forming method of the fin formula field effect transistor also includes：After forming separation layer, opening is formed in the isolation structure, described be open exposes the portion of the first initial fin both sides Divide side wall, and the partial sidewall exposed is parallel to the first initial fin bearing of trend；After forming opening, protective layer is removed；After removing protective layer, the top surface with the first initial fin of part in outs open is developed across the first initial fin Grid structure.
- 10. the forming method of fin formula field effect transistor according to claim 9, it is characterised in that also include：Formed Form the second initial fin while first initial fin, the both ends of the second initial fin respectively with the first adjacent initial fin Portion connects, the first initial fin and the second initial fin structure annular in shape；During isolation structure is formed, remove at the beginning of second Beginning fin.
- 11. the forming method of fin formula field effect transistor according to claim 10, it is characterised in that it is initial to form first The technique of fin and the second initial fin is self-alignment duplex pattern chemical industry skill.
- 12. the forming method of fin formula field effect transistor according to claim 10, it is characterised in that form the isolation The method of structure includes：The first initial isolation structure is formed on the semiconductor substrate, and the first initial isolation structure covers the first initial fin Portion and the side wall of the second initial fin；The second initial fin is removed, forms the second groove；After forming the second groove, fill full second initial isolation structure in second groove, the second initial isolation structure and First initial isolation structure forms isolation structure.
- 13. the forming method of fin formula field effect transistor according to claim 12, it is characterised in that also include：Remove Second initial fin and the first initial fin of part being connected with the second initial fin, form the second groove.
- 14. the forming method of fin formula field effect transistor according to claim 10, it is characterised in that form the isolation The method of structure includes：The first initial isolation structure is formed on the semiconductor substrate, and the first initial isolation structure covers the first initial fin Portion and the side wall of the second initial fin；The the first initial fin of part for removing the second initial fin and being connected with the second initial fin, form the second groove, institute State the partial sidewall that the second groove exposes the first initial fin；After forming the second groove, the first initial isolation structure forms isolation structure.
- 15. the forming method of fin formula field effect transistor according to claim 12, it is characterised in that the protective layer position In the first initial fin and the top surface of the second initial fin；The forming method of the fin formula field effect transistor also includes： While the second initial fin is removed, the protective layer of the second initial fin top surface is removed.
- 16. the forming method of the fin formula field effect transistor according to claim 13 or 14, it is characterised in that the protection Layer is positioned at the first initial fin and the top surface of the second initial fin；The forming method of the fin formula field effect transistor is also wrapped Include：While the second initial fin and the first initial fin of part being connected with the second initial fin is removed, second is removed The protective layer of the initial fin top surface of protective layer and corresponding part first of initial fin top surface.
- 17. the forming method of fin formula field effect transistor according to claim 14, it is characterised in that also include：In shape While into epitaxial layer, additional epitaxial layers are formed in the first initial fin side wall that second groove exposes.
- A kind of 18. fin formula field effect transistor formed according to claim 1 to 17 any one, it is characterised in that including：Semiconductor substrate, there is the first initial fin in the Semiconductor substrate；First groove, in the first initial fin；Epitaxial layer, the first initial fin side wall exposed positioned at the first groove；Separation layer, in the first groove；Grid structure, across the first initial fin；Source and drain doping area, in the first initial fin of grid structure both sides.
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| CN102623487A (en) * | 2011-01-26 | 2012-08-01 | 中国科学院微电子研究所 | Semiconductor device and method for manufacturing the same |
| US20130264643A1 (en) * | 2010-05-06 | 2013-10-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for fabricating a strained structure |
| CN104051270A (en) * | 2013-03-15 | 2014-09-17 | 三星电子株式会社 | Methods of forming semiconductor devices using hard mask layers |
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| CN101312191A (en) * | 2007-05-25 | 2008-11-26 | 台湾积体电路制造股份有限公司 | Semi-conductor construction and forming method thereof |
| US20130264643A1 (en) * | 2010-05-06 | 2013-10-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for fabricating a strained structure |
| CN102623487A (en) * | 2011-01-26 | 2012-08-01 | 中国科学院微电子研究所 | Semiconductor device and method for manufacturing the same |
| CN104051270A (en) * | 2013-03-15 | 2014-09-17 | 三星电子株式会社 | Methods of forming semiconductor devices using hard mask layers |
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