CN114724944A - Method for manufacturing semiconductor structure - Google Patents
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- CN114724944A CN114724944A CN202210541143.8A CN202210541143A CN114724944A CN 114724944 A CN114724944 A CN 114724944A CN 202210541143 A CN202210541143 A CN 202210541143A CN 114724944 A CN114724944 A CN 114724944A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 29
- 238000000034 method Methods 0.000 title claims description 38
- 239000000758 substrate Substances 0.000 claims abstract description 54
- 238000005530 etching Methods 0.000 claims abstract description 49
- 230000004888 barrier function Effects 0.000 claims abstract description 35
- 150000004767 nitrides Chemical class 0.000 claims description 29
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 claims description 12
- 239000007789 gas Substances 0.000 claims description 11
- CPELXLSAUQHCOX-UHFFFAOYSA-N Hydrogen bromide Chemical compound Br CPELXLSAUQHCOX-UHFFFAOYSA-N 0.000 claims description 8
- RWRIWBAIICGTTQ-UHFFFAOYSA-N difluoromethane Chemical compound FCF RWRIWBAIICGTTQ-UHFFFAOYSA-N 0.000 claims description 8
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 claims description 6
- 229910000042 hydrogen bromide Inorganic materials 0.000 claims description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 39
- 238000002955 isolation Methods 0.000 description 26
- 230000008569 process Effects 0.000 description 15
- 238000001312 dry etching Methods 0.000 description 10
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- 229910052581 Si3N4 Inorganic materials 0.000 description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 9
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 8
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- 229910000147 aluminium phosphate Inorganic materials 0.000 description 4
- 229910052731 fluorine Inorganic materials 0.000 description 4
- 239000011737 fluorine Substances 0.000 description 4
- 239000011810 insulating material Substances 0.000 description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- 238000005498 polishing Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
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- NPNPZTNLOVBDOC-UHFFFAOYSA-N 1,1-difluoroethane Chemical compound CC(F)F NPNPZTNLOVBDOC-UHFFFAOYSA-N 0.000 description 2
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 2
- 239000004341 Octafluorocyclobutane Substances 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- NWAIGJYBQQYSPW-UHFFFAOYSA-N azanylidyneindigane Chemical compound [In]#N NWAIGJYBQQYSPW-UHFFFAOYSA-N 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 229940104869 fluorosilicate Drugs 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
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- BCCOBQSFUDVTJQ-UHFFFAOYSA-N octafluorocyclobutane Chemical compound FC1(F)C(F)(F)C(F)(F)C1(F)F BCCOBQSFUDVTJQ-UHFFFAOYSA-N 0.000 description 2
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- 239000001301 oxygen Substances 0.000 description 2
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- 239000010980 sapphire Substances 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
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- Microelectronics & Electronic Packaging (AREA)
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Abstract
The invention discloses a manufacturing method of a semiconductor structure, and belongs to the technical field of semiconductors. The manufacturing method comprises the following steps: providing a substrate; forming a barrier layer on the substrate; forming a hard mask layer on the barrier layer; etching the hard mask layer to the barrier layer to form a first opening; etching the substrate side on the first opening and the hard mask layer on one side of the first opening to form a first shallow trench and a second shallow trench; and the depth difference between the first shallow trench and the second shallow trench is equal to the product of the thickness of the hard mask layer and the etching selection ratio of the substrate and the hard mask layer. By the manufacturing method of the semiconductor structure, the manufacturing process of the semiconductor structure can be optimized.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a manufacturing method of a semiconductor structure.
Background
STI (Shallow Trench Isolation) is an important structure in integrated circuits, and can prevent current leakage between adjacent semiconductor devices and perform other electrical functions. In the semiconductor process, some semiconductor devices include different functional regions, and the requirements for the depths of the shallow trench isolation structures are different, so that the shallow trench isolation structures with different depths are required to be formed in different regions of a chip. Therefore, it is an urgent problem to improve the etching efficiency, simplify the process flow and reduce the cost.
Disclosure of Invention
The invention aims to provide a manufacturing method of a semiconductor structure, which solves the problems of complex etching process and residual photoresistance when the existing shallow trench is formed, and has simple manufacturing method and good etching effect.
In order to solve the technical problems, the invention is realized by the following technical scheme:
the invention provides a manufacturing method of a semiconductor structure, which at least comprises the following steps:
providing a substrate;
forming a barrier layer on the substrate;
forming a hard mask layer on the barrier layer;
etching the hard mask layer to the barrier layer to form a first opening;
etching the substrate side on the first opening and the hard mask layer on one side of the first opening to form a first shallow trench and a second shallow trench;
and the depth difference between the first shallow trench and the second shallow trench is equal to the product of the thickness of the hard mask layer and the etching selection ratio of the substrate and the hard mask layer.
In an embodiment of the present invention, the method for manufacturing the semiconductor structure further includes the following steps:
forming a pad oxide layer on the substrate; and
and forming a pad nitride layer on the pad oxide layer.
In an embodiment of the invention, the barrier layer is formed on the pad nitride layer, and the thickness of the barrier layer is 50A-150A.
In an embodiment of the invention, the hard mask layer has a thickness of 200A-600A.
In an embodiment of the present invention, the first shallow trench and the second shallow trench are formed by one-step etching, and a depth of the first shallow trench is greater than a depth of the second shallow trench.
In an embodiment of the present invention, a gas used for etching the first shallow trench and the second shallow trench includes one or a combination of several of trifluoromethane, carbon tetrafluoride, hydrogen bromide, and difluoromethane.
In an embodiment of the invention, the depth difference between the first shallow trench and the second shallow trench is 1000A-3000A.
In an embodiment of the present invention, the depth difference between the first shallow trench and the second shallow trench is obtained by the following formula:
h1=T╳SR；
wherein h1 is the depth difference between the first shallow trench and the second shallow trench, T is the thickness of the hard mask layer, SRAnd etching selection ratio of the substrate and the hard mask layer.
In an embodiment of the invention, after the first and second shallow trenches are formed, the thickness of the hard mask layer or the pad nitride layer is 200A-500A.
In an embodiment of the invention, an etching selection ratio of the substrate to the hard mask layer is 4: 1-10: 1.
According to the manufacturing method of the semiconductor structure, the hard mask layer is arranged, the hard mask layer is etched firstly to form the first opening, then the hard mask layer and the first opening are patterned, and the shallow trenches with different depths are obtained through one-step etching. By controlling the thickness of the hard mask layer and the pad oxide layer, the depth of the shallow trench and the depth difference between different shallow trenches can be controlled, and the controllability is high. By arranging the barrier layer and the hard mask layer, the pad oxide layer and the pad nitride layer can be replaced, the manufacturing process is simplified, and the cost is saved. In summary, the present invention provides a method for manufacturing a semiconductor structure, which can optimize the manufacturing process of the semiconductor structure.
Of course, it is not necessary for any product in which the invention is practiced to achieve all of the above-described advantages at the same time.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic diagram of a first patterned photoresist layer in an embodiment.
FIG. 2 is a schematic view of a first opening in an embodiment.
Fig. 3 to 4 are schematic diagrams illustrating the formation of a second patterned photoresist layer in one embodiment.
Fig. 5 to 6 are schematic diagrams illustrating the formation of shallow trenches in an embodiment.
Fig. 7 to 8 are schematic views illustrating the formation of a shallow trench isolation structure in one embodiment.
FIG. 9 is a schematic diagram of a barrier layer and a hard mask layer in one embodiment.
FIG. 10 is a schematic diagram of a first patterned photoresist layer in an embodiment.
FIG. 11 is a schematic view of a first opening in an embodiment.
Fig. 12 to fig. 13 are schematic diagrams illustrating the formation of a second patterned photoresist layer in one embodiment.
FIG. 14 is a schematic diagram illustrating the formation of shallow trenches in an embodiment.
Fig. 15-16 are schematic views illustrating the formation of a shallow trench isolation structure in one embodiment.
Description of reference numerals:
10 a substrate; 11 pad oxide layer; 12 pad nitride layer; 13 a barrier layer; 14 hard mask layer; 15 a first patterned photoresist layer; 16 a first opening; 17 a photoresist layer; 18 a second patterned photoresist layer; 19 a second opening; 20 a first shallow trench; 21 a second shallow trench; 22 an insulating medium; 23 a first shallow trench isolation structure; 24 a second shallow trench isolation structure; 30 a substrate; 31 a barrier layer; 32 hard mask layers; 33 a first patterned photoresist layer; 34 a first opening; 35 photoresist layer; 36 a second patterned photoresist layer; 37 a first shallow trench; 38 a second shallow trench; 39 an insulating medium; 40 a first shallow trench isolation structure; 41 second shallow trench isolation structure.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the drawings provided in this embodiment are only for schematically illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings and not drawn according to the number, shape and size of the components in actual implementation, and the form, quantity and proportion of each component in actual implementation may be arbitrarily changed, and the component layout may be more complicated.
In the present invention, it should be noted that, as the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. appear, their indicated orientations or positional relationships are based on the orientations or positional relationships shown in the drawings, and are only for convenience of describing the present application and simplifying the description, but do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first" and "second," if any, are used for descriptive and distinguishing purposes only and are not to be construed as indicating or implying relative importance.
In a semiconductor process, shallow trenches with different depths are required to form a plurality of regions of a semiconductor structure, such as a logic region for memory and a core region for control. The manufacturing method of the semiconductor structure provided by the invention can form shallow trench isolation structures with different depths, has simple manufacturing process, lower cost and high controllability, and can be widely applied to semiconductor integrated devices.
Referring to fig. 1, in an embodiment of the present invention, a substrate 10 is first provided, wherein the substrate 10 may be any suitable semiconductor material, such as a substrate of silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), sapphire, or silicon wafer. In the present embodiment, the substrate 10 is, for example, a silicon wafer semiconductor substrate.
Referring to fig. 1, in an embodiment of the invention, a pad oxide layer 11 is formed on a substrate 10, wherein the pad oxide layer 11 is, for example, a dense silicon oxide material, and the pad oxide layer 11 is formed on the substrate 10 by, for example, a thermal oxidation method, an in-situ vapor growth method, or a chemical vapor deposition method. In this embodiment, the substrate 10 is placed in a furnace tube at a temperature of, for example, 900 ℃ to 1150 ℃, oxygen is introduced, and the substrate 10 reacts with the oxygen at a high temperature to generate the dense pad oxide layer 11. The thickness of the pad oxide layer 11 is, for example, 50A-150A, specifically 60A, 80A, 100A, or 140A.
Referring to fig. 1, in one embodiment of the present invention, a pad nitride layer 12 is formed on a pad oxide layer 11, wherein the pad nitride layer 12 is, for example, silicon nitride or a mixture of silicon nitride and silicon oxide, and in this embodiment, the pad nitride layer 12 is, for example, silicon nitride. Wherein, the pad oxide layer 11 is used as a buffer layer to improve the stress between the substrate 10 and the pad nitride layer 12. In the present invention, the pad nitride layer 12 is formed on the pad oxide layer 11 by, for example, a Low Pressure Chemical Vapor Deposition (LPCVD) method or a Plasma Enhanced Chemical Vapor Deposition (PECVD) method. Specifically, the substrate 10 with the pad oxide layer 11 is placed in a furnace tube filled with dichlorosilane and ammonia gas, for example, and reacts at a pressure of 2T to 8T and a temperature of 700 ℃ to 800 ℃ for example, to deposit the pad nitride layer 12. And the thickness of the pad nitride layer 12 may be adjusted by controlling the heating time, in some embodiments, the thickness of the pad nitride layer 12 is, for example, 400 a-1200 a, specifically, 600 a, 800 a, 1000 a, 1200 a, or the like. The pad nitride layer 12 may protect the substrate 10 from damage during etching.
Referring to fig. 1, in one embodiment of the present invention, a barrier layer 13 is formed on the pad nitride layer 12, and the barrier layer 13 is made of a dense insulating material such as silicon oxide. In this embodiment, a barrier layer 13 is formed on the pad nitride layer 12, for example, by chemical vapor deposition or the like, the thickness of the barrier layer 13 being, for example, 50 a-150 a, specifically 60 a, 80 a, 100 a, 140 a, or the like. By providing the barrier layer 13, it can be used as an etch stop layer for the first etching.
Referring to fig. 1, in one embodiment of the present invention, a hard mask layer 14 is formed on a barrier layer 13, wherein the hard mask layer 14 is, for example, silicon nitride or a mixture of silicon nitride and silicon oxide, and in this embodiment, the hard mask layer 14 is, for example, silicon nitride. And the hard mask layer 14 may be prepared, for example, by low pressure chemical vapor deposition or plasma enhanced chemical vapor deposition. The thickness of the hard mask layer 14 is, for example, 200A-600A, specifically 200A, 300A, 400A, or 500A. The hard mask layer 14 may be used as a first etching layer to form corresponding openings to form shallow trenches of different depths during formation of the shallow trenches.
Referring to fig. 1, 2 and 6, in an embodiment of the present invention, a photoresist layer is formed on the hard mask layer 14, for example, by a spin-coating method, and a first patterned photoresist layer 15 is formed on the hard mask layer 14 through an exposure and development process, wherein the first patterned photoresist layer 15 is used for positioning the first opening 16. After the first patterned photoresist layer 15 is formed, the hard mask layer 14 under the first patterned photoresist layer 15 is quantitatively removed by using the first patterned photoresist layer 15 as a mask and the barrier layer 13 as an etching stop layer through dry etching, wet etching, or a combination of the dry etching and the wet etching, so as to obtain the first opening 16. In this embodiment, the hard mask layer 14 is, for example, dry etched, and the etching gas includes, for example, a fluorine-containing gas, specifically, one or a mixture of carbon tetrafluoride, trifluoromethane, difluoroethane, or octafluorocyclobutane, etc. In other embodiments, the hard mask layer 14 may also be wet etched using hot phosphoric acid. In the present embodiment, the first opening 16 is used to position the first shallow trench 20, and defines a predetermined depth of the first shallow trench 20 to be greater than a predetermined depth of the second shallow trench 21.
Referring to fig. 3 to 6, in an embodiment of the present invention, after the first opening 16 is formed, a photoresist layer 17 is formed on the hard mask layer 14 and the first opening 16, i.e., the photoresist layer 17 covers the hard mask layer 14 and the first opening 16. A second patterned photoresist layer 18 is formed on the hard mask layer 14 through an exposure and development process to locate the second opening 19. Since the depth of the first opening 16 is shallow, the second patterned photoresist layer 18 can completely expose the first opening 16, which can improve the problem of photoresist residue in shallow trenches when shallow trenches with different depths are formed step by step. After the second patterned photoresist layer 18 is formed, shallow trenches with different depths are formed by etching once. The etching process goes through two stages, first, the second patterned photoresist layer 18 is used as a mask to etch the substrate 10, and the hard mask layer 14, the blocking layer 13 and a portion of the pad nitride layer 12 under the second patterned photoresist layer 18 are quantitatively removed to obtain a second opening 19, wherein the second opening 19 is used to position the second shallow trench 21. At this time, the first opening 16 is etched to the substrate 10 in the direction of the substrate 10, and the second patterned photoresist layer 18 is etched substantially completely, as shown in fig. 5. Next, after the second patterned photoresist layer 18 is etched, the hard mask layer 14 is used as a mask to continuously etch the first opening 16 and the second opening 19, so as to form a first shallow trench 20 and a second shallow trench 21. The shallow trenches with different depths are formed by one-step etching, so that the phenomenon that light resistance remains in the shallow trenches when the shallow trenches are formed by step-by-step etching can be improved, the performance of preparing a semiconductor device at the later stage is improved, and the yield of preparing the semiconductor device is improved.
Referring to fig. 5 to 6, in an embodiment of the invention, when forming the shallow trench, the etching may be performed by using dry etching, wet etching, or a combination of the wet etching and the dry etching. In this embodiment, for example, dry etching is used to form the shallow trench, and the etching gas is, for example, one or a combination of several of trifluoromethane, carbon tetrafluoride, hydrogen bromide or difluoromethane, or a mixed gas of other fluorine-based gases. After the shallow trench is formed, the remaining thickness of the pad nitride layer 12 is, for example, 200A-500A, so as to serve as a polishing stop layer for a subsequent shallow trench isolation structure. After the etching is finished, a first shallow trench 20 and a second shallow trench 21 are formed, and the depth of the first shallow trench 20 is deeper than that of the second shallow trench 21And (4) deep. In this embodiment, the depth of the first shallow trench 20 is, for example, 2500A-4500A, the depth of the second shallow trench 21 is, for example, 1000A-2500A, and the difference in the depths of the first shallow trench 20 and the second shallow trench 21 is, for example, 1000A-3000A. The depth difference between the first shallow trench 20 and the second shallow trench 21 is determined by the thickness of the hard mask layer 14 and the etching selectivity of the substrate 10 and the hard mask layer 14. In this embodiment, the depth difference between the first shallow trench 20 and the second shallow trench 21 is denoted as h1, the thickness of the hard mask layer 14 is denoted as T, and the etching selectivity ratio between the substrate 10 and the hard mask layer 14 is denoted as SRThen the depth difference can be calculated by the following formula:
h1=T╳SR；
in the present embodiment, the etching selectivity ratio between the substrate 10 and the hard mask layer 14 is, for example, 4:1 to 10: 1. The thickness of the pad nitride layer 12 determines the etching depth of the first shallow trench 20, and the thickness of the hard mask layer 14 determines the depth of the second shallow trench 21 and the depth difference between the first shallow trench 20 and the second shallow trench 21. Therefore, the depth of the shallow trenches and the depth difference between the shallow trenches can be controlled by varying the thickness of the pad nitride layer 12 and the hard mask layer 14.
Referring to fig. 7, in one embodiment of the present invention, an insulating dielectric 22 is deposited in the first shallow trench 20 and the second shallow trench 21 until the insulating dielectric 22 covers the surface of the pad nitride layer 12. The present invention is not limited to the deposition method of the insulating medium 22, and the insulating medium 22 can be deposited by High Density Plasma CVD (HDP-CVD) or High Aspect Ratio CVD (HARP-CVD). After the deposition of the insulating dielectric 22, a high temperature annealing process may be performed to increase the density and stress of the insulating dielectric 22. In this embodiment, the insulating medium 22 is made of, for example, a silicon oxide material with high adaptability to a grinding tool, and in other embodiments, the insulating medium 22 may also be an insulating material such as fluorosilicate glass. After the insulating dielectric 22 is deposited, the insulating dielectric 22 is planarized, for example, by a Chemical Mechanical Polishing (CMP) process, to planarize the insulating dielectric 22 and a portion of the pad nitride layer 12, and to make the insulating dielectric 22 and the pad nitride layer 12 have the same height.
Referring to fig. 6 and 8, in an embodiment of the invention, the polished pad nitride layer 12 and the insulating medium 22 are etched, for example, by wet etching, for example, by sequentially etching with hot phosphoric acid and hydrofluoric acid, so as to remove the pad nitride layer 12 and a portion of the insulating medium 22, thereby forming a first shallow trench isolation structure 23 and a second shallow trench isolation structure 24. The first shallow trench isolation structure 23 is formed in the first shallow trench 20, and the second shallow trench isolation structure 24 is formed in the second shallow trench 21. By setting the depth of the first shallow trench isolation structure 23 to be greater than the depth of the second shallow trench isolation structure 24, shallow trench isolation structures with different depths are formed in different regions of the substrate 10, and different units can be set in different regions according to the requirements of manufacturing semiconductor devices. The manufacturing method of the semiconductor structure can flexibly adjust the depth of the shallow trench and the depth difference of the shallow trench by adjusting the thickness of the pad nitride layer 12 and the thickness of the hard mask layer 14, and can be applied to integrated devices with higher requirements on the depth and the depth difference.
In some embodiments, as shown in fig. 9-16, another method for fabricating a semiconductor structure is also provided, and the method for fabricating the semiconductor structure in this embodiment will be described in detail with reference to the drawings.
Referring to fig. 9, in an embodiment of the invention, a substrate 30 is provided, and the substrate 30 may be any suitable semiconductor material, such as a substrate of silicon carbide (SiC), gallium nitride (GAN), aluminum nitride (AlN), indium nitride (InN), sapphire, or silicon wafer. In this embodiment, the substrate 30 is, for example, a silicon wafer semiconductor substrate.
Referring to fig. 9, in an embodiment of the present invention, a barrier layer 31 is formed on a substrate 30, and the barrier layer 31 is made of a dense insulating material such as silicon oxide. The barrier layer 31 may be formed by a thermal oxidation method, an in-situ vapor growth method, or chemical vapor deposition, for example. In the present embodiment, the barrier layer 31 is formed on the substrate 30 by, for example, a thermal oxidation method. The thickness of the barrier layer 31 is, for example, 50A-150A, specifically 60A, 80A, 100A or 140A. By providing the barrier layer 31, it can be used as an etch stop layer for the first etching.
Referring to fig. 9, in an embodiment of the present invention, a hard mask layer 32 is formed on the barrier layer 31, and the hard mask layer 32 is, for example, silicon nitride or a mixture of silicon nitride and silicon oxide. In the present embodiment, the hard mask layer 32 is, for example, silicon nitride, and the hard mask layer 32 can be prepared by, for example, a low pressure chemical vapor deposition method or a plasma enhanced chemical vapor deposition method. The thickness of the hard mask layer 32 is, for example, 200A-600A, specifically 200A, 300A, 400A, or 500A. The hard mask layer 32 may be used as a first etching layer to form corresponding openings, and shallow trenches of different depths may be formed during the formation of the shallow trenches.
Referring to fig. 10 to 11, in an embodiment of the invention, a photoresist layer is formed on the hard mask layer 32, for example, by a spin-coating method, and a first patterned photoresist layer 33 is formed on the hard mask layer 32 through exposure and development processes, wherein the first patterned photoresist layer 33 is used for positioning the first opening 34. After the first patterned photoresist layer 33 is formed, the hard mask layer 32 under the first patterned photoresist layer 33 is quantitatively removed by dry etching, wet etching, or a combination of the wet etching and the dry etching, with the first patterned photoresist layer 33 as a mask and the barrier layer 31 as an etching stop layer, so as to obtain a first opening 34. In this embodiment, for example, the hard mask layer 32 is dry etched by using a fluorine-containing gas, specifically, one or a mixture of several of carbon tetrafluoride, trifluoromethane, difluoroethane, or octafluorocyclobutane, or the hard mask layer 32 is wet etched by using hot phosphoric acid.
Referring to fig. 12-14, in an embodiment of the invention, after the first opening 34 is formed, a photoresist layer 35 is formed on the hard mask layer 32 and the first opening 34, and the photoresist layer 35 covers the hard mask layer 32 and the first opening 34. After exposure and development processes, a second patterned photoresist layer 36 is formed on the hard mask layer 32 to position the second shallow trench 38, and the second patterned photoresist layer 36 exposes the first opening 34. After the second patterned photoresist layer 36 is formed, the substrate 30 is etched using the second patterned photoresist layer 36 as a mask, and shallow trenches having different depths are formed by one etching. The barrier layer 31 and a portion of the substrate 30 in the first opening 34 are removed quantitatively to obtain a first shallow trench 37, and the hard mask layer 32, the barrier layer 31 and a portion of the substrate 30 under the second patterned photoresist layer 36 are removed quantitatively to obtain a second shallow trench 38. In the present embodiment, the predetermined depth of the first shallow trench 37 is defined to be greater than the predetermined depth of the second shallow trench 38. The shallow trenches with different depths are formed through one-step etching, so that the phenomenon that light resistance remains in the shallow trenches when the shallow trenches are etched step by step can be improved, and the performance of devices prepared in the later stage is improved.
Referring to fig. 14, in an embodiment of the invention, when forming the shallow trench, the etching process may be performed by dry etching, wet etching, or a combination of wet etching and dry etching. In this embodiment, for example, dry etching is used to form the shallow trench, and the etching gas includes, for example, one or a combination of several of trifluoromethane, carbon tetrafluoride, hydrogen bromide, and difluoromethane, or a mixed gas of other fluorine-based gases. After the shallow trench is formed, the remaining thickness of the hard mask layer 32 is, for example, 200A-500A, so as to be used as a polishing stop layer of a subsequent shallow trench isolation structure. After the etching is finished, a first shallow trench 37 and a second shallow trench 38 are formed, and the depth of the first shallow trench 37 is deeper than the depth of the second shallow trench 38, and in this embodiment, the depth of the first shallow trench 37 is, for example, 2000A-3000A, and the depth of the second shallow trench 38 is, for example, 1000A-2000A. In the present embodiment, the depth difference between the first shallow trench 37 and the second shallow trench 38 is denoted as h1, the thickness of the hard mask layer 32 is denoted as T, and the etching selection ratio between the substrate 30 and the hard mask layer 32 is denoted as SRThen the depth difference can be calculated by the following formula:
h1=T╳SR；
in the present embodiment, the etching selectivity ratio between the substrate 30 and the hard mask layer 32 is, for example, 4:1 to 10: 1.
Referring to fig. 15, in one embodiment of the present invention, an insulating dielectric 39 is deposited in the first and second shallow trenches 37 and 38 until the insulating dielectric 39 covers the surface of the hard mask layer 32. The present invention is not limited to the deposition method of the insulating dielectric 39, and the insulating dielectric 39 can be deposited by a deposition method such as high density plasma chemical vapor deposition or high aspect ratio chemical vapor deposition. After the insulating medium 39 is deposited, a high temperature annealing process may be performed to increase the density and stress of the insulating medium 39, such as a silicon oxide material with high adaptability to the grinding tool, for example. In other embodiments, the insulating medium 39 may also be an insulating material such as fluorosilicate glass. After the deposition of the insulating dielectric 39, the insulating dielectric 39 is planarized, for example, by a Chemical Mechanical Polishing (CMP) process, to planarize the insulating dielectric 39 and a portion of the hard mask layer 32 and to make the insulating dielectric 39 and the hard mask layer 32 have the same height.
Referring to fig. 14 and 16, in an embodiment of the invention, the polished hard mask layer 32 and the insulating dielectric 39 are etched, for example, by wet etching, for example, by sequentially etching with hot phosphoric acid and hydrofluoric acid, so as to remove the hard mask layer 32 and partially deposit the insulating dielectric 39, thereby forming a first shallow trench isolation structure 40 and a second shallow trench isolation structure 41. The first sti structure 40 is formed in the first shallow trench 37, and the second sti structure 41 is formed in the second shallow trench 38. By setting the depth of the first shallow trench isolation structure 40 to be greater than the depth of the second shallow trench isolation structure 41, the substrate 30 is divided into different regions, and different units can be arranged in different regions according to the requirements of manufacturing semiconductor integrated devices. The manufacturing method directly arranges the barrier layer 31 and the hard mask layer 32 on the substrate 30, and then further etches to form shallow trenches with different depths. Because the hard mask layer 32 needs to be kept with a certain thickness, the adjustment space of the depth and the height difference of the shallow trench is narrower than that of the former embodiment, but the forming process is simple, the cost is lower, and the requirement of forming shallow trenches with different depths on the same substrate is met. Therefore, in practical production, the manufacturing method can be flexibly selected according to the depth and the height difference of the groove.
In an embodiment of the present invention, the method is used to fabricate shallow trench isolation structures of different depths in a Complementary Metal Oxide Semiconductor (CMOS) image sensor. The formed deep shallow trench isolation structure can be used for isolating metal oxide semiconductor field effect transistor devices in peripheral logic circuit units in a CMOS image sensor, and the shallow trench isolation structure can be used for isolating Pixel sensing units (Pixel areas) in the CMOS image sensor.
The embodiments of the invention disclosed above are intended merely to aid in the explanation of the invention. The examples are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention. The invention is limited only by the claims and their full scope and equivalents.
Claims (10)
1. A method of fabricating a semiconductor structure, comprising:
providing a substrate;
forming a barrier layer on the substrate;
forming a hard mask layer on the barrier layer;
etching the hard mask layer to the barrier layer to form a first opening;
etching the substrate side on the first opening and the hard mask layer on one side of the first opening to form a first shallow trench and a second shallow trench;
and the depth difference of the first shallow trench and the second shallow trench is equal to the product of the thickness of the hard mask layer and the etching selection ratio of the substrate and the hard mask layer.
2. The method of claim 1, further comprising:
forming a pad oxide layer on the substrate; and
and forming a pad nitride layer on the pad oxide layer.
3. The method of manufacturing a semiconductor structure according to claim 2, wherein the barrier layer is formed on the pad nitride layer, and a thickness of the barrier layer is 50A-150A.
4. The method of manufacturing a semiconductor structure according to claim 1, wherein the hard mask layer has a thickness of 200A-600A.
5. The method of claim 1, wherein the first and second shallow trenches are formed by one-step etching, and wherein a depth of the first shallow trench is greater than a depth of the second shallow trench.
6. The method as claimed in claim 5, wherein the gas used for etching the first and second shallow trenches comprises one or more of trifluoromethane, carbon tetrafluoride, hydrogen bromide or difluoromethane.
7. The method of manufacturing a semiconductor structure according to claim 5, wherein the difference in depth between the first shallow trench and the second shallow trench is 1000A-3000A.
8. The method of manufacturing a semiconductor structure according to claim 1, wherein the difference in depth between the first shallow trench and the second shallow trench is obtained by the following formula:
h1=T╳SR；
wherein h1 is the depth difference between the first shallow trench and the second shallow trench, T is the thickness of the hard mask layer, SREtching the substrate and the hard mask layerThe selection ratio.
9. The method of manufacturing a semiconductor structure of claim 2, wherein a thickness of the hard mask layer or the pad nitride layer after the first and second shallow trenches are formed is 200A-500A.
10. The method of claim 1, wherein an etching selectivity ratio of the substrate to the hard mask layer is 4:1 to 10: 1.
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