CN114156176A - Method for manufacturing semiconductor structure - Google Patents
Method for manufacturing semiconductor structure Download PDFInfo
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- CN114156176A CN114156176A CN202210123451.9A CN202210123451A CN114156176A CN 114156176 A CN114156176 A CN 114156176A CN 202210123451 A CN202210123451 A CN 202210123451A CN 114156176 A CN114156176 A CN 114156176A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Element Separation (AREA)
Abstract
The invention discloses a manufacturing method of a semiconductor structure, which comprises the following steps: providing a substrate; forming a pad oxide layer on the substrate; forming a pad nitride layer on the pad oxide layer; etching the pad oxide layer, the pad nitride layer and part of the substrate to form a shallow trench; forming a lining oxide layer in the shallow trench; depositing an isolation medium in the shallow trench to form a shallow trench isolation structure; and etching the pad nitride layer and part of the shallow trench isolation structure to form a step between the shallow trench isolation structure and the pad oxide layer. The method for manufacturing the semiconductor structure can select the step height of the shallow trench isolation structure.
Description
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to a manufacturing method of a semiconductor structure.
Background
Shallow Trench Isolation (STI) is an important structure in integrated circuits, which can prevent current leakage between adjacent semiconductor devices and also play a role in other electrical properties. The step height of shallow trench isolation influences the performance of the device, when the step height is too low, stress concentration exists at the corner between the step and the pad oxide layer, a recess can be formed, and when the shallow trench isolation is used, leakage of an active region is caused. When the step height is too high, polysilicon remains at the corner formed by the step of the shallow trench isolation structure and the substrate in the subsequent gate etching process, and thus the semiconductor element is short-circuited.
At present, the step height of the shallow trench isolation structure is generally formed by adopting a two-step etching process, wherein the shallow trench isolation structure is etched by hydrofluoric acid, and then silicon nitride is etched by hot phosphoric acid. The etching process is complex, the step height is difficult to control, the cost is high, and the production period is relatively long. Therefore, how to accurately control the height of the step and simplify the process become problems to be solved.
Disclosure of Invention
The invention aims to provide a manufacturing method of a semiconductor structure, which adopts a one-step method to etch and form steps, is simple and convenient to operate, shortens the process time, can accurately control the height of the steps, and solves the problems of unstable electrical property and yield.
In order to realize the purpose, the invention is realized by the following technical scheme:
the invention provides a manufacturing method of a semiconductor structure, which comprises the following steps:
providing a substrate;
forming a pad oxide layer on the substrate;
forming a pad nitride layer on the pad oxide layer;
etching the pad oxide layer, the pad nitride layer and part of the substrate to form a shallow trench;
forming a lining oxide layer in the shallow trench;
depositing an isolation medium in the shallow trench to form a shallow trench isolation structure; and
and etching the pad nitride layer and part of the shallow trench isolation structure so that the shallow trench isolation structure and the pad oxide layer form a step.
In some embodiments of the present disclosure, an opening is formed by first etching the pad nitride layer, the pad oxide layer, and a portion of the substrate.
In some embodiments of the present disclosure, the shallow trench is formed by etching a portion of the substrate within the opening a second time.
In some embodiments of the disclosure, the method for forming the liner oxide layer includes: and introducing oxygen mixed with a small amount of hydrogen into the shallow trench at the temperature of 500-650 ℃ and the pressure of 10-20T, wherein the oxygen reacts with the side wall of the shallow trench to generate an oxide layer.
In some embodiments of the present disclosure, the forming of the shallow trench isolation structure includes:
depositing the isolation medium in the shallow trench; and
planarizing the isolation medium and a part of the pad nitride layer to make the isolation medium and the pad nitride layer have the same height;
wherein the thickness of the planarized pad nitride layer is 40-150 nm.
In some embodiments disclosed in the present invention, the pad nitride layer and a portion of the shallow trench isolation structure are removed simultaneously by wet etching.
In some embodiments disclosed in the present invention, the etching liquid for wet etching includes hydrofluoric acid, and the mass fraction of hydrogen fluoride in the hydrofluoric acid is 45-55%.
In some embodiments disclosed in the present invention, the etching solution for wet etching further includes ethylene glycol, and a volume ratio of the ethylene glycol to the hydrofluoric acid is 1: 10-1: 40.
In some embodiments disclosed in the present invention, an etching selection ratio of the shallow trench isolation structure to the pad nitride layer in the wet etching process is 1: 1.2-1: 2.
In some embodiments of the present disclosure, the wet etching includes:
mixing the hydrofluoric acid and the glycol to obtain the etching liquid;
heating the etching solution to 60-90 ℃; and
and reacting the substrate with the etching solution for 100-500 s.
The invention provides a manufacturing method of a semiconductor structure, which can repair the damage of the surface of a groove by depositing a lining oxide layer in the shallow groove after the shallow groove is formed by etching, and form a fillet at the bottom of the shallow groove, thereby reducing the phenomenon of electric leakage of a sharp corner and improving the electrical property and the yield of a device. By using the mixed solution of hydrofluoric acid and glycol as the etching solution, the pad nitride layer and the isolation medium can be etched synchronously due to different etching selection ratios of the mixed solution of hydrofluoric acid and glycol to the pad nitride layer and the isolation medium. By controlling the mixing ratio and the etching temperature of hydrofluoric acid and ethylene glycol and controlling the etching selection ratio of the pad nitride layer and the isolation medium, great freedom is provided for the height selection of the step. Therefore, the invention provides a manufacturing method of a semiconductor structure, which simplifies the manufacturing process of preparing the shallow trench isolation structure, reduces the complexity of the process and the production cost by synchronously etching the shallow trench isolation structure and the pad nitride layer, shortens the production period and has wide application prospect.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic flow chart illustrating a method for manufacturing a semiconductor structure according to the present invention.
Fig. 2 is a schematic structural diagram corresponding to step S1 when a pad nitride layer and a pad oxide layer are formed on a silicon substrate.
Fig. 3 is a schematic structural diagram corresponding to step S2 when openings are formed in the pad nitride layer, the pad oxide layer and the silicon substrate.
Fig. 4 is a schematic structural diagram corresponding to the step S3 of forming the isolation trench.
Fig. 5 is a schematic structural diagram corresponding to the step S4 of forming the liner oxide layer.
Fig. 6 is a schematic structural diagram corresponding to the step S5 when the isolation medium is formed.
Fig. 7 is a schematic structural diagram of the isolation medium after chemical mechanical polishing in step S6.
Fig. 8 is a schematic structural diagram of the pad nitride layer and the sti structure after one-step etching in step S7.
Description of reference numerals:
a 110 silicon substrate; 120 pad oxide layer; 130 pad nitride layer; 140 opening; 150a shallow trench; 150 shallow trench isolation structures; 160 lining oxide layer; 170 steps; 101, rounding; 200 an isolation medium; an alpha tilt angle; h step height; s1 to S7.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
In the present invention, it should be noted that, as the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. appear, their indicated orientations or positional relationships are based on the orientations or positional relationships shown in the drawings, and are only for convenience of describing the present application and simplifying the description, but do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first" and "second," if any, are used for descriptive and distinguishing purposes only and are not to be construed as indicating or implying relative importance.
The invention provides a manufacturing method of a semiconductor structure, which is characterized in that after a shallow trench is formed, an isolation medium is filled to form a trench isolation structure. After the isolation medium is ground to enable the height of the groove isolation structure to be consistent with that of the pad nitride layer, the pad nitride layer and the isolation medium are synchronously etched by a one-step etching method to form a step of the shallow groove isolation structure, and the height of the step is accurately controlled by changing etching conditions.
As shown in fig. 1, in various embodiments of the present invention, a method for fabricating a shallow trench isolation structure may include the following steps:
s1, forming a pad oxide layer and a pad nitride layer on the pad oxide layer on a substrate.
And S2, etching the pad oxide layer, the pad nitride layer and part of the substrate to form an opening.
And S3, continuing etching at the opening position to form a shallow trench.
And S4, forming a lining oxide layer in the shallow trench.
S5, filling shallow trench isolation media in the shallow trench to form a shallow trench isolation structure until the isolation media covers the pad nitride layer.
And S6, chemically and mechanically polishing to make the shallow trench isolation medium and the nitride layers of the two side pads have the same height.
And S7, simultaneously etching the pad nitride layer and the shallow trench isolation structure to form a step between the pad oxide layer and the shallow trench isolation structure.
In the embodiment of the present invention, as shown in fig. 2, the substrate 110, such as a silicon substrate, may further be monocrystalline silicon, polycrystalline silicon or amorphous silicon, although the substrate 110 may also include doped silicon. The thickness of the substrate 110 is not particularly limited, and may be selected according to the requirements of the actual manufacturing process. The invention is not limited to the material of the substrate 110, and in other embodiments, the substrate 110 may be a substrate made of different materials, such as a nitride substrate, a sapphire substrate, or a silicon substrate.
As shown in fig. 2, in the embodiment of the invention, in step S1, a pad oxide layer 120 is formed on a substrate 110, where the pad oxide layer 120 is, for example, dense silicon oxide, and the pad oxide layer 120 may be formed on the substrate 110 by, for example, a thermal oxidation method. Specifically, the substrate 110 may be placed in a furnace tube at a temperature of 900-1150 ℃, for example, oxygen is introduced into the furnace tube, and the substrate 110 reacts with the oxygen at a high temperature to form the dense pad oxide layer 130. The thickness of the pad oxide layer 120 is, for example, 10 to 50nm, specifically, 30nm, 40nm, 45nm or 50 nm. The invention is not limited to the method for forming the pad oxide layer 120, and in other embodiments, the pad oxide layer 120 may be formed by Chemical Vapor Deposition (CVD).
As shown in fig. 2, in the embodiment of the invention, in step S1, a pad nitride layer 130 is formed on the pad oxide layer 120, and the pad nitride layer 130 is, for example, silicon nitride (SiN) or a mixture of silicon nitride and silicon oxide. The pad oxide layer 120 serves as a buffer layer to improve the high stress between the substrate 110 and the pad nitride layer 130. In the present invention, the pad nitride layer 130 may be formed on the pad oxide layer 120 by, for example, a Low Pressure Chemical Vapor Deposition (LPCVD) method. Specifically, the substrate 110 with the pad oxide layer 120 is placed in a furnace filled with dichlorosilane and ammonia gas, and the pad nitride layer 130 is deposited under a pressure of, for example, 2 to 10T, specifically, 8T, and at a temperature of, for example, 700 to 800 ℃, specifically, 750 ℃. The thickness of the pad nitride layer 130 can be adjusted by controlling the heating time, in some embodiments, the heating time is, for example, 50 to 190min, and the thickness of the pad nitride layer 130 is, for example, 50nm to 200nm, specifically, 60nm, 75nm, 80nm, 100nm, 150nm, 180nm, or 200nm, etc. The pad nitride layer 130 may protect the substrate 110 from a Chemical Mechanical Polishing (CMP) process involved in the manufacturing process of the sti structure. The pad nitride layer 130 can be used as a mask during the formation of the shallow trench, and protects the substrate 110 at other parts from being damaged when the substrate 110 is etched.
As shown in fig. 3, in the embodiment of the present invention, the shallow trench forming process includes a first etching and a second etching, and in step S2, the first etching is performed on the substrate 110 and the pad oxide layer 120 and the pad nitride layer 130 disposed on the substrate 110. Specifically, for example, a photoresist layer may be formed on the pad nitride layer 130 by a spin coating method, and a photoresist pattern may be formed on the photoresist layer through exposure and development processes to obtain a patterned photoresist layer (not shown), where the patterned photoresist layer is used to define the position of the opening. After forming the patterned photoresist layer, the pad nitride layer 130, the pad oxide layer 120 and a portion of the substrate 110 under the photolithography pattern are quantitatively removed by dry etching using the patterned photoresist layer as a mask, thereby obtaining an opening 140. The opening 140 is used to define the position of the shallow trench, and in this embodiment, for example, the substrate 110 with 10-50 nm is etched, and then the patterned photoresist layer is removed. The opening 140 is formed by the first etching to position the formation position of the shallow trench, and the etching process of the shallow trench is etched in two steps, so that the photoresist stripping caused by too thick photoresist in the patterning process can be prevented.
As shown in fig. 4, in the embodiment of the present invention, after the opening 140 is formed, the substrate 110 is etched for the second time. In the second etching, the pad nitride layer 130 is used as a mask, for example, the substrate 110 is dry etched, and a shallow trench 150a is formed at the position of the opening 140, the shallow trench 150a has an inclined sidewall, and the inclination angle α is, for example, 85 to 90 °, and the width of the top opening of the shallow trench 150a is large, so as to facilitate the subsequent process operation. The etching gas used in the process of forming the shallow trench 150a in the dry etching process may be, for example, chlorine (Cl)2) Fluoromethane (CF)3) Difluoromethane (CF)2) Nitrogen trifluoride (NF)3) Sulfur hexafluoride (SF)6) Hydrogen bromide (HBr), nitrogen (N)2) Or they and oxygen (O)2) Combinations, in particular, for example, Cl2、N2And O2The mixed gas of (1). Based on its anisotropic characteristics, the bottom corner of the shallow trench 150a is almost a right angle corner, which has potential leakage problems during subsequent deposition of the isolation medium 200 and packaging of the semiconductor device.
As shown in fig. 5, in the embodiment of the present invention, after the shallow trench 150a is formed, a liner oxide layer 160 is formed in the shallow trench 150 a. In the present embodiment, a small amount of hydrogen (H) is introduced into the shallow trench 150a at 500-650 deg.C and 10-20T, for example2) Oxygen (O) of2) The hydrogen and oxygen form a mixture of water vapor, OH radicals, O radicals, etc. on the silicon surface in the shallow trench 150a, and since the reaction product of the hydrogen and oxygen does not react with the pad oxide layer 120 and the pad nitride layer 130, it reacts with the silicon substrate surface only inside the shallow trench 150a of the substrate 110 portion to produce silicon oxide to form the linear liner oxide layer 160. And the liner oxide layer 160 may be deposited at the bottom corner of the shallow trench 150a to form the fillet 101, and the fillet 101 may reduce the contact area and solve the potential leakage problem. And the liner oxide layer 160 can also repair the damage of the edge surface of the shallow trench 150a during etching, thereby improving the electrical property and yield of the device.
As shown in fig. 6, in the embodiment of the present invention, in step S5, an isolation dielectric 200 is deposited in the shallow trench 150a and on top of the shallow trench 150a, the isolation dielectric 200 covering the surface of the pad nitride layer 130. The invention is not limited to the deposition method of the isolation dielectric 200, and the isolation dielectric 200 can be formed by High Density Plasma chemical vapor deposition (HDP-CVD) or High Aspect Ratio chemical vapor deposition (HARP-CVD). The thickness of the isolation medium 200 is, for example, 300-1200 nm, specifically, 350nm, 560nm, 750nm, 890nm, 970nm, 1200nm, or the like. After the isolation dielectric 200 is deposited, a high temperature annealing process may be performed, such as annealing the isolation dielectric 200 at 800-1200 ℃ to increase the density and stress of the isolation dielectric 200. In this embodiment, the isolation medium 200 is, for example, silicon oxide with high adaptability to the grinding tool, and in other embodiments, the isolation medium 200 may also be an insulating material such as fluorosilicate glass.
In step S6, in the embodiment of the invention, the isolation medium 200 after step S5 is planarized, for example, by using a Chemical Mechanical Polishing (CMP) process to planarize the isolation medium 200 and a portion of the pad nitride layer 130 and to make the height of the shallow trench isolation structure 150 and the pad nitride layer 130 on both sides consistent. After the etching and polishing processes, the thickness of the pad nitride layer 130 is, for example, 40 to 150nm, such as 60nm, 75nm, 90nm, and 120 nm.
As shown in fig. 8, in step S7, the polished pad nitride layer 130 and the shallow trench isolation structure 150 are simultaneously etched, for example, wet etched. The etching liquid for wet etching is prepared by mixing hydrofluoric acid (HF) and Ethylene Glycol (EG), and the etching selection ratio of the mixed solution of hydrofluoric acid and ethylene glycol to silicon nitride and silicon oxide is different. The hydrofluoric acid is a hydrofluoric acid aqueous solution with the mass fraction of hydrogen fluoride of 45-55%, specifically, a 49% hydrofluoric acid aqueous solution is uniformly mixed with ethylene glycol, and the volume ratio of the hydrofluoric acid aqueous solution to the ethylene glycol in the etching liquid is 1: 10-1: 40. In the present embodiment, the pad nitride layer 130 and the shallow trench isolation structure 150 are simultaneously etched at an etching temperature of, for example, 60 to 90 ℃, and the etching time is, for example, 100 to 500 seconds. By using a mixed solution of hydrofluoric acid and ethylene glycol as an etching solution, the pad nitride layer 130 and the shallow trench isolation structure 150 can be etched simultaneously.
As shown in FIG. 8, in the embodiment of the present invention, the pad nitride layer 130 is, for example, SiN, and the shallow trench isolation structure 150 is, for example, SiO2. The etching liquid is a mixed solution of 49% hydrofluoric acid aqueous solution and ethylene glycol, the volume ratio of the hydrofluoric acid aqueous solution to the ethylene glycol is 1:24, and the etching liquid is applied to SiO at 70-80 DEG C2And the etch selectivity of SiN was 1: 1.5. Since the height of the pad nitride layer 130 is the same as that of the shallow trench isolation structure 150 after the step S6, when etching is performed, the etching speed of SiN is fast, a step is formed between the pad nitride layer 130 and the shallow trench isolation structure 150, and the reaction time is controlled, so that the step height of the step can be adjustedDegree (step height) is selected. In the present embodiment, the step height H is, for example, 10 to 60nm, specifically, 10nm, 20nm, 30nm, 40nm, or 50 nm.
As shown in fig. 8, in the embodiment of the invention, the heights of the pad nitride layer 130 and the shallow trench isolation structure 150 are selected, the ratio of the etching solution is fixed, and the etching time is determined by controlling the height of the pad nitride layer 130 before etching, so as to ensure that the pad nitride layer 130 is etched completely to form different step heights. For example, the height of the pad nitride layer 130 before etching is 90nm, and the etching solution is used to perform etching, when the pad nitride layer 130 is just completely etched, at this time, the shallow trench isolation structure 150 is etched by 60nm, and the step height H formed between the pad oxide layer 120 and the shallow trench isolation structure 150 is 30 nm.
As shown in fig. 8, in the embodiment provided by the present invention, during the manufacturing process, the heights of the pad nitride layer 130 and the shallow trench isolation structure 150 may be selected, and the mixing ratio of the hydrofluoric acid aqueous solution and the ethylene glycol and the etching temperature are selected, so as to control different etching selection ratios of the nitride layer and the oxide layer, in the embodiment, by controlling the mixing ratio, the etching selection ratio of the etching solution to the nitride layer and the oxide layer is, for example, 1:1.2 to 1:2, so that step heights with different heights can be formed in one step. And the complexity and the production period of the process are reduced by a one-step etching process.
As shown in fig. 8, in the embodiment of the present invention, when etching the pad nitride layer 130 and the shallow trench isolation structure 150, a whole batch of substrates are etched in an etching solution, and after the etching is completed, the substrates are immediately taken out, and a whole batch of substrates are washed in a water tank, and then dried after being washed clean, so as to complete the preparation of the shallow trench isolation structure. The shallow trench isolation structure can be applied to a semiconductor device to obtain a semiconductor device isolation structure.
In summary, the method for manufacturing a semiconductor structure according to the present invention deposits a pad oxide layer and a pad nitride layer on a substrate, and etches the pad nitride layer, the pad oxide layer and the substrate in two steps to form a shallow trench. A liner oxide layer is formed by forming an oxide in the shallow trench. And depositing an isolation medium layer in the shallow trench, covering the pad nitride layer, and flattening the isolation medium layer to form a shallow trench isolation structure. The pad nitride layer and the shallow trench isolation structure are synchronously etched by adopting wet etching, the pad nitride layer is removed, steps are formed on the pad oxide layer and the shallow trench isolation structure, and the steps with different heights are formed by controlling the proportion of each component in the etching liquid and the etching temperature. The manufacturing method of the semiconductor structure provided by the invention can improve the performance of the semiconductor device.
The preferred embodiments of the invention disclosed above are intended to be illustrative only. The preferred embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention. The invention is limited only by the claims and their full scope and equivalents.
Claims (10)
1. A method of fabricating a semiconductor structure, comprising:
providing a substrate;
forming a pad oxide layer on the substrate;
forming a pad nitride layer on the pad oxide layer;
etching the pad oxide layer, the pad nitride layer and part of the substrate to form a shallow trench;
forming a lining oxide layer in the shallow trench;
depositing an isolation medium in the shallow trench to form a shallow trench isolation structure; and
and etching the pad nitride layer and part of the shallow trench isolation structure so that the shallow trench isolation structure and the pad oxide layer form a step.
2. The method of claim 1, wherein an opening is formed by first etching the pad nitride layer, the pad oxide layer, and a portion of the substrate.
3. The method of claim 2, wherein the shallow trench is formed by etching a portion of the substrate within the opening a second time.
4. The method of claim 1, wherein the liner oxide layer is formed by a method comprising: and introducing oxygen mixed with a small amount of hydrogen into the shallow trench at the temperature of 500-650 ℃ and the pressure of 10-20T, wherein the oxygen reacts with the side wall of the shallow trench to generate an oxide layer.
5. The method of claim 1, wherein the step of forming the shallow trench isolation structure comprises:
depositing the isolation medium in the shallow trench; and
planarizing the isolation medium and a part of the pad nitride layer to make the isolation medium and the pad nitride layer have the same height;
wherein the thickness of the planarized pad nitride layer is 40-150 nm.
6. The method as claimed in claim 1, wherein the pad nitride layer and a portion of the shallow trench isolation structure are removed simultaneously by wet etching.
7. The method for manufacturing the semiconductor structure, according to claim 6, wherein the etching liquid for the wet etching comprises hydrofluoric acid, and the mass fraction of hydrogen fluoride in the hydrofluoric acid is 45-55%.
8. The method for manufacturing the semiconductor structure, according to claim 7, wherein the etching solution for wet etching further comprises ethylene glycol, and the volume ratio of the ethylene glycol to the hydrofluoric acid is 1: 10-1: 40.
9. The method for manufacturing a semiconductor structure according to claim 6, wherein an etching selection ratio of the shallow trench isolation structure to the pad nitride layer in the wet etching process is 1: 1.2-1: 2.
10. The method of claim 8, wherein the wet etching step comprises:
mixing the hydrofluoric acid and the glycol to obtain the etching liquid;
heating the etching solution to 60-90 ℃; and
and reacting the substrate with the etching solution for 100-500 s.
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