CN1319153C - Process for making trench capacitor having geometric shape trench - Google Patents
Process for making trench capacitor having geometric shape trench Download PDFInfo
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- CN1319153C CN1319153C CNB031463746A CN03146374A CN1319153C CN 1319153 C CN1319153 C CN 1319153C CN B031463746 A CNB031463746 A CN B031463746A CN 03146374 A CN03146374 A CN 03146374A CN 1319153 C CN1319153 C CN 1319153C
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- 238000000034 method Methods 0.000 title claims abstract description 84
- 230000008569 process Effects 0.000 title claims description 12
- 239000003990 capacitor Substances 0.000 title abstract description 18
- 238000004519 manufacturing process Methods 0.000 claims abstract description 60
- 239000000758 substrate Substances 0.000 claims description 56
- 238000005530 etching Methods 0.000 claims description 50
- 230000015572 biosynthetic process Effects 0.000 claims description 14
- 229920005591 polysilicon Polymers 0.000 claims description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 11
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 10
- 239000011521 glass Substances 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- 238000005229 chemical vapour deposition Methods 0.000 claims description 8
- 238000000059 patterning Methods 0.000 claims description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 8
- 229910052785 arsenic Inorganic materials 0.000 claims description 5
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 5
- 230000004888 barrier function Effects 0.000 claims description 5
- RZVAJINKPMORJF-UHFFFAOYSA-N Acetaminophen Chemical compound CC(=O)NC1=CC=C(O)C=C1 RZVAJINKPMORJF-UHFFFAOYSA-N 0.000 claims description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 4
- 239000005297 pyrex Substances 0.000 claims description 4
- 239000003989 dielectric material Substances 0.000 claims description 3
- 238000003701 mechanical milling Methods 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000005268 plasma chemical vapour deposition Methods 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 2
- 238000001020 plasma etching Methods 0.000 description 13
- 239000004065 semiconductor Substances 0.000 description 11
- 229920002120 photoresistant polymer Polymers 0.000 description 10
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- 238000003860 storage Methods 0.000 description 8
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- 230000002093 peripheral effect Effects 0.000 description 7
- 239000003595 mist Substances 0.000 description 5
- 230000008859 change Effects 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
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- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
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- 238000001039 wet etching Methods 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- CPELXLSAUQHCOX-UHFFFAOYSA-N Hydrogen bromide Chemical compound Br CPELXLSAUQHCOX-UHFFFAOYSA-N 0.000 description 1
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- 235000011114 ammonium hydroxide Nutrition 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
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- QVLTXCYWHPZMCA-UHFFFAOYSA-N po4-po4 Chemical compound OP(O)(O)=O.OP(O)(O)=O QVLTXCYWHPZMCA-UHFFFAOYSA-N 0.000 description 1
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- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
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Abstract
The present invention provides a manufacturing process of a ditch groove type capacitor with a ditch groove in the geometric shape. The present invention comprises the following procedures that a base with a structure of a cushion layer is provided, a first hard cover screen layer is formed and arranged on the structure of the cushion layer, and a patterned second hard cover screen layer is formed and arranged on the first hard cover screen layer. A first opening is exposed, and a spacing layer is formed and arranged at one side wall of the first opening to form a smaller second opening. A third hard cover screen layer is formed to fill the second opening, and the spacing layer is removed. The first hard cover screen layer is etched, and a third opening is exposed. The first hard cover screen layer is in the third opening and is provided with a prominence part of the first hard cover screen layer, the first hard cover screen layer, the prominence part of the first hard cover screen layer, the structure of the cushion layer and a basal plate are etched, and a ditch groove which has a middle prominence part and forms a geometric shape is formed in the basal plate.
Description
Technical field
The invention relates to the method for the trench capacitor of making semiconductor integrated circuit, particularly a kind of manufacture method of the groove relevant for groove-shaped electric capacity.
Background technology
The development of integrated circuits technology is maked rapid progress, its development trend is toward powerful, size is dwindled with the direction that speeds up and is advanced, and the manufacturing technology of dynamic random access memory (DRAM) also is so, especially the most important especially key of the increase of its memory capacity.
Most now DRAM unit is made of capacitor of a transistor AND gate.Along with semiconductor technology develops with the direction that improves component density towards dwindling the semiconductor subassembly size, DRAM memory capacity also is increased to more than 512 megabits, so the area of base of memory cell must constantly reduce and makes integrated circuit can hold a large amount of memory cell and improve density in the memory.Require under the more and more higher situation in the assembly integration, memory cell and transistorized size need significantly be dwindled, and it is higher just may to produce memory capacity, and processing speed is DRAM faster.Yet the design of traditional stacking-type electric capacity can occupy the area of too many chip surface and can't meet the demand.
Utilize the technology of three-dimensional, can reduce the area of transistor AND gate capacitor shared cloth on the semiconductor-based end in large quantities, therefore the three-dimensional technology begins to be applied on the manufacture method of DRAM, for example groove-shaped capacitor, account for the sizable area of cloth semiconductor surface with respect to classic flat-plate formula transistor, can't satisfy the demand of Present Attitude productive setization, therefore groove-shaped capacitor can significantly improve the shortcoming of known semiconductor memory cell, becomes at present and the following main trend of making semiconductor memory cell.
Yet, in size constantly under the situation of granular, groove in the dynamic random access memory stores node capacitance (trench storage node capacitance) and also needs along with managing to increase storage capacitors to keep the good operating characteristics of memory, and the surface area that therefore must promote the memory cell channel capacitor is to store sufficient electric charge.Though groove-shaped electric capacity can because the groove-shaped electric capacity of high-aspect-ratio has its restriction on manufacture method, cause increasable gash depth to still have certain qualification by increasing the surface area that gash depth promotes electric capacity.
The method that has been widely used at present the storage capacitors that increases dynamic random access memory is for increasing the width of channel bottom, similarly be for example to form a bottle type channel capacitor (bottle shaped trench capacitor) that can improve surface area, as shown in Figure 1a, be the initial step that shows the manufacture method of a known doleiform groove.At first, on a silicon base 10, form a patterning bed course (pad layer) 12, be etching mask with this patterning bed course 12 then, utilize the dry ecthing mode in this silicon base 10, to form a groove 14, and this groove 14 has a top peripheral part 16 and a bottom peripheral part 18, and its opening microspur is 13.
Then, shown in Fig. 1 b, then deposit a photoresist layer 22 in this groove 14 of part and cover bottom peripheral part 18 of this groove 14.Afterwards, compliance deposits a sacrifice polysilicon layer 20 on these groove 14 top peripheral part 16.Then, shown in Fig. 1 c, remove the sacrifice polysilicon layer 20 that is positioned at this bed course 12 and part photoresist layer 22 top in the anisotropic etching mode.So, promptly form sacrifice polysilicon layer sidewall 24 on the top of groove 14 peripheral part 16.
At last; shown in Fig. 1 d; carry out a wet etching manufacture method (also claiming wet bottle etching manufacture method); with ammoniacal liquor or dilute hydrofluoric acid solution (dilute HF solution) isotropic etching not by the silicon base 10 of groove 14 downsides of sacrifice polysilicon layer 20 protection; and the bottle shaped portion 24 of formation groove 14, and these bottle shaped portion 24 its microspurs 15 are greater than the opening microspur 13 of this groove 14.A yet above-mentioned manufacture method palpus step complexity, need to make a bottle type groove again to divide other manufacture method to form deep trench earlier, because the etching manufacture method easily forms the groove of taper, therefore increase the degree of difficulty on the manufacture method, and because the doleiform groove during fabrication, the shape of wayward groove bottom and the width of doleiform groove cause the unsteadiness of manufacture method and the interference on the geometry, increase the degree of difficulty of manufacture method.
Therefore, under the prerequisite that does not increase gash depth and trench bottom width, develop and a kind ofly have that to increase the capacitance meter area be a important topic on the present dynamic random access memory manufacturing technology with the groove-shaped electric capacity that promotes storage capacitors.
Summary of the invention
The object of the present invention is to provide a kind of manufacture method of groove, be to utilize the manufacture of plural hard mask layer to change the groove shape of groove-shaped electric capacity, by groove to increase the surface area of groove-shaped electric capacity effectively, do not increase under the prerequisite of gash depth in the hope of reaching in the component height aggregationization, the ability that promotes storage capacitors is to keep the good operating characteristics of memory.
In addition, the invention provides a kind of manufacture method that under the situation that need not enlarge trench bottom width, can increase the groove-shaped electric capacity of electric capacity storage.
For obtaining above-mentioned purpose, the manufacture method of groove of the present invention comprises the following steps: to provide a substrate at least; Form a cushion layer structure in this substrate surface; Form one first hard mask layer on this cushion layer structure; Second hard mask layer that forms a patterning is on this first hard mask layer, and this first hard mask layer surface of exposed portions serve is to constitute one first opening; Form a wall in above-mentioned first opening sidewalls to constitute second a less opening; Form one the 3rd hard mask layer to fill up this second opening; Remove this wall, and with this second hard mask layer and the 3rd hard mask layer as this first hard mask layer of etching mask etching, form the 3rd opening of a tool one first hard mask layer ledge; And this first hard mask layer of etching, this first hard mask layer ledge, this cushion layer structure and this substrate, with the groove that forms ledge in the middle of the tool one in this substrate.
Manufacture method according to groove of the present invention, wherein this first hard mask layer of etching, this first hard mask layer ledge, this cushion layer structure and this substrate, the step of groove in this substrate of ledge is to comprise in the middle of the tool one to form: this first hard mask layer of etching, this first hard mask layer ledge, this cushion layer structure and this substrate, until removing this first hard mask layer ledge fully, in substrate, to form an annular recess; And this annular recess of being constituted of this substrate of etching and this cushion layer structure that exposes, with the groove that forms ledge in the middle of the tool one in this substrate.
Manufacture method according to groove of the present invention, wherein remove with etching mode this wall of part with this first hard mask layer surface of exposing this second hard mask layer surface and part with the step that constitutes this second opening in, the width of this second opening is to be inversely proportional to this space layer that forms.
According to the manufacture method of groove of the present invention, wherein the width of this centre ledge of this groove is to be directly proportional with the width of this second opening.
The manufacture method of groove of the present invention can also another way show, and comprises the following steps: to provide a substrate at least; Form a cushion layer structure in this substrate surface, this cushion layer structure is made of a pad oxide and a pad silicon nitride layer in regular turn; Form one first hard mask layer on this cushion layer structure; Second hard mask layer that forms a patterning is on this first hard mask layer, and this first hard mask layer surface of exposed portions serve is to constitute one first opening; Form a wall in above-mentioned first opening sidewalls to constitute second a less opening; Form one the 3rd hard mask layer in this first hard mask layer surface of exposing to fill up this second opening; The 3rd hard mask layer is carried out a flatening process be formed at the 3rd outer hard mask layer of this second opening with removal; Remove this wall, and with this second hard mask layer and the 3rd hard mask layer as this first hard mask layer of etching mask etching, form the 3rd opening of a tool one first hard mask layer ledge; Remove this second hard mask layer and the 3rd hard mask layer; This first hard mask layer of etching, this first hard mask layer ledge, this cushion layer structure and this substrate are until removing this first hard mask layer ledge fully, to form an annular recess in substrate; And this annular recess of being constituted of this substrate of etching, with the groove that forms ledge in the middle of the tool one in this substrate.
According to the manufacture method of groove of the present invention, wherein the groove of ledge more comprises forming a buried regions battery lead plate in the above-mentioned substrate of part that constitutes above-mentioned groove after the step of this substrate in the middle of formation one tool one; And form ring (collar) insulating barrier and at least the conductive layer of one deck in above-mentioned groove.
Description of drawings
Fig. 1 a to Fig. 1 d is section of structure, is the manufacturing process that illustrates the groove-shaped electric capacity of a known ampuliform;
Fig. 2 a to Fig. 2 k is section of structure, is the manufacturing process that illustrates according to the groove-shaped electric capacity of a preferred embodiment of the present invention.
Symbol description:
The 10-silicon base
12-patterning bed course
13-opening microspur
The 14-groove
15-channel bottom microspur
16-top peripheral part
18-bottom peripheral part
20-sacrifice polysilicon layer
22-photoresist layer
The 24-bottle shaped portion
The 100-substrate
The 102-cushion layer structure
Ledge in the middle of the 106-
110-first hard mask layer
The 110a-first hard mask layer ledge
112-second hard mask layer
114-the 3rd hard mask layer
The photoresist layer of 120-caseization
The 124-wall
130-first opening
132-second opening
134-the 3rd opening
The 136-annular recess
The 138-groove
140-buried regions battery lead plate
142-first conductive layer
144-second conductive layer
150-encircles insulating barrier
Embodiment
For above-mentioned purpose of the present invention, feature can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below:
Fig. 2 a to Fig. 2 j is the technological process profile that illustrates according to the groove of a preferred embodiment of the present invention.
At first, shown in Fig. 2 a, providing semiconductor substrate 100, for example is P type silicon base, N type silicon base or epitaxial silicon substrate.In narration of the present invention, " substrate " speech is to comprise established assembly and various the filming that covers on the wafer on the semiconductor crystal wafer, its top can form any required semiconductor subassembly, but herein for simplicity of illustration, only represents with smooth substrate.Form a cushion layer structure 102 on silicon base 100 surfaces, and this cushion layer structure 102, can for example be made of a pad oxide and a pad silicon nitride layer, be to form this pad oxide 102 earlier on the surface of substrate 100, forms this pad silicon nitride layer again on this pad oxide.This pad oxide wherein, can for example be silicon oxide layer, its thickness can be approximately 50-300 , and the formation method for example is to carry out thermal oxidation program (thermal oxidation) or form with aumospheric pressure cvd (APCVD), low-pressure chemical vapor deposition (LPCVD) mode under the temperature of 850-950 degree Celsius; This fills up silicon nitride layer, and its thickness can be approximately 1000-2000 , and the formation method is with SiCl under 750-800 ℃
2H
2And NH
3Mist carry out low-pressure chemical vapor deposition.
Then, shown in Fig. 2 b, form one first hard mask layer 110 and one second hard mask layer 112 in regular turn on this cushion layer structure, and on second hard mask layer, 112 surfaces coating one photoresist layer, and implement suitable photoetching manufacturing method and define required photoresist pattern 120.Wherein, the material of this first hard mask layer 110 can be boron-phosphorosilicate glass (BPSG), arsenic silex glass (AsSG), phosphorosilicate glass (PSG) or Pyrex (BSG), for example is Pyrex (BSG), and its formation method is with SiH
4, BF
3And B
2H
6Mist carry out the chemical vapour deposition (CVD) step, the thickness of formation is to can be 8000-15000 , and can for example be 13000 in this preferred embodiment; The material of this second hard mask layer 112 is the polysilicons that can be polysilicon (polysilicon) or mix, and the formation method can be for example for utilizing the Low Pressure Chemical Vapor Deposition (LPCVD) that mixes up synchronously to form, and its reacting gas is PH
3, SiH
4With N
2Or A sH
3, SiH
4With N
2Mist, reaction temperature is between 500 to 650 ℃, between the 1E21 atoms/cm, the thickness of formation is to can be 500-5000 to its concentration impurity ion, and can for example be 3000 in this preferred embodiment between 1E20.
Then, shown in Fig. 2 c, utilize the photoresist layer 120 of patterning to be used as etching mask, second hard mask layer 112 is implemented an anisotropic etching program, can for example be magnetic field enhanced active ion formula method for plasma etching (MERIE), Ecr plasma etching method (ECR) or traditional active ion formula method for plasma etching (RIE), its plasma reaction gas can for example be sulphur hexafluoride (SF
6), oxygen (O
2), chlorine (Cl
2) and the mist of hydrogen bromide (HBr), on design transfer to the second hard mask layer 112 with photoresist layer 120, and first hard mask layer, 110 surfaces of exposed portions serve, and form one first opening 130 that is positioned at second mask layer 112 and first mask layer 110 surface.And the width range of this first opening 130 is roughly the width range as the groove of groove-shaped electric capacity.Then, remove the photoresist layer with suitable solution or dry-etching program again.
Then, shown in Fig. 2 d, compliance forms a wall 124 on this second hard mask layer 112 and this first opening 130, wherein this wall 124 is made of dielectric material, it can for example be a nitrogenous silicide, its generation type can be Low Pressure Chemical Vapor Deposition (LPCVD), plasma enhanced chemical vapor deposition method (PECVD), high density plasma CVD method (HDPCVD), atmospheric chemical vapor deposition (APCVD) or subatmospheric chemical vapour deposition technique (SACVD), for example for utilizing Low Pressure Chemical Vapor Deposition, with dichlorosilane (SiCl
2H
2) and ammonia (NH
3) form for reaction raw materials deposits.Then, shown in Fig. 2 e, this wall 124 of anisotropic etching, for example utilize reactive ion etching (reactive ion etching, RIE) program, removal is positioned at this second hard mask layer 112 and these first hard mask layer, 110 lip-deep walls 124 of part, and formation one is positioned at one second opening 132 on this wall 124 and first mask layer, 110 surfaces.Above-mentioned steps is to be a self-aligned etching step.Wherein this wall 124 of etching part with the step of exposing this second opening 132 in, the width of this second opening 132 is that the thickness with this wall 124 that forms is inversely proportional to.
Then, shown in Fig. 2 f, form one the 3rd hard mask layer 114 in these first hard mask layer, 110 surfaces of exposing filling up this second breach 130, and the 3rd hard mask layer 114 carried out a flatening process be formed at the 3rd outer hard mask layer 114 of this second breach 130 with removal.Wherein, the 3rd hard mask layer 114 can be made of identical or different materials with this second hard mask layer 112, and the composition material of the 3rd hard mask layer 114 and this second hard mask layer 112 is different with the composition material of this wall 124 or this first hard mask layer.The 3rd hard mask layer 114 can for example be a polysilicon, and its reacting gas is PH
3, SiH
4With N
2Or AsH
3, SiH
4With N
2Mist, reaction temperature is between 500 to 650 ℃; And above-mentioned flatening process can for example be formed at this second breach 130 the 3rd hard mask layer 114 outward for utilizing a chemical mechanical milling method to remove.Wherein the width of this centre ledge of this groove is to be directly proportional with the width of this second opening.
Then, shown in Fig. 2 g, remove this wall 124 fully in a selective etch mode, to expose this first hard mask layer, 110 surfaces, the etching mode of wherein removing this wall 124 can be a wet etching, for example uses the phosphoric acid (phosphoric acid) through heating to carry out the etching as the silicon nitride of this wall 124.Then, shown in Fig. 2 h, with this second hard mask layer 112 and the 3rd hard mask layer 114 as etching mask, this first hard mask layer 110 is carried out etching, so that going up in these cushion layer structure 102 surfaces, this first hard mask layer 110 constitutes one the 3rd breach 134, and this first hard mask layer 110 has one first hard mask layer ledge 110a in the 3rd breach 134, and then remove this second hard mask layer 112 and the 3rd hard mask layer 114 fully with etching mode, for example with reactive ion etching (reactive ion etching, RIE) mode.
Then, shown in Fig. 2 i, this first hard mask layer 110 of etching, this first hard mask layer ledge 110a, this cushion layer structure 102 and this substrate 100 are until removing this first hard mask layer ledge 110a fully, to form an annular recess 136 in substrate 100.Owing to this first hard mask layer ledge 110a is positioned at the 3rd breach 134 to protrude from this cushion layer structure 102 surfaces, make this etching program except from its top, more can be by this first hard mask layer ledge 110a being carried out etching all around, the etch-rate that causes this first hard mask layer ledge 110a than the etch-rate of these first hard mask layer, 110 other parts come many soon, so when removing this first hard mask layer ledge 110a fully with etching, still have this first hard mask layer 110 to be positioned on this annular recess 136 this cushion layer structure outward.
Then, shown in Fig. 2 j, this annular recess 136 that this substrate 100 of etching is constituted, the groove 138 that forms a tool one middle ledge 106 is in this substrate 100, different with above-mentioned steps is that the etching emphasis of this step is this annular recess 136 that substrate 100 is constituted.Wherein the mode of this annular recess 136 of being constituted of this substrate of etching can be an anisotropic etching, for example utilize reactive ion etching (reactive ion etching, RIE), and with this first hard mask layer 110 as sacrifice layer.When etching process, this first hard mask layer 110 need have a necessary thickness to keep its function as etching mask, can form a photoresist layer in case of necessity with as etched sacrifice layer on this first hard mask layer 110.In the present invention, the degree of depth of the height of this centre ledge 106 and this groove 138 can be come modulation by changing the etching selectivity of first hard mask layer 110 with this substrate, and the degree of depth of this groove 138 also can be come modulation by the thickness that changes as this first hard mask layer 110 of etch sacrificial layer.At last, shown in Fig. 2 k, form buried regions battery lead plate 140, ring insulating barrier 150, first conductive layer 142 and second conductive layer 144 in groove 138 to constitute a dark flute capacitor.The method that wherein forms buried regions battery lead plate 140 can be utilized the silica glass of arsenic doped (Arsenic Doped Silicon DioxideGlass; ASG) layer and tetraethoxysilane (TEOS) layer are formed in the groove 138, drive in (drive in) then and in the interior buried regions battery lead plate 140 of this bottle type groove.
In sum, the present invention compares with known technology, and the manufacture method of the groove-shaped electric capacity of groove of the present invention has several advantages.At first, the present invention utilizes the manufacture of plural hard mask layer to change the groove shape of groove-shaped electric capacity, under the situation that does not increase gash depth and trench bottom width, increase the surface area of groove-shaped electric capacity and the ability of storage capacitors effectively with groove, this practice has been avoided known bottle type channel capacitor, and it makes difficulty, wayward channel bottom doleiform structure and the easy problems such as interference that form on the geometry.
Secondly, under situation about increasing for the capacity of asking dynamic random access memory, the area of base of memory cell must constantly reduce and makes integrated circuit can hold a large amount of memory cell and improve density in the memory, therefore dynamic random access memory also develops with the direction that improves density towards dwindling the semiconductor subassembly size in the manufacture method design, thus the groove width of electric capacity also with dwindle.Yet when groove width constantly reduces, the manufacture method degree of difficulty also constantly improves.When dynamic random memory process reached 0.11 μ m, desiring to scribe making method with photoengraving this moment, to define fine and closely woven pattern as second opening 132 be unusual difficulty.And the manufacture method of groove-shaped electric capacity of the present invention, be to carry out the formation of groove with a self-aligned etching step, even when dynamic random memory process reaches 0.11 μ m, still can form a ledge at the channel bottom of groove-shaped electric capacity with the change groove, and then it is long-pending to promote the ability of storage capacitors to increase table.
Claims (26)
1. the manufacture method of a groove comprises the following steps:
One substrate is provided;
Form a cushion layer structure in this substrate surface;
Form one first hard mask layer on this cushion layer structure;
Second hard mask layer that forms a patterning is on this first hard mask layer, and this first hard mask layer surface of exposed portions serve is to constitute one first opening;
Form a wall and want the second little opening to constitute an aperture efficiency first opening in above-mentioned first opening sidewalls;
Form one the 3rd hard mask layer to fill up this second opening;
Remove this wall, and with this second hard mask layer and the 3rd hard mask layer as this first hard mask layer of etching mask etching, form the 3rd opening with one first hard mask layer ledge;
Remove this second hard mask layer and the 3rd hard mask layer; And
This first hard mask layer of etching, this first hard mask layer ledge, this cushion layer structure and this substrate, to form the groove that has ledge in the middle of in this substrate, the upper surface of this centre ledge is lower than the upper surface of substrate.
2. the manufacture method of groove according to claim 1, wherein forming the 3rd hard mask layer in the step of this second opening, comprising that also the 3rd hard mask layer is carried out a flatening process is formed at the 3rd outer hard mask layer of this second opening with removal.
3. the manufacture method of groove according to claim 2, wherein this flatening process is a chemical mechanical milling method.
4. the manufacture method of groove according to claim 1, wherein this first hard mask layer material is to be selected from the group that is made up of boron-phosphorosilicate glass, arsenic silex glass, phosphorosilicate glass and Pyrex.
5. the manufacture method of groove according to claim 1, wherein this second hard mask layer material is the polysilicon of polysilicon or doping.
6. the manufacture method of groove according to claim 1, the material that wherein constitutes this second hard mask layer is identical with the material that constitutes the 3rd hard mask layer.
7. the manufacture method of groove according to claim 1, wherein this wall is made of dielectric material.
8. the manufacture method of groove according to claim 1, the method that wherein forms this wall dielectric layer is to comprise Low Pressure Chemical Vapor Deposition, plasma enhanced chemical vapor deposition method, high density plasma CVD method, atmospheric chemical vapor deposition or subatmospheric chemical vapour deposition technique.
9. the manufacture method of groove according to claim 1 wherein forms this cushion layer structure and comprises in the step of this substrate surface:
Form a pad oxide in this substrate surface; And
Form a pad silicon nitride layer in this pad oxide surface, wherein this pad oxide and this pad silicon nitride layer constitute this cushion layer structure.
10. the manufacture method of groove according to claim 1, wherein this first hard mask layer of etching, this first hard mask layer ledge, this cushion layer structure and this substrate, the step of groove in this substrate of ledge comprises in the middle of the tool one to form:
This first hard mask layer of etching, this first hard mask layer ledge, this cushion layer structure and this substrate are until removing this first hard mask layer ledge fully, to form an annular recess in substrate; And
This annular recess that this substrate of etching is constituted and this cushion layer structure that exposes are to form the groove that has ledge in the middle of in this substrate.
11. the manufacture method of groove according to claim 10, wherein in the step of this first hard mask layer of etching, this first hard mask layer ledge, this cushion layer structure and this substrate, when removing this first hard mask layer ledge fully, still have this first hard mask layer to be positioned on this outer cushion layer structure of this annular recess.
12. the manufacture method of groove according to claim 1, wherein this wall of etching part with the step of exposing this second opening in, the thickness of the width of this second opening and this wall of formation is inversely proportional to.
13. the manufacture method of groove according to claim 12, wherein the width of this centre ledge of this groove is directly proportional with the width of this second opening.
14. the manufacture method of groove according to claim 1, wherein the groove of ledge also comprises after the step of this substrate in the middle of formation one tool one:
Form a buried regions battery lead plate in the above-mentioned substrate of part that constitutes above-mentioned groove; And
Form a ring insulating barrier and at least the conductive layer of one deck in above-mentioned groove.
15. the manufacture method of a groove comprises the following steps:
One substrate is provided;
Form a cushion layer structure in this substrate surface, this cushion layer structure is made of a pad oxide and a pad silicon nitride layer in regular turn;
Form one first hard mask layer on this cushion layer structure;
Second hard mask layer that forms a patterning is on this first hard mask layer, and this first hard mask layer surface of exposed portions serve is to constitute one first opening;
Form a wall and want the second little opening to constitute an aperture efficiency first opening in above-mentioned first opening sidewalls;
Form one the 3rd hard mask layer in this first hard mask layer surface of exposing to fill up this second opening;
The 3rd hard mask layer is carried out a flatening process be formed at the 3rd outer hard mask layer of this second opening with removal;
Remove this wall, and with this second hard mask layer and the 3rd hard mask layer as this first hard mask layer of etching mask etching, form the 3rd opening of a tool one first hard mask layer ledge;
Remove this second hard mask layer and the 3rd hard mask layer;
This first hard mask layer of etching, this first hard mask layer ledge, this cushion layer structure and this substrate are until removing this first hard mask layer ledge fully, to form an annular recess in substrate; And
This annular recess that this substrate of etching is constituted, with the groove that forms ledge in the middle of the tool one in this substrate.
16. the manufacture method of groove according to claim 15, wherein this flatening process is a chemical mechanical milling method.
17. the manufacture method of groove according to claim 15, this pad oxide that wherein constitutes this cushion layer structure is formed by thermal oxidation method.
18. the manufacture method of groove according to claim 15, wherein this first hard mask layer material is to be selected from the group that is made up of boron-phosphorosilicate glass, arsenic silex glass, phosphorosilicate glass and Pyrex.
19. the manufacture method of groove according to claim 15, wherein this second hard mask layer material is the polysilicon of polysilicon or doping.
20. the manufacture method of groove according to claim 15, the material that wherein constitutes this second hard mask layer is identical with the material that constitutes the 3rd hard mask layer.
21. the manufacture method of groove according to claim 15, wherein this wall is made of dielectric material.
22. the manufacture method of groove according to claim 15, the method that wherein forms this wall dielectric layer are to comprise Low Pressure Chemical Vapor Deposition, plasma enhanced chemical vapor deposition method, high density plasma CVD method, atmospheric chemical vapor deposition or subatmospheric chemical vapour deposition technique.
23. the manufacture method of groove according to claim 15, wherein in the step of this first hard mask layer of etching, this first hard mask layer ledge, this cushion layer structure and this substrate, when removing this first hard mask layer ledge fully, still have this first hard mask layer to be positioned on this outer cushion layer structure of this annular recess.
24. the manufacture method of groove according to claim 15, wherein this wall of etching part with the step of exposing this second opening in, the thickness of the width of this second opening and this wall of formation is inversely proportional to.
25. the manufacture method of groove according to claim 24, wherein the width of this centre ledge of this groove is directly proportional with the width of this second opening.
26. the manufacture method of groove according to claim 15, wherein the groove of ledge also comprises after the step of this substrate in the middle of formation one tool one:
Form a buried regions battery lead plate in the above-mentioned substrate of part that constitutes above-mentioned groove; And
Form a ring insulating barrier and at least the conductive layer of one deck in above-mentioned groove.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031463746A CN1319153C (en) | 2003-07-10 | 2003-07-10 | Process for making trench capacitor having geometric shape trench |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031463746A CN1319153C (en) | 2003-07-10 | 2003-07-10 | Process for making trench capacitor having geometric shape trench |
Publications (2)
| Publication Number | Publication Date |
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| CN1567571A CN1567571A (en) | 2005-01-19 |
| CN1319153C true CN1319153C (en) | 2007-05-30 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB031463746A Expired - Lifetime CN1319153C (en) | 2003-07-10 | 2003-07-10 | Process for making trench capacitor having geometric shape trench |
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| CN (1) | CN1319153C (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102270567A (en) * | 2010-06-04 | 2011-12-07 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing capacitor |
| US9991363B1 (en) * | 2017-07-24 | 2018-06-05 | Globalfoundries Inc. | Contact etch stop layer with sacrificial polysilicon layer |
| TWI691052B (en) * | 2019-05-07 | 2020-04-11 | 力晶積成電子製造股份有限公司 | Memory structure and manufacturing method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4650544A (en) * | 1985-04-19 | 1987-03-17 | Advanced Micro Devices, Inc. | Shallow groove capacitor fabrication method |
| CN1166054A (en) * | 1997-05-12 | 1997-11-26 | 世界先进积体电路股份有限公司 | Method for producing capacitor by utilizing etching tech. |
| CN1230018A (en) * | 1998-01-27 | 1999-09-29 | 国际商业机器公司 | Fabrication of trench capacitors using disposable hard mask |
| CN1236991A (en) * | 1998-05-27 | 1999-12-01 | 世界先进积体电路股份有限公司 | Method for manufacturing capacitor structure of high-density DRAM |
| US6020230A (en) * | 1998-04-22 | 2000-02-01 | Texas Instruments-Acer Incorporated | Process to fabricate planarized deep-shallow trench isolation having upper and lower portions with oxidized semiconductor trench fill in the upper portion and semiconductor trench fill in the lower portion |
-
2003
- 2003-07-10 CN CNB031463746A patent/CN1319153C/en not_active Expired - Lifetime
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4650544A (en) * | 1985-04-19 | 1987-03-17 | Advanced Micro Devices, Inc. | Shallow groove capacitor fabrication method |
| CN1166054A (en) * | 1997-05-12 | 1997-11-26 | 世界先进积体电路股份有限公司 | Method for producing capacitor by utilizing etching tech. |
| CN1230018A (en) * | 1998-01-27 | 1999-09-29 | 国际商业机器公司 | Fabrication of trench capacitors using disposable hard mask |
| US6020230A (en) * | 1998-04-22 | 2000-02-01 | Texas Instruments-Acer Incorporated | Process to fabricate planarized deep-shallow trench isolation having upper and lower portions with oxidized semiconductor trench fill in the upper portion and semiconductor trench fill in the lower portion |
| CN1236991A (en) * | 1998-05-27 | 1999-12-01 | 世界先进积体电路股份有限公司 | Method for manufacturing capacitor structure of high-density DRAM |
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| CN1567571A (en) | 2005-01-19 |
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