CN1236991A - Method for manufacturing capacitor structure of high-density DRAM - Google Patents
Method for manufacturing capacitor structure of high-density DRAM Download PDFInfo
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- CN1236991A CN1236991A CN98109314A CN98109314A CN1236991A CN 1236991 A CN1236991 A CN 1236991A CN 98109314 A CN98109314 A CN 98109314A CN 98109314 A CN98109314 A CN 98109314A CN 1236991 A CN1236991 A CN 1236991A
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- 239000003990 capacitor Substances 0.000 title claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 238000000034 method Methods 0.000 title claims description 79
- 238000003860 storage Methods 0.000 claims abstract description 50
- 238000005516 engineering process Methods 0.000 claims abstract description 13
- 239000004065 semiconductor Substances 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 230000004888 barrier function Effects 0.000 claims description 119
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 99
- 229920005591 polysilicon Polymers 0.000 claims description 97
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 76
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 76
- 239000000428 dust Substances 0.000 claims description 47
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 35
- 238000000151 deposition Methods 0.000 claims description 29
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 27
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 27
- 229910052710 silicon Inorganic materials 0.000 claims description 27
- 239000010703 silicon Substances 0.000 claims description 27
- 230000008021 deposition Effects 0.000 claims description 26
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 15
- 230000015572 biosynthetic process Effects 0.000 claims description 13
- 239000013078 crystal Substances 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 13
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 12
- 229910052785 arsenic Inorganic materials 0.000 claims description 12
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 12
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 8
- 230000003647 oxidation Effects 0.000 claims description 8
- 238000007254 oxidation reaction Methods 0.000 claims description 8
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 7
- -1 phosphonium ion Chemical class 0.000 claims description 6
- 229910052698 phosphorus Inorganic materials 0.000 claims description 5
- 239000011574 phosphorus Substances 0.000 claims description 5
- 239000010409 thin film Substances 0.000 claims description 4
- 238000010276 construction Methods 0.000 claims description 3
- 239000011521 glass Substances 0.000 claims description 3
- 239000007788 liquid Substances 0.000 claims description 3
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- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims 10
- 238000000227 grinding Methods 0.000 claims 2
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 claims 2
- 239000003795 chemical substances by application Substances 0.000 claims 1
- 230000003628 erosive effect Effects 0.000 claims 1
- VIKNJXKGJWUCNN-XGXHKTLJSA-N norethisterone Chemical compound O=C1CC[C@@H]2[C@H]3CC[C@](C)([C@](CC4)(O)C#C)[C@@H]4[C@@H]3CCC2=C1 VIKNJXKGJWUCNN-XGXHKTLJSA-N 0.000 claims 1
- 238000004528 spin coating Methods 0.000 claims 1
- 238000001020 plasma etching Methods 0.000 description 9
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 239000000377 silicon dioxide Substances 0.000 description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
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- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
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- 150000002500 ions Chemical class 0.000 description 1
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- 230000010415 tropism Effects 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Abstract
A technology for manufacturing the capacitor structure of high-density DRAM features that a deep-pocket COB structure is formed on semiconductor substrate in order to increase the surface area of capacitor for higher capacity of capacitor, and an insulating gap wall is formed between storage node structure and bit line structure in order to prevent the residual HSG from staying outside the contact hole of storage node for minimizing the space between nodes, solving insulating problem and improving product.
Description
The present invention relates to the manufacture method of a kind of dynamic random access memory (DRAM) element, particularly relate to a kind of manufacture method of DRAM element capacitor arrangement.
The development of high density DRAM element often is subject to its capacitor arrangement, and new capacitor design must make capacitance increase to purpose to increase capacitor area.For example the 5th of Kim the, 447, No. 882 United States Patent (USP) is just described a kind of stacked capacitor that is applicable to, be shaped as the new memory node profile (storage node configuration) of imperial crown shape, its feature comprises the structure of utilizing polysilicon outstanding, with the surface area of increase capacitor, yet, the method will increase the complexity of technology, and can not provide high density DRAM unit required surface area.
Another increases the long-pending method of capacitor surface for using the COB structure of " form bit line earlier and form capacitor (capacitor over bit line) again ", provides the DRAM unit also can increase the capacitance of DRAM in the minimized while.For example the 5th, 478 of Iwasa the, No. 768 United States Patent (USP) is just described a kind of storage node contact hole hole (storage node contact hole) that is applied to, and uses new technology to increase the COB structure of memory node electric capacity.The COB capacitor arrangement of a dark pocket (deep pocket) is described in this invention, it is characterized by semi-round ball silicon crystal grain (Hemispherical Silicon Grained, HSG) layer only is formed at the inner surface in storage node contact hole hole, surface area is increased, yet, therefore can't obtain to minimize nodal pitch for avoiding HSG to remain in outside the storage node contact hole hole.The present invention will propose to form insulating gap wall between storage node structure and bit line structure, help to improve the problem of insulation and the result of production.
Therefore, it is long-pending to the objective of the invention is to increase capacitor surface, to be applied in the highdensity DRAM unit.
Another object of the present invention is to form a dark pocket COB structure, use a hsg polysilicon layer to be formed on the inner surface in storage node contact hole hole.
Another purpose of the present invention is to use two silicon nitride layers, and one is formed on the bit line structure, and another is formed on the silicon oxide layer that places bit line, required etching selectivity when providing the storage node contact hole hole to form.
A further object of the present invention is to use between memory node and bit line structure the silica clearance wall, to increase the generation of isolating.
For achieving the above object, the invention provides a kind of manufacture method of high density DRAM capacitor arrangement, an its transfer gate transistor, polysilicon bit line structure and at formation bottom in the semiconductor substrate is positioned at the stack capacitance structure on this polysilicon bit line structure, and this method may further comprise the steps: form this transistor grid structure that coats with a silicon nitride layer; Deposition one first insulating barrier on this transfer gate transistor; Form this polysilicon bit line structure, be overlying on this first insulating barrier, and contact with this first source/drain region in this first insulating barrier, to form a contact hole hole; On this polysilicon bit line structure, and the upper surface of this first insulating barrier deposits silicon nitride layer between a ground floor; Deposition series of thin rete comprises silicon nitride layer between one second insulating barrier, a second layer, one the 3rd insulating barrier and one second polysilicon layer on silicon nitride layer between this ground floor; In this series thin film layer, the boundary forms one first memory node opening between this polysilicon bit line structure; In this first memory node opening, the side that exposes to the open air of the 3rd insulating barrier and this second insulating barrier forms depression; Deposit one the 4th insulating barrier; With this first memory node opening is that a mask forms a storage node contacts fenestra hole, it removes via silicon nitride layer and this first insulating barrier between the 4th insulating barrier, this ground floor, make second source/drain region expose to the open air out, and, form insulating gap wall by the side that exposes to the open air of the 4th insulating barrier at this second insulating barrier and this polysilicon bit line structure; Deposit one the 3rd polysilicon layer, as one man to be coated in this storage node contacts fenestra hole; Deposition one dome-type grain silicon layer on the 3rd polysilicon layer; Remove this dome-type crystal grain silicon layer, the 3rd polysilicon layer and this second polysilicon layer from the 3rd insulating barrier upper surface; Remove the 3rd insulating barrier from silicon nitride layer upper surface between this second layer, to form a storage node structure, comprise this dome-type crystal grain silicon layer on upper strata and the 3rd polysilicon layer of lower floor, in this storage node contacts fenestra hole, form and comprise this dome-type crystal grain silicon layer and the 3rd polysilicon layer, from silicon nitride layer surface between this second layer to extending out the outstanding shape of stretching; On this storage node structure, form a capacitor dielectric; And form a top electrode, to finish this stack capacitor structure that places this polysilicon bit line structure top.
The present invention also provides a kind of method of making high density DRAM capacitor arrangement on the other hand, and it forms a dark pocket COB structure in the semiconductor substrate, and this method may further comprise the steps: a transfer gate transistor was provided on this semiconductor-based end; Form this polysilicon bit line structure, be overlying on this first insulating barrier, and contact with this first source/drain region with the contact hole hole in this first insulating barrier; Deposit silicon nitride layer between a ground floor, to cover this polysilicon bit line structure fully; Deposition one second insulating barrier on silicon nitride layer between this ground floor; This second insulating barrier of planarization; Depositing silicon nitride layer between a second layer on this second insulating barrier; Deposition one the 3rd insulating barrier on silicon nitride layer between this second layer; Deposition one first polysilicon layer on the 3rd insulating barrier; Between this first polysilicon layer, the 3rd insulating barrier, this second layer, in silicon nitride layer and this second insulating barrier, terminate in silicon nitride layer upper surface between this ground floor, and the boundary forms one first memory node opening between this polysilicon bit line structure; In this first memory node opening, form depression at the side that exposes to the open air of the 3rd insulating barrier and this second insulating barrier; Deposit one the 4th insulating barrier, to fill up the depression in the 3rd insulating barrier and this second insulating barrier; In this first memory node opening, the 4th insulating barrier of silicon nitride layer and this first insulating barrier between this ground floor of isotropic etching, to form a dark pocket storage node contact hole hole, make the second source/drain region of this transfering transistor when insulating gap wall forms, expose to the open air out, comprise the 4th insulating barrier on the silicon nitride side that covers the polysilicon bit line; Deposition one second polysilicon layer on this first polysilicon layer surface, and as one man be coated in this dark pocket storage node contacts fenestra hole, make it to contact with this second source/drain region; Deposition one dome-type grain silicon layer on this second polysilicon layer; Fill up this dark pocket storage node contacts fenestra hole with the 4th insulating barrier; Remove this dome-type crystal grain silicon layer, this second polysilicon layer and this first polysilicon layer from the 3rd insulating barrier upper surface; Remove the 4th insulating barrier from silicon nitride layer upper surface between this dark pocket, storage node contacts fenestra hole and this second layer, to form a storage node structure, comprise this dome-type crystal grain silicon layer and this second polysilicon layer in this dark pocket storage node contacts fenestra hole; On this storage node structure, form a capacitor dielectric; Deposition one the 3rd polysilicon layer on this capacitor dielectric; And limit the 3rd poly-silicon pattern, to form the top electrode of this dark pocket COB structure.
For above-mentioned and other purposes of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. elaborates.In the accompanying drawing:
Fig. 1 illustrates a top view of DRAM unit with COB structure of dark pocket;
Fig. 2 a-11a illustrates along AA ＇ direction among Fig. 1, has the technological process profile of the COB structure DRAM unit of dark pocket; And
Fig. 2 b-11b illustrates along BB ' direction among Fig. 1, and is vertical with Fig. 2 a-11a profile direction, has the technological process profile of the COB structure DRAM unit of dark pocket.
The method that the DRAM unit of the following stated dark pocket COB structure of the present invention forms will be example with mos field effect transistor (NFET) element of N type, but be equally applicable to P-type mos field-effect transistor (PFET) element.
Please refer to Fig. 1, it illustrates the top view of the DRAM unit with dark pocket COB structure.Word line WL makes with polysilicon gate construction, across on element region 1 and the boundary in 2 of field oxide regions.The semiconductor-based end 1 up line BL contacts with the silicon cell district at bit line contact hole 24, and all the other places then isolate silicon cell district and word line BL with a thick dielectric layer (not illustrating).Storage node contact hole hole 17a and COB structure 25 are then as shown in the figure.
Please provide a monocrystalline to arrange＜100 simultaneously with reference to Fig. 2 a and 2b〉the P type semiconductor substrate, wherein Fig. 2 a is the profile along AA ' line of Fig. 1, Fig. 2 b then is the profile along BB ' line.Field oxide among Fig. 2 (FOX) 2 is in order to isolate, can be by under an oxygen atmosphere, obtaining with the about 850-1050 of temperature ℃ thermal oxidation, thickness is about the 3000-5000 dust, be to utilize an oxidation photomask limiting pattern made from silicon-nitride and silicon oxide, make and form field oxide district 2 in the substrate 1, with hot phosphoric acid solution the silicon nitride of upper strata photomask is removed again afterwards, and removed the silica of lower floor's photomask with hydrofluoric acid cushioning liquid.
After a succession of wet-cleaned, with the about 850-1050 of temperature ℃ formation, thickness is about the 50-200 dust to a grid oxic horizon 3 under an oxygen atmosphere.Then, with low-pressure chemical vapor deposition (LPCVD) method,, form the thickness that is about the 1500-4000 dust at the about 500-700 of temperature ℃ deposit one polysilicon layer 4.This polysilicon can be by implanting via the ion of arsenic or phosphorus after the growth again, with the about 30-80KeV of energy, and dosage about 1 * 10
13-1 * 10
16Atom/cm
2Form, or, form down via adding arsenic or phosphorus environment in silicomethane by growing simultaneously and implant procedure.Afterwards, a top cover oxide layer 5, for example comprising a silicon nitride layer or a lower floor is silica, the upper strata is the combination layer of silicon nitride, forms the about 1000-3000 dust of thickness with LPCVD or plasma reinforced chemical vapour deposition (PECVD) method.Traditional photoetching and reactive ion etching (RIE) use CHF
3Be the etchant of top cover oxide layer 5, use Cl
2Be the etchant of polysilicon layer 4, to form polysilicon gate construction as the DRAM word line of Fig. 2 a.Fig. 2 b then is the section between two polysilicon word lines, so there is not this structure.At last, photoresist can be cleaned and wet-cleaned removal completely by plasma oxygen.
One lightly-doped source/drain region 6 is by implanting phosphonium ion, with the about 20-50KeV of energy, and dosage about 1 * 10
13-1 * 10
14Atom/cm
2Form, shown in Fig. 2 a.One silicon nitride sidewall insulating barrier, an or lower floor is the combination layer of silicon nitride for the silica upper strata with LPCVD or PECVD method, is about the thickness of 1500-4000 dust in the about 400-700 of temperature ℃ formation, again with isotropism (waiting the tropism) RIE technology, uses Cl
2For the etchant of silicon nitride (if the abutment wall insulating barrier of combination needs earlier with CHF
3Be the etchant etching oxide layer) form the silicon nitride gap wall 7 that Fig. 2 a is positioned at the polysilicon word line abutment wall.The polysilicon word line of this moment is encased with silicon nitride gap wall 7 by the top cover oxide layer 5 of silicon nitride, replants into arsenic ion, and with the about 30-80KeV of energy, dosage about 1 * 10
15-1 * 10
16Atom/cm
2Form one heavy-doped source/drain region 8.The result is shown in Fig. 2 a, 2b.
Then form one first insulating barrier 9, comprise, use tetraethyl-metasilicate (TEOS) to be the formed silica of gas source with LPCVD or PECVD, or the boron-phosphorosilicate glass (BPSG) that forms with LPCVD or PECVD equally, thickness is about the 2000-7000 dust.Fig. 2 a-2b does not show the opening of Fig. 1 neutrality line contact hole 24, and it is by conventional lithography and RIE technology, uses CHF
3Be etchant, etching first insulating barrier 9 is finished to expose heavy-doped source/drain region 8.At last, one first polysilicon layer 10a is with the LPCVD method, the thickness of the about 500-700 of the temperature ℃ of about 1000-3000 dust of deposition, wherein, the first polysilicon layer 10a can be by forming via implanting arsenic or phosphonium ion after the growth again, or, form down via adding arsenic or phosphorus environment, and also can cover one deck tungsten silicide layer on the first polysilicon layer 10a to increase conductivity in silicomethane by growing simultaneously and implanted prosthetics.
Next limit the first polysilicon layer 10a,, use Cl with conventional lithography and isotropism RIE technology
2Be etchant, form bit line structure 10b as Fig. 3 b.Wherein can find out the situation that the first polysilicon 10a is removed by Fig. 3 a.Then, form silicon nitride layer 11 between a ground floor, cover fully on first insulating barrier 9 of the bit line structure 10b of Fig. 3 b and Fig. 3 a.Between ground floor silicon nitride layer 11 is with LPCVD or PECVD method, and temperature is about 500-850 ℃ of formation, and deposit thickness is about the 500-1000 dust.
Please refer to Fig. 4 a, 4b, it illustrates produces required insulating barrier and the polysilicon layer that forms successively in storage electrode contact hole of the present invention hole.One second insulating barrier 12 can be equally and comprises silicon oxide layer or the bpsg layer that is grown up to TEOS, uses PEVCD or LPCVD, the about 4000-7000 dust of deposit thickness on silicon nitride layer between ground floor 11; Utilize a cmp (CMP) or E method planarization second insulating barrier 12 to make it have smooth outward appearance; Re-use LPCVD or pecvd process, at the about 500-850 of temperature ℃, silicon nitride layer 13 between the second layer of the about 500-1000 dust of deposit thickness; Deposit one the 3rd insulating barrier 14 with LPCVD or PECVD method again, can be equally and comprise silicon oxide layer or the bpsg layer that is grown up to TEOS, thickness then is about the 3000-8000 dust; Last second polysilicon layer 15 is with LPCVD method deposition, and in temperature 500-700 ℃ formation, thickness is about the 500-2000 dust.
Next step forms the first memory node opening 17a in storage node contact hole hole, utilize photoresist 16 to be mask, etch away the silicon nitride layer 13 and second insulating barrier 12 between part second polysilicon layer 15, the 3rd insulating barrier 14, the second layer with isotropism RIE method, to expose silicon nitride layer 11 between ground floor, produce the first memory node opening 17a.Cl is adopted in this etching
2Be the etchant of silicon nitride layer 13 between second polysilicon layer 15 and the second layer, and with CHF
3Be the etchant of the 3rd insulating barrier 14 and the second exhausted layer 12, compare CHF with second insulating barrier 12
3The silicon nitride etch selectivity is had the lower rate that removes, can avoid that silicon nitride layer 11 is penetrated between ground floor, the result is shown in Fig. 5 a.The same demonstration of Fig. 5 b exposes silicon nitride layer 11 between the ground floor that covers bit line 10b.
Then, the first memory node opening 17a is subjected to the isotropism wet etching of buffered hydrofluoric acid solution, make the 3rd insulating barrier 14 and second insulating barrier, 12 surfaces of exposing to the open air in the first opening 17a, etchedly under the silicon nitride layer 13 between second polysilicon layer 15 and the second layer respectively go out a depression.Afterwards, form one the 4th insulating barrier 18a, for example with LPCVD or PECVD method, use TEOS to be gas source, the silica of the about 500-1000 dust of deposit thickness is evenly to cover in the first opening 17a, insert the depression of the 3rd insulating barrier 14 and second insulating barrier 12, the result is shown in Fig. 6 a, 6b.
Next form dark pocket memory node opening 17b.At the first opening 17a,, use CHF by an isotropism RIE method
3Be the etchant of the 4th insulating barrier 18a and first insulating barrier 9, Cl
2Be the etchant of silicon nitride layer between ground floor 11, make source/drain region 8 expose to the open air out, formation has dark pocket memory node opening 17b as Fig. 7 a, 7b.When removing the 4th insulating barrier 18a, the depression of the 3rd insulating barrier 14 is removed, and keeps second insulating barrier, 12 surperficial formed insulating gap wall 18b, as polysilicon bit line additional passivation (passivation) protection that is coated with silicon nitride.In addition, insulating gap wall 18b only is formed on the zone that joins with first insulating barrier 9, therefore produces a dark pocket storage node contact hole hole that diminishes gradually, the i.e. big structure of top radius ratio bottom radius shown in Fig. 7 a, 7b.
Please refer to Fig. 8 a, 8b, it illustrates next with the storage node structure that forms.With the LPCVD method, be about the 3rd polysilicon layer 19 of the 500-700 ℃ of about 700-1500 dust of deposition one thickness in temperature earlier.It can be replanted after deposition into arsenic or phosphonium ion, or the while adds arsenic when deposition or phosphorus forms under the silicomethane environment.Use the LPCVD method, at the about 500-600 of temperature ℃, the about 5-10Torr of pressure, dome-type crystal grain (HSG) silicon layer 20 of the about 300-700 dust of formation thickness.Can produce HSG silicon layer under these conditions, can make that surface area greatly improves with concavo-convex contoured surface.Afterwards, forming one again revolves and covers glass (SOG) layer, a bpsg layer or a photoresist layer 21, to fill up dark pocket storage node contact hole hole 17b, and optionally grind away HSG silicon layer 20, the 3rd polysilicon layer 19 and second polysilicon layer 15 on the 3rd insulating barrier 14 with the CMP method, to limit storage node structure 30; Or with RIE method use Cl
2Be above-mentioned each layer of etchant selective etch, form the result shown in Fig. 9 a, 9b.
Figure 10 a, 10b illustrate SOG layer (or bpsg layer) 21 are removed from dark pocket node contact hole hole 17b, re-using hydrofluoric acid solution simultaneously removes the 3rd insulating barrier 14, produce a storage node structure 30, formation is from the outstanding shape that silicon nitride layer between the second layer 13 outwards stretches, and making increases extra surface area.If filling dark pocket storage node contact hole hole 17b is photoresist, then need to remove photoresist with the plasma oxygen clean, remove the 3rd insulating barrier 14 with hydrofluoric acid solution again.
The final dark pocket COB structure 23 that forms is shown in Figure 11 a, 11b.Be formed on the storage node structure 30 with a capacitance dielectric layer 22 earlier, can be the nitration case (ONO) of oxidation, be equivalent to the silicon oxide layer of the about 40-80 dust of a thickness.It forms the silicon oxide layer of the about 10-20 dust of a thickness earlier by thermal oxidation method; Deposit thickness is about the silicon nitride layer of 10-50 dust, and reoxidizing this silicon nitride layer is the nitric oxide silicon layer to change the upper strata.Then, under the about 500-700 of temperature ℃, form the 4th polysilicon layer 22 that a thickness is about the 1000-3000 dust, can after deposition, replant equally, or the while adds arsenic when deposition or phosphorus forms under the silicomethane environment into arsenic or phosphonium ion with the LPCVD method.Utilize photoetching and RIE technology again, with Cl
2Be the etchant of the 4th polysilicon layer 22 and capacitance dielectric layer 21, produce dark pocket COB structure 23.Sentencing plasma after photoresist is removed again cleans and wet type cleaning completely.
Though the present invention discloses as above in conjunction with a preferred embodiment; but it is not in order to limit the present invention; those skilled in the art can make various changes and retouching without departing from the spirit and scope of the present invention, so protection scope of the present invention should be limited by accompanying Claim.
Claims (32)
1. the manufacture method of a high density DRAM capacitor arrangement, an its transfer gate transistor, polysilicon bit line structure and at formation bottom in the semiconductor substrate is positioned at the stack capacitance structure on this polysilicon bit line structure, and this method may further comprise the steps:
This transistor grid structure that formation coats with a silicon nitride layer;
Deposition one first insulating barrier on this transfer gate transistor;
Form this polysilicon bit line structure, be overlying on this first insulating barrier, and contact with this first source/drain region in this first insulating barrier, to form a contact hole hole;
Depositing the silicon nitride layer between a ground floor and the upper surface of this first insulating barrier on this polysilicon bit line structure;
Deposition series of thin rete comprises silicon nitride layer between one second insulating barrier, a second layer, one the 3rd insulating barrier and one second polysilicon layer on silicon nitride layer between this ground floor;
In this series thin film layer, the boundary forms one first memory node opening between this polysilicon bit line structure:
In this first memory node opening, the side that exposes to the open air of the 3rd insulating barrier and this second insulating barrier forms depression;
Deposit one the 4th insulating barrier;
With this first memory node opening is that a mask forms a storage node contacts fenestra hole, it removes via silicon nitride layer and this first insulating barrier between the 4th insulating barrier, this ground floor, make second source/drain region expose to the open air out, and, form insulating gap wall by the side that exposes to the open air of the 4th insulating barrier at this second insulating barrier and this polysilicon bit line structure;
Deposit one the 3rd polysilicon layer, as one man to be coated in this storage node contacts fenestra hole;
Deposition one dome-type grain silicon layer on the 3rd polysilicon layer;
Remove this dome-type crystal grain silicon layer, the 3rd polysilicon layer and this second polysilicon layer from the 3rd insulating barrier upper surface;
Remove the 3rd insulating barrier from silicon nitride layer upper surface between this second layer, to form a storage node structure, comprise this dome-type crystal grain silicon layer on upper strata and the 3rd polysilicon layer of lower floor, in this storage node contacts fenestra hole, form and comprise this dome-type crystal grain silicon layer and the 3rd polysilicon layer, from silicon nitride layer surface between this second layer to extending out the outstanding shape of stretching;
On this storage node structure, form a capacitor dielectric; And
Form a top electrode, to finish this stack capacitor structure that places this polysilicon bit line structure top.
2. the method for claim 1, wherein this transfer gate transistor also comprises a polysilicon gate construction, is positioned on the grid oxic horizon that a thickness is about the 50-200 dust, is coated with a silicon nitride layer and has the silicon nitride sidewall clearance wall of N type source/drain region.
3. the method for claim 1, wherein this polysilicon bit line structure is by the LPCVD method, at the about 500-700 of temperature ℃, deposits the polysilicon layer that a thickness is about the 1000-3000 dust, again via RIE technology with Cl
2For the etchant limiting pattern forms.
4. the method for claim 1, wherein silicon nitride layer is with one of LPCVD, PECVD between this ground floor, at the about 500-850 of temperature ℃, deposits that the about 500-1000 dust of a thickness forms.
5. the method for claim 1, place wherein that this serial thin layer on the silicon nitride layer also comprises between this ground floor: be the formed oxide layer of gas source with TEOS, or be about a bpsg layer of 4000-7000 dust with the thickness that one of LPCVD, PECVD are deposited, form second insulating barrier of a bottom; With one of PECVD, LPCVD, silicon nitride layer between a second layer of the about 500-850 of the temperature ℃ about 500-1000 dust of the thickness that is deposited; With TEOS is the formed oxide layer of gas source, or is about a bpsg layer of 3000-8000 dust with the thickness that one of LPCVD, PECVD are deposited, and forms one the 3rd insulating barrier; And use the LPCVD method, at the about 500-700 dust of temperature, one second polysilicon layer of the about 500-2000 dust of the thickness that is deposited.
6. the method for claim 1, wherein this first memory node opening is got through RIE technology by this series thin film layer, uses Cl respectively
2Etchant for silicon nitride layer between this second polysilicon layer and this second layer; And use CHF
3Etchant for the 3rd insulating barrier and this second insulating barrier.
7. the method for claim 1 wherein at the side that exposes to the open air of the 3rd insulating barrier and second insulating barrier, is positioned at the formed depression of this first memory node opening and is to use a hydrofluoric acid cushioning liquid etching and gets.
8. the method for claim 1, wherein be positioned at this insulating gap wall on the silicon nitride side of this second insulating barrier and passivation, this polysilicon bit line structure in this storage node contacts window opening hole, it is method deposition silicon monoxide by one of LPCVD, PECVD, form the 4th insulating barrier that a thickness is about the 500-1000 dust, re-use CHF afterwards
3For etchant is done isotropism RIE etching.
9. the method for claim 1, wherein this storage node contact hole hole is by isotropism RIE technology, with CHF
3For the etchant of the 4th insulating barrier and this first insulating barrier, with Cl
2By the etchant of this ground floor silicon nitride is formed.
10. the method for claim 1, wherein the 3rd polysilicon layer is via the LPCVD method, at the about 500-700 of temperature ℃, deposit thickness is about the 700-1500 dust, form via implanting one of arsenic, phosphonium ion again after using growth, or, form down via adding one of arsenic, phosphorus environment in silicomethane by growing simultaneously and implanted prosthetics.
11. the method for claim 1, wherein this HSG silicon layer is to use the LPCVD method, and at the about 500-600 of temperature ℃, the about 5-100 of pressure is torr in the least, deposits the thickness of about 300-700 .
12. the method for claim 1, wherein this storage node structure is by the CMP grinding, with Cl
2Be one of isotropism RIE etching of etchant, remove HSG silicon layer not, the 3rd polysilicon layer of not wanting forms.
13. the method for claim 1, wherein this capacitor dielectric is the ONO layer, is equivalent to the silicon oxide layer of the about 40-80 dust of a thickness, is the silicon oxide layer that forms the about 10-20 dust of a thickness by first thermal oxidation; Deposit the silicon nitride layer of the about 10-50 dust of a thickness again; Then this silicon nitride layer of thermal oxidation forms the silicon oxide layer that a upper strata is nitrogenize, and lower floor is the structure of silicon oxide layer.
14. the method for claim 1 wherein forms this top electrode of this stacked capacitor structure with the 4th polysilicon layer, be to utilize the LPCVD method, at the about 500-700 of temperature ℃, deposits the thickness of about 1000-3000 dust.
15. a method of making high density DRAM capacitor arrangement, it forms a dark pocket COB structure in the semiconductor substrate, and this method may further comprise the steps:
One transfer gate transistor was provided on this semiconductor-based end;
Form this polysilicon bit line structure, be overlying on this first insulating barrier, and contact with this first source/drain region with the contact hole hole in this first insulating barrier;
Deposit silicon nitride layer between a ground floor, to cover this polysilicon bit line structure fully;
Deposition one second insulating barrier on silicon nitride layer between this ground floor;
This second insulating barrier of planarization;
Depositing silicon nitride layer between a second layer on this second insulating barrier;
Deposition one the 3rd insulating barrier on silicon nitride layer between this second layer;
Deposition one first polysilicon layer on the 3rd insulating barrier;
Between this first polysilicon layer, the 3rd insulating barrier, this second layer, in silicon nitride layer and this second insulating barrier, terminate in silicon nitride layer upper surface between this ground floor, and the boundary forms one first memory node opening between this polysilicon bit line structure;
In this first memory node opening, form depression at the side that exposes to the open air of the 3rd insulating barrier and this second insulating barrier;
Deposit one the 4th insulating barrier, to fill up the depression in the 3rd insulating barrier and this second insulating barrier;
In this first memory node opening, the 4th insulating barrier of silicon nitride layer and this first insulating barrier between this ground floor of isotropic etching, to form a dark pocket storage node contact hole hole, make the second source/drain region of this transfering transistor when insulating gap wall forms, expose to the open air out, comprise the 4th insulating barrier on the silicon nitride side that covers the polysilicon bit line;
Deposition one second polysilicon layer on this first polysilicon layer surface, and as one man be coated in this dark pocket storage node contacts fenestra hole, make it to contact with this second source/drain region;
Deposition one dome-type grain silicon layer on this second polysilicon layer;
Fill up this dark pocket storage node contacts fenestra hole with the 4th insulating barrier;
Remove this dome-type crystal grain silicon layer, this second polysilicon layer and this first polysilicon layer from the 3rd insulating barrier upper surface;
Remove the 4th insulating barrier from silicon nitride layer upper surface between this dark pocket, storage node contacts fenestra hole and this second layer, to form a storage node structure, comprise this dome-type crystal grain silicon layer and this second polysilicon layer in this dark pocket storage node contacts fenestra hole;
On this storage node structure, form a capacitor dielectric;
Deposition one the 3rd polysilicon layer on this capacitor dielectric; And
Limit the 3rd poly-silicon pattern, to form the top electrode of this dark pocket COB structure.
16. method as claimed in claim 15, wherein this polysilicon bit line structure is at the about 500-700 of temperature ℃, and a polysilicon layer of the about 1000-3000 dust of formed thickness is again via with Cl
2For the RIE etching of etchant is made.
17. method as claimed in claim 15, wherein silicon nitride layer covers this polysilicon bit line structure between this ground floor, and with one of LPCVD, PECVD method, at the about 500-850 of temperature ℃, the about 500-1000 dust of deposit thickness forms.
18. method as claimed in claim 15, wherein this second insulating barrier is to be the formed oxide layer of gas source with TEOS, or is about a bpsg layer of 4000-7000 dust with the thickness that one of LPCVD, PECVD method are deposited.
19. method as claimed in claim 15, wherein silicon nitride layer is with one of PECVD, LPCVD method between this second layer, in the about 500-850 of temperature ℃ formation, and the about 500-1000 dust of deposit thickness.
20. method as claimed in claim 15, wherein the 3rd insulating barrier is to be the formed oxide layer of gas source with TEOS, or is about a bpsg layer of 3000-8000 dust with the thickness that one of LPCVD, PECVD method are deposited.
21. method as claimed in claim 15, wherein first polysilicon layer is to use the LPCVD method, forms the about 500-2000 dust of deposit thickness at the about 500-700 dust of temperature.
22. method as claimed in claim 15, wherein this first memory node opening is obtained through RIE technology by this series thin film layer, uses Cl respectively
2Etchant for silicon nitride layer between this first polysilicon layer and this second layer; And use CHF
3Etchant for the 3rd insulating barrier and this second insulating barrier.
23. method as claimed in claim 15, wherein the 3rd insulating barrier and second insulating barrier expose side to the open air, be positioned at the formed depression of this first memory node opening and be to use a hydrofluoric acid cushioning liquid etching and obtain.
24. method as claimed in claim 15, wherein the 4th insulating barrier is a silicon oxide layer, is the method with one of LPCVD, PECVD, in the about 500-800 of temperature ℃ formation, deposit thickness is about the 500-1000 dust.
25. method as claimed in claim 15, wherein this dark pocket, storage node contact hole hole are by isotropism RIE technology, with CHF
3For the etchant of the 4th insulating barrier and this first insulating barrier, with Cl
2By the erosion agent of silicon nitride layer between this ground floor is formed.
26. method as claimed in claim 15 wherein is positioned at this second insulating barrier and this insulating gap wall that is overlying on the side of this polysilicon bit line structure silicon nitride, is with CHF by RIE technology
3For this second insulating barrier of etchant etching forms.
27. method as claimed in claim 15, wherein this second crystal silicon layer is by the LPCVD method, at the about 500-700 of temperature ℃, deposit thickness is about the 700-1500 dust, form via implanting one of arsenic, phosphonium ion again after using growth, or, form down via adding one of arsenic, phosphorus environment in silicomethane by growing simultaneously and implanted prosthetics.
28. method as claimed in claim 15, wherein this HSG silicon layer is to use the LPCVD method, and at the about 500-600 of temperature ℃, the about 5-100 milli of pressure torr forms down, deposits the thickness of about 300-700 dust.
29. method as claimed in claim 15 is a spin-coating glass or a bpsg layer in order to the 4th insulating barrier that fills up this dark pocket, storage node contacts fenestra hole wherein.
30. method as claimed in claim 15, wherein this storage node structure is by the CMP grinding, with Cl
2Be one of isotropism RIE etching of etchant, remove HSG silicon layer not, the 3rd polysilicon layer of not wanting forms.
31. method as claimed in claim 15, wherein this capacitor dielectric is the ONO layer, is equivalent to the about 40-80 dust of thickness silicon oxide layer, is the silicon oxide layer that forms the about 10-20 dust of a thickness by first thermal oxidation; Deposit the silicon nitride layer of the about 10-50 dust of a thickness again; Then this silicon nitride layer of thermal oxidation forms the silicon oxide layer that a upper strata is nitrogenize, and lower floor is the structure of silicon oxide layer.
32. method as claimed in claim 15, wherein the 3rd polysilicon layer adopts the LPCVD method, in the about 500-700 of temperature ℃ formation, and the about 1000-3000 dust of deposit thickness.
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| CN98109314A CN1127137C (en) | 1998-05-27 | 1998-05-27 | Method for manufacturing capacitor structure of high-density DRAM |
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| CN98109314A CN1127137C (en) | 1998-05-27 | 1998-05-27 | Method for manufacturing capacitor structure of high-density DRAM |
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| CN1127137C CN1127137C (en) | 2003-11-05 |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1319153C (en) * | 2003-07-10 | 2007-05-30 | 南亚科技股份有限公司 | Process for making trench capacitor having geometric shape trench |
| CN1333455C (en) * | 2003-03-14 | 2007-08-22 | 海力士半导体有限公司 | Method for making semiconductor device |
| CN100336170C (en) * | 2004-03-10 | 2007-09-05 | 海力士半导体有限公司 | Method for forming capacitor of semiconductor device |
| CN100416699C (en) * | 2003-09-08 | 2008-09-03 | 三洋电机株式会社 | Semiconductor memory device |
| CN101656254B (en) * | 2008-08-21 | 2012-04-04 | 南亚科技股份有限公司 | Dynamic random access memory structure and manufacturing method thereof |
-
1998
- 1998-05-27 CN CN98109314A patent/CN1127137C/en not_active Expired - Lifetime
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1333455C (en) * | 2003-03-14 | 2007-08-22 | 海力士半导体有限公司 | Method for making semiconductor device |
| CN1319153C (en) * | 2003-07-10 | 2007-05-30 | 南亚科技股份有限公司 | Process for making trench capacitor having geometric shape trench |
| CN100416699C (en) * | 2003-09-08 | 2008-09-03 | 三洋电机株式会社 | Semiconductor memory device |
| CN100336170C (en) * | 2004-03-10 | 2007-09-05 | 海力士半导体有限公司 | Method for forming capacitor of semiconductor device |
| CN101656254B (en) * | 2008-08-21 | 2012-04-04 | 南亚科技股份有限公司 | Dynamic random access memory structure and manufacturing method thereof |
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| Publication number | Publication date |
|---|---|
| CN1127137C (en) | 2003-11-05 |
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