CN110957304A - Capacitor structure and manufacturing method thereof - Google Patents
Capacitor structure and manufacturing method thereof Download PDFInfo
- Publication number
- CN110957304A CN110957304A CN201811132395.5A CN201811132395A CN110957304A CN 110957304 A CN110957304 A CN 110957304A CN 201811132395 A CN201811132395 A CN 201811132395A CN 110957304 A CN110957304 A CN 110957304A
- Authority
- CN
- China
- Prior art keywords
- layer
- etching
- supporting layer
- thickness
- supporting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 title claims abstract description 75
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 238000005530 etching Methods 0.000 claims abstract description 136
- 239000000758 substrate Substances 0.000 claims abstract description 49
- 238000000034 method Methods 0.000 claims abstract description 36
- 239000000463 material Substances 0.000 claims description 28
- -1 boron ions Chemical class 0.000 claims description 12
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 11
- 230000000149 penetrating effect Effects 0.000 claims description 8
- 229910052796 boron Inorganic materials 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 6
- 229910052698 phosphorus Inorganic materials 0.000 claims description 5
- 239000011574 phosphorus Substances 0.000 claims description 5
- 238000000151 deposition Methods 0.000 description 13
- 230000008021 deposition Effects 0.000 description 12
- 229920002120 photoresistant polymer Polymers 0.000 description 12
- 229910052581 Si3N4 Inorganic materials 0.000 description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 10
- 230000007547 defect Effects 0.000 description 5
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000005336 cracking Methods 0.000 description 4
- 239000005360 phosphosilicate glass Substances 0.000 description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 229910052799 carbon Inorganic materials 0.000 description 3
- 230000000052 comparative effect Effects 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 102100022717 Atypical chemokine receptor 1 Human genes 0.000 description 2
- 101000678879 Homo sapiens Atypical chemokine receptor 1 Proteins 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 230000003667 anti-reflective effect Effects 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003575 carbonaceous material Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229940104869 fluorosilicate Drugs 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/642—Capacitive arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
Abstract
The invention provides a capacitor structure and a manufacturing method thereof, wherein the method comprises the following steps: forming an etching stop layer, a lower sacrificial layer, a middle supporting layer, a top sacrificial layer, a first supporting layer and a stress relieving layer on a bottom substrate, wherein the bottom substrate is provided with a contact hole; etching the stress relieving layer based on the first pattern mask to form a stress relieving part; forming a second supporting layer on the first supporting layer and the stress relieving part, wherein the stress relieving part is coated by the first supporting layer and the second supporting layer to form a top supporting layer; etching the top supporting layer based on the second pattern mask to form a primary capacitor hole; forming a lower electrode layer on at least an inner wall surface of the primary capacitor hole; etching at least the top support layer based on the third pattern mask to form an etch opening; the top sacrificial layer, a portion of the middle support layer, and the lower sacrificial layer are removed based on the etch opening to form a termination capacitance hole. The invention solves the problem of low stability of the capacitance supporting layer in the existing capacitor structure.
Description
Technical Field
The present invention relates to the field of semiconductor integrated circuits, and more particularly, to a capacitor structure and a method for fabricating the same.
Background
Dynamic Random Access Memory (DRAM) is a semiconductor Memory device commonly used in computers, and is composed of many repetitive Memory cells. Each memory cell typically includes a capacitor and a transistor; the grid electrode of the transistor is connected with the word line, the drain electrode of the transistor is connected with the bit line, and the source electrode of the transistor is connected with the capacitor; the voltage signal on the word line can control the transistor to be turned on or off, so that data information stored in the capacitor can be read through the bit line, or the data information can be written into the capacitor through the bit line for storage.
As the device size of Dynamic Random Access Memory (DRAM) is getting smaller, the aspect ratio of the capacitor is getting larger, so that the etching becomes more difficult and the requirement for the capacitor support layer is getting higher; therefore, how to provide a capacitor structure with a more stable capacitance support layer is a problem that needs to be solved urgently in the existing Dynamic Random Access Memory (DRAM).
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention is directed to a capacitor structure and a method for manufacturing the same, which is used to solve the problem of low stability of the capacitance support layer in the prior capacitor structure.
To achieve the above and other related objects, the present invention provides a method of manufacturing a capacitor structure, the method comprising:
s1: providing a bottom substrate, and sequentially forming an etching stop layer, a lower sacrificial layer, a middle supporting layer, a top sacrificial layer, a first supporting layer and a stress relieving layer on the upper surface of the bottom substrate from bottom to top; wherein the bottom substrate has a contact hole penetrating its upper and lower surfaces;
s2: forming a first pattern mask on the upper surface of the stress relieving layer, and etching the stress relieving layer based on the first pattern mask to form a stress relieving part exposing the first support layer;
s3: forming a second supporting layer on the upper surface of the first supporting layer and the surface of the stress relieving part, wherein the stress relieving part is wrapped in the first supporting layer and the second supporting layer to form a top supporting layer;
s4: forming a second pattern mask on the upper surface of the top supporting layer, and etching the top supporting layer based on the second pattern mask to form a primary capacitor hole exposing the contact hole;
s5: forming a lower electrode layer at least on an inner wall surface of the primary capacitor hole;
s6: forming a third pattern mask on the upper surface of the structure obtained in the step S5, and etching at least the top supporting layer based on the third pattern mask to form an etching opening exposing the top sacrificial layer; and
s7: based on the etching opening, the top sacrificial layer, a part of the middle support layer and the lower sacrificial layer are removed in sequence to form a terminal capacitance hole.
Optionally, the manufacturing method further includes S8: a dielectric layer and an upper electrode layer are formed in this order from the outside to the inside at least on the surface of the terminal capacitance hole.
Optionally, the specific method for forming the etch stop layer in S1 includes: forming a first etch stop layer prior to an upper surface of the base substrate; and then thinning the first etching stop layer, and forming a second etching stop layer on the thinned upper surface of the first etching stop layer so as to form an etching stop layer on the upper surface of the bottom substrate.
Optionally, the thickness of the etching stop layer is between 10nm and 80 nm; the thickness of the first etching stop layer is between 10nm and 80nm, the thinning thickness is between 5nm and 30nm, and the thickness of the second etching stop layer is between 5nm and 30 nm.
Optionally, the material of the stress relief layer is selected from borophosphosilicate glass, wherein the weight percentage of boron ions is between 2 wt% and 4 wt%, and the weight percentage of phosphorus ions is between 2 wt% and 5 wt%.
Optionally, the thickness of the top support layer is between 150nm and 300 nm; the thickness of the first supporting layer is between 50nm and 150nm, the thickness of the stress relieving part is between 20nm and 100nm, and the thickness of the second supporting layer is between 50nm and 150 nm.
Optionally, a specific method for forming the etching opening in S6 includes:
s61: forming a third pattern mask on the upper surface of the structure obtained in S5, wherein the third pattern mask has a plurality of dry etching patterns, and a gap is formed between adjacent etching patterns, the gap is located above the top supporting layer to be etched, and the width of the gap is the same as the width of the top supporting layer to be etched; and
s62: and at least etching the top supporting layer to be etched based on the third pattern mask so as to form an etching opening exposing the top sacrificial layer.
The present invention also provides a capacitor structure comprising:
a bottom substrate having a contact hole penetrating upper and lower surfaces thereof;
the lower electrode layer is positioned on the bottom substrate, wherein the cross section of the lower electrode layer is U-shaped;
the etching stop layer is positioned on the upper surface of the bottom substrate and is connected with the bottom side wall of the lower electrode layer;
the middle supporting layer is positioned above the etching stopping layer and is connected to the middle side wall of the lower electrode layer;
the top supporting layer is positioned above the middle supporting layer and is connected to the top side wall of the lower electrode layer;
the top supporting layer sequentially comprises a first supporting layer, a stress relieving part and a second supporting layer from bottom to top, and the stress relieving part is coated in the first supporting layer and the second supporting layer.
Optionally, the capacitor structure further comprises: a dielectric layer and an upper electrode layer; the dielectric layer is at least formed on the surface of the lower electrode layer, and the upper electrode layer is formed on the surface of the dielectric layer.
Optionally, the etch stop layer comprises: the etching device comprises a first etching stop layer formed on the upper surface of the bottom substrate, and a second etching stop layer formed on the upper surface of the first etching stop layer.
Optionally, the thickness of the etching stop layer is between 10nm and 80 nm; wherein the thickness of the first etching stop layer is between 5nm and 50nm, and the thickness of the second etching stop layer is between 5nm and 30 nm.
Optionally, the tops of the two sidewalls of the U-shaped lower electrode layer are flush with the top of the top support layer.
Optionally, the material of the stress relief portion is selected from borophosphosilicate glass, wherein the weight percentage of boron ions is between 2 wt% and 4 wt%, and the weight percentage of phosphorus ions is between 2 wt% and 5 wt%.
Optionally, the thickness of the top support layer is between 150nm and 300 nm; the thickness of the first supporting layer is between 50nm and 150nm, the thickness of the stress relieving part is between 20nm and 100nm, and the thickness of the second supporting layer is between 50nm and 150 nm.
As described above, the capacitor structure and the manufacturing method thereof of the present invention have the following advantages:
according to the invention, the top supporting layer is designed into a multi-layer structure of the first supporting layer/the stress relieving part/the second supporting layer, and the stress relieving part is coated in the first supporting layer and the second supporting layer, so that the thickness of the top supporting layer is increased, and simultaneously, the internal stress of the first supporting layer and the internal stress of the second supporting layer are relieved by the stress relieving part, and the internal stress is reduced by about 50-80%, so that the supporting stability of the top supporting layer is increased, and the risk of cracking of the top supporting layer is reduced.
When the etching stop layer is formed, a first etching stop layer is firstly deposited, then the first etching stop layer is thinned, and then a second etching stop layer is formed on the first etching stop layer, so that the defects existing when the etching stop layer is formed by one-time deposition are overcome; the invention solves the problems of uneven surface and poor compactness of the etching stop layer caused by different materials with the bottom substrate when the etching stop layer is formed on the bottom substrate by primary deposition through thinning treatment and secondary deposition, thereby optimizing the surface compactness of the etching stop layer to reduce the risk of short circuit between the bottoms of the capacitors.
When the etching opening is formed, the etching is only carried out on the top supporting layer to be etched and/or the lower electrode layer on the upper surface of the top supporting layer to be etched, and the lower electrode layers on the two sides of the top supporting layer to be etched are reserved, so that the surface area of the capacitor hole is increased, and the capacity of the capacitor is improved generally.
Drawings
Fig. 1 to 17 are schematic structural diagrams illustrating steps in the manufacturing method of the capacitor structure according to the present embodiment, wherein fig. 16 is a top view of fig. 15.
Fig. 18 to 24 are schematic structural views showing steps in a method of manufacturing a capacitor structure according to a comparative example, in which fig. 24 is a top view of fig. 23.
Description of the element reference numerals
101 bottom substrate 102 contact hole
103 first etch stop layer 104 second etch stop layer
105 etch stop layer 106 first sacrificial layer
107 second sacrificial layer 108 lower sacrificial layer
109 middle support layer 110 top sacrificial layer
111 first support layer 112 stress relief layer
113 first pattern mask 114 stress relief
115 second support layer 116 top support layer
117 second pattern mask 118 primary capacitive aperture
119 lower electrode layer 120 mask sacrificial layer
121 third pattern mask 122 gap
123 top support layer 124 to be etched etch opening
125 terminal capacitance hole 126 dielectric layer
127 upper electrode layer
201 bottom substrate 202 contact hole
203 etch stop layer 204 first sacrificial layer
205 second sacrificial layer 206 lower sacrificial layer
207 middle support layer 208 top sacrificial layer
209 top support layer 210 first pattern mask
211 lower electrode layer of primary capacitor hole 212
213 second pattern mask 214 etch openings
215 final capacitor aperture
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 24. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
Examples
As shown in fig. 1 to 17, the present embodiment provides a method for manufacturing a capacitor structure, the method including:
s1: providing a bottom substrate 101, and sequentially forming an etching stop layer 105, a lower sacrificial layer 108, a middle support layer 109, a top sacrificial layer 110, a first support layer 111 and a stress relief layer 112 on the upper surface of the bottom substrate 101 from bottom to top; wherein the base substrate 101 has a contact hole 102 penetrating its upper and lower surfaces;
s2: forming a first pattern mask 113 on the upper surface of the stress relieving layer 112, and etching the stress relieving layer 112 based on the first pattern mask 113 to form a stress relieving portion 114 exposing the first supporting layer 111;
s3: forming a second support layer 115 on the upper surface of the first support layer 111 and the surface of the stress relief portion 114, wherein the stress relief portion 114 is covered by the first support layer 111 and the second support layer 115 to form a top support layer 116;
s4: forming a second pattern mask 117 on the upper surface of the top support layer 116, and etching the top support layer 116 based on the second pattern mask 117 to form a primary capacitor hole 118 exposing the contact hole 102;
s5: forming a lower electrode layer 119 at least on an inner wall surface of the primary capacitor hole 118;
s6: forming a third pattern mask 121 on the upper surface of the structure obtained in S5, and etching at least the top supporting layer 116 based on the third pattern mask 121 to form an etching opening 124 exposing the top sacrificial layer 110; and
s7: based on the etch opening 124, the top sacrificial layer 110, a portion of the middle support layer 109, and the lower sacrificial layer 108 are sequentially removed to form a terminal capacitance hole 125.
Referring to fig. 1 to 17, a method for manufacturing the capacitor structure according to the present embodiment will be described in detail.
As shown in fig. 1 to 4, providing a bottom substrate 101, and sequentially forming an etch stop layer 105, a lower sacrificial layer 108, a middle support layer 109, a top sacrificial layer 110, a first support layer 111, and a stress relief layer 112 on an upper surface of the bottom substrate 101 from bottom to top; wherein the base substrate 101 has a contact hole 102 penetrating its upper and lower surfaces. It should be noted that the contact hole 102 is used to connect the capacitor of the present embodiment with the lower circuit, and in the dram, the contact hole 102 is used to connect the capacitor with the source or drain of the lower transistor.
As an example, as shown in fig. 1 to 3, a specific method for forming the etch stop layer 105 includes: forming a first etch stop layer 103 prior to an upper surface of the base substrate 101; then, the first etching stop layer 103 is thinned, and a second etching stop layer 104 is formed on the thinned upper surface of the first etching stop layer 103, so as to form an etching stop layer 105 on the upper surface of the bottom substrate 101. Specifically, a chemical vapor deposition process is used to form the first etching stop layer 103 and the second etching stop layer 104, and an etching process is used to reduce the thickness of the first etching stop layer 103, wherein the first etching stop layer 103 and the second etching stop layer 104 are made of the same material and are both selected from silicon nitride; the etch stop layer 105 has a thickness between 10nm and 80nm, inclusive, the first etch stop layer 103 has a thickness between 10nm and 80nm, inclusive, a reduced thickness (i.e., etch removal thickness) between 5nm and 30nm, inclusive, and the second etch stop layer has a thickness between 5nm and 30nm, inclusive. In this embodiment, when forming the etching stop layer 105, the first etching stop layer 103 is deposited first, and then the second etching stop layer 104 is formed on the first etching stop layer 103 after the first etching stop layer 103 is thinned, so as to compensate for the defect existing when the etching stop layer is formed by one deposition; that is, the embodiment solves the problems of unevenness and poor compactness of the surface of the etching stop layer due to different materials from the bottom substrate when the etching stop layer is formed by the primary deposition on the bottom substrate through the thinning treatment and the secondary deposition, so as to optimize the surface compactness of the etching stop layer 105 in the embodiment, and reduce the risk of short circuit between the bottoms of the capacitors.
As an example, as shown in fig. 4, a specific method of forming the lower sacrificial layer 108 includes: a first sacrificial layer 106 is formed on the upper surface of the etch stop layer 105, and then a second sacrificial layer 107 is formed on the upper surface of the first sacrificial layer 106, so as to form a lower sacrificial layer 108 on the upper surface of the etch stop layer 105. Specifically, the material of the first sacrificial layer 106 is selected from one of the group consisting of phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), and fluorosilicate glass (FSG), and the first sacrificial layer 106 is made of a softer material to facilitate subsequent bottom etching; wherein the thickness of the first sacrificial layer 106 is between 100nm and 600nm (inclusive). The second sacrificial layer 107 is made of one selected from the group consisting of Tetraethylorthosilicate (TEOS), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), and fluorosilicone glass (FSG); wherein the thickness of the second sacrificial layer 107 is between 300nm and 1000nm (inclusive).
As an example, the middle support layer 109 is formed by a chemical vapor deposition process, and the material of the middle support layer 109 is selected from silicon nitride, and the thickness of the middle support layer is between 10nm and 80nm (inclusive).
As an example, the material of the top sacrificial layer 110 is selected from silicon dioxide (SiO)2) And Tetraethylorthosilicate (TEOS), the thickness of the top sacrificial layer 110 being between 300nm and 800nm, inclusive.
As an example, the first support layer 111 is formed by a chemical vapor deposition process, and the material of the first support layer 111 is selected from silicon nitride, and the thickness of the first support layer is between 50nm and 150nm (inclusive).
As an example, the material of the stress relieving layer 112 is selected from borophosphosilicate glass (BPSG), wherein the weight percentage of boron ions is between 2 wt% and 4 wt% (inclusive), and the weight percentage of phosphorous ions is between 2 wt% and 5 wt% (inclusive), so that the stress relieving layer 112 of the present embodiment has better fluidity, thereby being beneficial to relieve the internal stress of the subsequently formed top supporting layer; wherein the stress relief layer 112 has a thickness between 20nm and 100nm, inclusive.
As shown in fig. 5 and 6, a first pattern mask 113 is formed on the upper surface of the stress relieving layer 112, and the stress relieving layer 112 is etched based on the first pattern mask 113 to form a stress relieving portion 114 exposing the first supporting layer 111. It is noted that after the stress relieving portion 114 is formed, the first pattern mask 113 needs to be removed.
As an example, a specific method of forming the first pattern mask 113 includes: forming a first hard mask layer and a second hard mask layer in sequence from bottom to top on the upper surface of the stress relieving layer 112; forming a patterned photoresist layer on the upper surface of the second hard mask layer, and etching the second hard mask layer and the first hard mask layer based on the patterned photoresist layer so as to transfer the pattern in the patterned photoresist layer to the first hard mask layer; and finally, removing the patterned photoresist layer and the second hard mask layer. Specifically, the first hard mask layer is made of one selected from the group consisting of silicon carbide, organic anti-reflective material (BARC) and spin on carbon (spin on carbon), and has a thickness of 50nm to 200nm (inclusive); the second hard mask layer is made of an inorganic anti-reflection material (DARC) and has a thickness of 20-150 nm (inclusive).
As shown in fig. 7, a second supporting layer 115 is formed on the upper surface of the first supporting layer 111 and the surface of the stress relief portion 114, wherein the stress relief portion 114 is enclosed by the first supporting layer 111 and the second supporting layer 115 to form a top supporting layer 116. In this embodiment, the top support layer 116 is designed to be a multilayer structure of the first support layer 111/the stress relieving portion 114/the second support layer 115, and the stress relieving portion 114 is wrapped by the first support layer 111 and the second support layer 115, so as to achieve the purpose of increasing the thickness of the top support layer 116, and at the same time, the stress relieving portion 114 is used to relieve the internal stress of the first support layer 111 and the second support layer 115, so that the absolute value of the stress of the top support layer 116 in this embodiment is reduced to 30MPa to 60MPa (inclusive), thereby increasing the support stability of the top support layer and reducing the risk of cracking of the top support layer.
As an example, the second support layer 115 is formed by a chemical vapor deposition process, and the material of the second support layer 115 is selected from silicon nitride, and the thickness of the second support layer is between 50nm and 150nm (inclusive).
Illustratively, the top support layer 116 has a thickness between 150nm and 300 nm; the thickness of the first support layer 111 is between 50nm and 150nm, the thickness of the stress relief part 114 is between 20nm and 100nm, and the thickness of the second support layer 115 is between 50nm and 150 nm.
As shown in fig. 8 and 9, a second pattern mask 117 is formed on the upper surface of the top support layer 116, and the top support layer 116 is etched based on the second pattern mask 117 to form a preliminary capacitor hole 118 exposing the contact hole 102. It is noted that after the formation of the primary capacitor hole 118, the second pattern mask 117 needs to be removed.
As an example, a specific method of forming the second pattern mask 117 includes: forming a hard mask layer on the top surface of the top support layer 116; forming a patterned photoresist layer on the upper surface of the hard mask layer, and etching the hard mask layer based on the patterned photoresist layer so as to transfer the pattern in the patterned photoresist layer into the hard mask layer; and finally, removing the patterned photoresist layer. Specifically, the hard mask layer is made of polysilicon, and the thickness of the hard mask layer is between 500nm and 1000nm (inclusive).
As shown in fig. 10, a lower electrode layer 119 is formed at least on the inner wall surface of the primary capacitor hole 118; alternatively, in the present embodiment, the lower electrode layer 119 is formed on the surface of the top support layer 116 and the inner wall surface of the primary capacitor hole 118.
As an example, the lower electrode layer 119 is formed by an atomic layer deposition process, wherein the material of the lower electrode layer 119 is selected from titanium nitride (TiN), and the thickness thereof is between 10nm and 80nm (inclusive).
As shown in fig. 11 and 12, a third pattern mask 121 is formed on the upper surface of the structure obtained in the previous step, and at least the top supporting layer 116 is etched based on the third pattern mask 121 to form an etching opening 124 exposing the top sacrificial layer 110. It is noted that after the etching opening 124 is formed, the third pattern mask 121 needs to be removed.
As an example, a specific method for forming the etching opening 124 includes: forming a third pattern mask 121 on the upper surface of the structure obtained in the previous step, wherein the third pattern mask 121 has a plurality of dry etching patterns, and a gap 122 is formed between adjacent dry etching patterns, the gap 122 is located above the top supporting layer 123 to be etched, and the width of the gap 122 is the same as the width of the top supporting layer 123 to be etched; and etching at least the top supporting layer 123 to be etched based on the third pattern mask 121 to form an etching opening 124 exposing the top sacrificial layer 110. In this embodiment, by designing the gap 122 between adjacent etching patterns to be the same as the width of the top supporting layer 123 to be etched, only the top supporting layer 123 to be etched and/or the lower electrode layer 119 above the top supporting layer are etched in the etching process, so as to retain the lower electrode layers 119 on both sides of the top supporting layer 123 to be etched, thereby increasing the surface area of the capacitor hole and generally increasing the capacity of the capacitor.
Specifically, as shown in fig. 11 and 12, since the lower electrode layer 119 is formed on the surface of the top support layer 116 and the inner wall surface of the primary capacitor hole 118, the specific method for forming the etching opening 124 of the present embodiment includes: forming a mask sacrificial layer 120 on the upper surface of the structure obtained in the previous step; forming a third pattern mask 121 on the upper surface of the mask sacrificial layer 120, wherein the third pattern mask 121 has a plurality of dry etching patterns, and a gap 122 is formed between adjacent dry etching patterns, the gap 122 is located above the top support layer 123 to be etched, and the width of the gap 122 is the same as the width of the top support layer 123 to be etched (both W1); finally, the lower electrode layer 119 on the upper surface of the top support layer 123 to be etched and the top support layer 123 to be etched are etched based on the third pattern mask 121 to form an etching opening 124 exposing the top sacrificial layer 110.
The material of the mask sacrificial layer 120 is selected from silicon nitride, and the thickness thereof is between 50nm and 150nm (inclusive).
The specific method for forming the third pattern mask 121 includes: forming a first hard mask layer, a second hard mask layer and a third hard mask layer in sequence from bottom to top on the upper surface of the mask sacrificial layer 120; forming a patterned photoresist layer on the upper surface of the third hard mask layer, and etching the first hard mask layer, the second hard mask layer and the third hard mask layer based on the patterned photoresist layer so as to transfer the pattern in the patterned photoresist layer to the first hard mask layer; and finally, removing the patterned photoresist layer, the third hard mask layer and the second hard mask layer. Wherein the first hard mask layer is made of silicon oxide and has a thickness of 50 nm-200 nm (inclusive); the second hard mask layer is made of one of the group consisting of silicon carbide, organic anti-reflection material (BARC) and spin on carbon material (spin on carbon), and has a thickness of 50-200 nm (inclusive); the third hard mask layer is made of an inorganic anti-reflection material (DARC) and has a thickness of 20-150 nm (inclusive).
As shown in fig. 13 to 16, the top sacrificial layer 110, a portion of the middle support layer 109 and the lower sacrificial layer 108 are sequentially removed based on the etch opening 124 to form a terminal capacitance hole 125.
In this embodiment, as shown in fig. 13 to 16, a specific method for forming the termination capacitor hole 125 includes: removing the top sacrificial layer 110 based on the etch opening 124; then removing part of the middle support layer 109 (i.e. removing the middle support layer 109 under the top support layer 123 to be etched), and simultaneously removing the mask sacrificial layer 120 and the lower electrode layer 119 above the top of the top support layer 116, so that the top of the lower electrode layer 119 is flush with the top of the top support layer 116; finally, the lower sacrificial layer 108 is removed.
As shown in fig. 17, the manufacturing method further includes: at least a dielectric layer 126 and an upper electrode layer 127 are formed in this order from the outside to the inside of the surface of the terminal capacitance hole 125.
As shown in fig. 15 and 16, the present embodiment also provides a capacitor structure manufactured by the capacitor manufacturing method described above, the capacitor structure including:
a base substrate 101, the base substrate 101 having a contact hole 102 penetrating upper and lower surfaces thereof;
a lower electrode layer 119 located on the bottom substrate 101, wherein the cross section of the lower electrode layer 109 is U-shaped;
an etch stop layer 105 on the top surface of the bottom substrate 101 and connected to the bottom sidewall of the bottom electrode layer 109;
a middle support layer 109 positioned above the etch stop layer 105 while being connected to a middle sidewall of the lower electrode layer 119;
a top support layer 116 positioned above the middle support layer 109 while being connected to a top sidewall of the lower electrode layer 119;
the top support layer 116 includes, from bottom to top, a first support layer 111, a stress relieving portion 114, and a second support layer 115 in sequence, and the stress relieving portion 114 is covered by the first support layer 111 and the second support layer 115.
As an example, the etch stop layer 105 includes: a first etch stop layer 103 formed on the top surface of the base substrate 101, and a second etch stop layer 104 formed on the top surface of the first etch stop layer 103. Specifically, the material of the first etch stop layer 103 is the same as the material of the second etch stop layer 104, and both are silicon nitride; the thickness of the etching stop layer 105 is between 10nm and 80nm, wherein the thickness of the first etching stop layer is between 5nm and 50nm, and the thickness of the second etching stop layer is between 5nm and 30 nm.
By way of example, the lower electrode layer 119 is made of titanium nitride (TiN) and has a thickness of 10nm to 80nm (inclusive). Specifically, the tops of two side walls of the U-shaped lower electrode layer are flush with the top of the top supporting layer, so that the surface area of a capacitor hole is increased, and the capacity of the capacitor is improved as a whole.
By way of example, the material of the middle support layer 109 is selected from silicon nitride, and the thickness thereof is between 10nm and 80nm (inclusive).
By way of example, the top support layer 116 has a thickness between 150nm and 300nm (inclusive), wherein the first support layer 111 has a thickness between 50nm and 150nm (inclusive), wherein the stress relief portion 114 has a thickness between 20nm and 100nm (inclusive), and wherein the second support layer 115 has a thickness between 50nm and 150nm (inclusive). Specifically, the material of the first support layer 111 is the same as that of the second support layer 115, and is selected from silicon nitride; the material of the stress relieving portion 114 is selected from borophosphosilicate glass, wherein the weight percentage of boron ions is between 2 wt% and 4 wt%, and the weight percentage of phosphorus ions is between 2 wt% and 5 wt%, so as to have better fluidity, which is beneficial to relieving the internal stress of the first supporting layer 111 and the second supporting layer 115.
As an example, as shown in fig. 17, the capacitor structure further includes: a dielectric layer 126 and an upper electrode layer 127; the dielectric layer 126 is formed on at least the surface of the lower electrode layer 119, and the upper electrode layer 127 is formed on the surface of the dielectric layer 126.
Comparative example
As shown in fig. 18 to 24, the comparative example provides a manufacturing method of a conventional capacitor structure, the manufacturing method including:
s1: providing a bottom substrate 201, and sequentially forming an etching stop layer 203, a lower sacrificial layer 206, a middle support layer 207, a top sacrificial layer 208 and a top support layer 209 on the upper surface of the bottom substrate 201 from bottom to top; wherein the base substrate 201 has a contact hole 202 penetrating its upper and lower surfaces;
s2: forming a first pattern mask 210 on the upper surface of the top supporting layer 209, etching the top supporting layer 209 based on the first pattern mask 210 to form a primary capacitor hole 211 exposing the contact hole 202, and then removing the first pattern mask 210;
s3: forming a lower electrode layer 212 on the inner wall surface of the primary capacitor hole 211;
s4: forming a second pattern mask 213 on the upper surface of the structure obtained in S3, etching the lower electrode layer 212 and the top supporting layer 209 based on the second pattern mask 213 to form an etching opening 214 exposing the top sacrificial layer 208, and removing the second pattern mask 213; and
s5: based on the etch opening 214, the top sacrificial layer 208, a portion of the middle support layer 207, and the lower sacrificial layer 206 are sequentially removed to form a terminal capacitance hole 215.
The specific method for forming the etch stop layer 203 is as follows: a silicon nitride layer is directly formed on the upper surface of the base substrate 201 by a single deposition process to serve as the etch stop layer 203. When the etching stop layer 203 is directly formed on the upper surface of the base substrate 201, the material of the base substrate 201 is different from the material of the etching stop layer 203, which may cause unevenness on the surface of the etching stop layer 203 to be formed, thereby causing poor surface denseness.
The specific method for forming the top support layer 209 is: depositing a silicon nitride layer with the thickness of 50 nm-150 nm on the upper surface of the top sacrificial layer 208 by adopting a plasma enhanced chemical vapor deposition process to serve as the top supporting layer 209; when plasma enhanced chemical vapor deposition is carried out, the pressure of a reaction chamber is 25 Pa-30 Pa, the radio frequency power is 50W-200W, and monosilane (SiH) is introduced4) The gas flow rate of (1) is 10sccm to 45sccm, and ammonia gas (NH)3) The gas flow rate of (2) is 20sccm to 40 sccm. The absolute value of the stress of the top supporting layer 209 formed by the existing plasma enhanced chemical vapor deposition process is 80 Mpa-450 Mpa, and even if the internal stress of the top supporting layer is reduced by changing the gas flow, the pressure intensity and the radio frequency power, the obtained minimum absolute value of the stress is 80 Mpa-150 Mpa.
When the etching opening 214 is formed, the lower electrode layer 212 on both sides of the top supporting layer 209 is directly removed, so that one side of each of the two side walls of the finally formed U-shaped lower electrode layer is high and the other side of the U-shaped lower electrode layer is low, thereby resulting in a small surface area of the conventional capacitor hole and a low capacitance of the capacitor.
As can be seen from this, as shown in fig. 15, 16, 23 and 24, compared with the conventional method for manufacturing the capacitor structure, in the present invention, when the etching stop layer is formed, a first etching stop layer is deposited first, and then a second etching stop layer is formed on the first etching stop layer after the first etching stop layer is thinned, so as to compensate for the defect existing when the etching stop layer is formed by one deposition; the invention solves the problems of uneven surface and poor compactness of the etching stop layer caused by different materials with the bottom substrate when the etching stop layer is formed on the bottom substrate by primary deposition through thinning treatment and secondary deposition, thereby optimizing the surface compactness of the etching stop layer to reduce the risk of short circuit between the bottoms of the capacitors. The top support layer is designed into a multi-layer structure of a first support layer/a stress relieving part/a second support layer, and the stress relieving part is coated in the first support layer and the second support layer, so that the thickness of the top support layer is increased, and simultaneously, the stress relieving part is utilized to relieve the internal stress of the first support layer and the second support layer, so that the internal stress is reduced by about 50-80%, the support stability of the top support layer is increased, and the risk of cracking of the top support layer is reduced. In the invention, when the etching opening is formed, only the top supporting layer to be etched and/or the lower electrode layer on the upper surface of the top supporting layer to be etched are etched, and the lower electrode layers on two sides of the top supporting layer to be etched are reserved, so that the surface area of the capacitor hole is increased, and the capacity of the capacitor is improved generally.
In summary, the capacitor structure and the manufacturing method thereof of the present invention have the following advantages: according to the invention, the top supporting layer is designed into a multi-layer structure of the first supporting layer/the stress relieving part/the second supporting layer, and the stress relieving part is coated in the first supporting layer and the second supporting layer, so that the thickness of the top supporting layer is increased, and simultaneously, the internal stress of the first supporting layer and the internal stress of the second supporting layer are relieved by the stress relieving part, and the internal stress is reduced by about 50-80%, so that the supporting stability of the top supporting layer is increased, and the risk of cracking of the top supporting layer is reduced. When the etching stop layer is formed, a first etching stop layer is firstly deposited, then the first etching stop layer is thinned, and then a second etching stop layer is formed on the first etching stop layer, so that the defects existing when the etching stop layer is formed by one-time deposition are overcome; the invention solves the problems of uneven surface and poor compactness of the etching stop layer caused by different materials with the bottom substrate when the etching stop layer is formed on the bottom substrate by primary deposition through thinning treatment and secondary deposition, thereby optimizing the surface compactness of the etching stop layer to reduce the risk of short circuit between the bottoms of the capacitors. When the etching opening is formed, the etching is only carried out on the top supporting layer to be etched and/or the lower electrode layer on the upper surface of the top supporting layer to be etched, and the lower electrode layers on the two sides of the top supporting layer to be etched are reserved, so that the surface area of the capacitor hole is increased, and the capacity of the capacitor is improved generally. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (14)
1. A method of fabricating a capacitor structure, the method comprising:
s1: providing a bottom substrate, and sequentially forming an etching stop layer, a lower sacrificial layer, a middle supporting layer, a top sacrificial layer, a first supporting layer and a stress relieving layer on the upper surface of the bottom substrate from bottom to top; wherein the bottom substrate has a contact hole penetrating its upper and lower surfaces;
s2: forming a first pattern mask on the upper surface of the stress relieving layer, and etching the stress relieving layer based on the first pattern mask to form a stress relieving part exposing the first support layer;
s3: forming a second supporting layer on the upper surface of the first supporting layer and the surface of the stress relieving part, wherein the stress relieving part is wrapped in the first supporting layer and the second supporting layer to form a top supporting layer;
s4: forming a second pattern mask on the upper surface of the top supporting layer, and etching the top supporting layer based on the second pattern mask to form a primary capacitor hole exposing the contact hole;
s5: forming a lower electrode layer at least on an inner wall surface of the primary capacitor hole;
s6: forming a third pattern mask on the upper surface of the structure obtained in the step S5, and etching at least the top supporting layer based on the third pattern mask to form an etching opening exposing the top sacrificial layer; and
s7: based on the etching opening, the top sacrificial layer, a part of the middle support layer and the lower sacrificial layer are removed in sequence to form a terminal capacitance hole.
2. The method of manufacturing a capacitor structure of claim 1, further comprising S8: a dielectric layer and an upper electrode layer are formed in this order from the outside to the inside at least on the surface of the terminal capacitance hole.
3. The method for manufacturing the capacitor structure according to claim 1, wherein the specific method for forming the etching stop layer in S1 comprises: forming a first etch stop layer prior to an upper surface of the base substrate; and then thinning the first etching stop layer, and forming a second etching stop layer on the thinned upper surface of the first etching stop layer so as to form an etching stop layer on the upper surface of the bottom substrate.
4. The method of claim 3, wherein the etch stop layer has a thickness of between 10nm and 80 nm; the thickness of the first etching stop layer is between 10nm and 80nm, the thinning thickness is between 5nm and 30nm, and the thickness of the second etching stop layer is between 5nm and 30 nm.
5. The method of claim 1, wherein the stress relief layer is made of borophosphosilicate glass, wherein the weight percentage of boron ions is between 2 wt% and 4 wt%, and the weight percentage of phosphorus ions is between 2 wt% and 5 wt%.
6. The method of claim 1, wherein the top support layer has a thickness of between 150nm and 300 nm; the thickness of the first supporting layer is between 50nm and 150nm, the thickness of the stress relieving part is between 20nm and 100nm, and the thickness of the second supporting layer is between 50nm and 150 nm.
7. The method of claim 1, wherein the specific method of forming the etching opening in S6 comprises:
s61: forming a third pattern mask on the upper surface of the structure obtained in S5, wherein the third pattern mask has a plurality of dry etching patterns, and a gap is formed between adjacent etching patterns, the gap is located above the top supporting layer to be etched, and the width of the gap is the same as the width of the top supporting layer to be etched; and
s62: and at least etching the top supporting layer to be etched based on the third pattern mask so as to form an etching opening exposing the top sacrificial layer.
8. A capacitor structure, comprising:
a bottom substrate having a contact hole penetrating upper and lower surfaces thereof;
the lower electrode layer is positioned on the bottom substrate, wherein the cross section of the lower electrode layer is U-shaped;
the etching stop layer is positioned on the upper surface of the bottom substrate and is connected with the bottom side wall of the lower electrode layer;
the middle supporting layer is positioned above the etching stopping layer and is connected to the middle side wall of the lower electrode layer;
the top supporting layer is positioned above the middle supporting layer and is connected to the top side wall of the lower electrode layer;
the top supporting layer sequentially comprises a first supporting layer, a stress relieving part and a second supporting layer from bottom to top, and the stress relieving part is coated in the first supporting layer and the second supporting layer.
9. The capacitor structure of claim 8, further comprising: a dielectric layer and an upper electrode layer; the dielectric layer is at least formed on the surface of the lower electrode layer, and the upper electrode layer is formed on the surface of the dielectric layer.
10. The capacitor structure of claim 8, wherein the etch stop layer comprises: the etching device comprises a first etching stop layer formed on the upper surface of the bottom substrate, and a second etching stop layer formed on the upper surface of the first etching stop layer.
11. The capacitor structure of claim 10, wherein the etch stop layer has a thickness of between 10nm and 80 nm; wherein the thickness of the first etching stop layer is between 5nm and 50nm, and the thickness of the second etching stop layer is between 5nm and 30 nm.
12. The capacitor structure of claim 8, wherein the tops of both sidewalls of the U-shaped lower electrode layer are flush with the top of the top support layer.
13. The capacitor structure of claim 8, wherein the stress relief portion is made of a material selected from the group consisting of borophosphosilicate glass, wherein the weight percentage of boron ions is between 2 wt% and 4 wt%, and the weight percentage of phosphorus ions is between 2 wt% and 5 wt%.
14. The capacitor structure of claim 8, wherein the thickness of the top support layer is between 150nm and 300 nm; the thickness of the first supporting layer is between 50nm and 150nm, the thickness of the stress relieving part is between 20nm and 100nm, and the thickness of the second supporting layer is between 50nm and 150 nm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811132395.5A CN110957304A (en) | 2018-09-27 | 2018-09-27 | Capacitor structure and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811132395.5A CN110957304A (en) | 2018-09-27 | 2018-09-27 | Capacitor structure and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110957304A true CN110957304A (en) | 2020-04-03 |
Family
ID=69967907
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811132395.5A Pending CN110957304A (en) | 2018-09-27 | 2018-09-27 | Capacitor structure and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110957304A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111896291A (en) * | 2020-08-10 | 2020-11-06 | 长江存储科技有限责任公司 | Sample preparation method and device |
| CN113161483A (en) * | 2021-04-07 | 2021-07-23 | 长鑫存储技术有限公司 | Method for manufacturing semiconductor device and semiconductor device |
| WO2021238618A1 (en) * | 2020-05-26 | 2021-12-02 | 长鑫存储技术有限公司 | Method for forming capacitor hole |
| CN114171461A (en) * | 2020-09-10 | 2022-03-11 | 长鑫存储技术有限公司 | Capacitor structure preparation method and capacitor |
| WO2022183642A1 (en) * | 2021-03-05 | 2022-09-09 | 长鑫存储技术有限公司 | Semiconductor structure and forming method therefor |
| US11784216B2 (en) | 2020-09-10 | 2023-10-10 | Changxin Memory Technologies, Inc. | Manufacturing method of capacitive structure, and capacitor |
| US11869932B2 (en) | 2020-09-10 | 2024-01-09 | Changxin Memory Technologies, Inc. | Manufacturing method of capacitive structure, and capacitor |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060189064A1 (en) * | 2005-02-02 | 2006-08-24 | Samsung Electronics Co., Ltd. | Method of manufacturing capacitor of semiconductor device |
| US20090243037A1 (en) * | 2008-04-01 | 2009-10-01 | Sung Min Park | Semiconductor device having capacitors fixed to support patterns and method for manufacturing the same |
| KR20100078971A (en) * | 2008-12-30 | 2010-07-08 | 주식회사 하이닉스반도체 | Semiconductor device and method for manufacturing of the same |
| JP2013247138A (en) * | 2012-05-23 | 2013-12-09 | Ps4 Luxco S A R L | Semiconductor device |
| US20170025416A1 (en) * | 2015-07-22 | 2017-01-26 | Samsung Electronics Co., Ltd. | Capacitor structures and methods of forming the same, and semiconductor devices including the same |
| CN108550569A (en) * | 2018-06-07 | 2018-09-18 | 睿力集成电路有限公司 | Capacitive means of semiconductor integrated circuit and preparation method thereof |
| CN208738232U (en) * | 2018-09-27 | 2019-04-12 | 长鑫存储技术有限公司 | A kind of capacitor arrangement |
-
2018
- 2018-09-27 CN CN201811132395.5A patent/CN110957304A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060189064A1 (en) * | 2005-02-02 | 2006-08-24 | Samsung Electronics Co., Ltd. | Method of manufacturing capacitor of semiconductor device |
| US20090243037A1 (en) * | 2008-04-01 | 2009-10-01 | Sung Min Park | Semiconductor device having capacitors fixed to support patterns and method for manufacturing the same |
| KR20100078971A (en) * | 2008-12-30 | 2010-07-08 | 주식회사 하이닉스반도체 | Semiconductor device and method for manufacturing of the same |
| JP2013247138A (en) * | 2012-05-23 | 2013-12-09 | Ps4 Luxco S A R L | Semiconductor device |
| US20170025416A1 (en) * | 2015-07-22 | 2017-01-26 | Samsung Electronics Co., Ltd. | Capacitor structures and methods of forming the same, and semiconductor devices including the same |
| CN108550569A (en) * | 2018-06-07 | 2018-09-18 | 睿力集成电路有限公司 | Capacitive means of semiconductor integrated circuit and preparation method thereof |
| CN208738232U (en) * | 2018-09-27 | 2019-04-12 | 长鑫存储技术有限公司 | A kind of capacitor arrangement |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021238618A1 (en) * | 2020-05-26 | 2021-12-02 | 长鑫存储技术有限公司 | Method for forming capacitor hole |
| US11889677B2 (en) | 2020-05-26 | 2024-01-30 | Changxin Memory Technologies, Inc. | Method for forming capacitor holes |
| CN111896291A (en) * | 2020-08-10 | 2020-11-06 | 长江存储科技有限责任公司 | Sample preparation method and device |
| CN114171461A (en) * | 2020-09-10 | 2022-03-11 | 长鑫存储技术有限公司 | Capacitor structure preparation method and capacitor |
| WO2022052589A1 (en) * | 2020-09-10 | 2022-03-17 | 长鑫存储技术有限公司 | Method for manufacturing capacitor structure and capacitor |
| CN114171461B (en) * | 2020-09-10 | 2022-10-28 | 长鑫存储技术有限公司 | Capacitor structure preparation method and capacitor |
| US11784216B2 (en) | 2020-09-10 | 2023-10-10 | Changxin Memory Technologies, Inc. | Manufacturing method of capacitive structure, and capacitor |
| US11869932B2 (en) | 2020-09-10 | 2024-01-09 | Changxin Memory Technologies, Inc. | Manufacturing method of capacitive structure, and capacitor |
| WO2022183642A1 (en) * | 2021-03-05 | 2022-09-09 | 长鑫存储技术有限公司 | Semiconductor structure and forming method therefor |
| CN113161483A (en) * | 2021-04-07 | 2021-07-23 | 长鑫存储技术有限公司 | Method for manufacturing semiconductor device and semiconductor device |
| CN113161483B (en) * | 2021-04-07 | 2022-06-10 | 长鑫存储技术有限公司 | Method for manufacturing semiconductor device and semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110957304A (en) | Capacitor structure and manufacturing method thereof | |
| US7825451B2 (en) | Array of capacitors with electrically insulative rings | |
| CN108550569B (en) | Capacitor device of semiconductor integrated circuit and manufacturing method thereof | |
| US7105884B2 (en) | Memory circuitry with plurality of capacitors received within an insulative layer well | |
| US8470668B2 (en) | Method for forming pillar type capacitor of semiconductor device | |
| US5668038A (en) | One step smooth cylinder surface formation process in stacked cylindrical DRAM products | |
| US20120132968A1 (en) | Semiconductor device and method for manufacturing the same | |
| US20060199332A1 (en) | Method of forming storage node of capacitor in semiconductor memory, and structure therefor | |
| JP2000216356A (en) | Semiconductor device and its manufacture | |
| CN208738232U (en) | A kind of capacitor arrangement | |
| US20110306197A1 (en) | Methods of Manufacturing Semiconductor Devices | |
| US8828864B2 (en) | Semiconductor device and method for manufacturing the same | |
| US20100155802A1 (en) | Semiconductor device and method of forming semiconductor device | |
| TWI396261B (en) | Low parasitic capacitance bit line process for stack dram | |
| US6413832B1 (en) | Method for forming inner-cylindrical capacitor without top electrode mask | |
| US8129251B2 (en) | Metal-insulator-metal-structured capacitor formed with polysilicon | |
| US5346846A (en) | Method of manufacturing a highly integrated semiconductor device | |
| US6043131A (en) | Method for making a flower shaped DRAM capacitor | |
| US20090124079A1 (en) | Method for fabricating a conductive plug | |
| KR100762869B1 (en) | A method for fabricating capacitor | |
| US6706587B1 (en) | Method for forming buried plates | |
| JP4392977B2 (en) | Manufacturing method of semiconductor device | |
| TWI389261B (en) | Buried wordline dram with stacked capacitor structures and fabrication methods for stacked capacitor structures | |
| US20120100713A1 (en) | Method for manufacturing semiconductor device | |
| KR100710199B1 (en) | Capacitor and method for fabricating the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |