CN115172256A - STI etching method for forming positive deviation CD value - Google Patents

STI etching method for forming positive deviation CD value Download PDF

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Publication number
CN115172256A
CN115172256A CN202210760422.3A CN202210760422A CN115172256A CN 115172256 A CN115172256 A CN 115172256A CN 202210760422 A CN202210760422 A CN 202210760422A CN 115172256 A CN115172256 A CN 115172256A
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layer
darc
sti
forming
etching method
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张振兴
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H01L21/0276—Photolithographic processes using an anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

The invention discloses an STI (shallow trench isolation) etching method for forming a positive deviation CD (compact disc), wherein a DARC (DARC) layer and a pattern conducting layer are coated on the surface of a semiconductor substrate, the DARC layer covers the pattern conducting layer, and the pattern conducting layer covers the surface of the semiconductor substrate; during photoetching, photoresist opens an etching window, the DARC layer is etched, an inclined appearance is etched on the DARC layer, and the inclined appearance is conducted on the pattern conducting layer when the pattern conducting layer is further etched; the STI trenches remain linear with the hard mask.

Description

STI etching method for forming positive deviation CD value
Technical Field
The invention relates to the field of semiconductor device or integrated circuit manufacturing, in particular to a method for forming a positive deviation CD value by STI (shallow trench isolation) etching.
Background
STI, shallow trench isolation, or shallow trench isolation, STI for short. Generally used in the process below 0.25um, an isolation structure commonly used in the manufacture of semiconductor devices is formed by depositing, patterning and etching silicon using a silicon nitride mask to form a trench, and filling the trench with a deposited oxide for isolation from the silicon.
STI techniques have become increasingly popular for forming isolation structures between active regions. STI structures are typically formed by first depositing a silicon nitride layer over a semiconductor substrate and then patterning the silicon nitride layer to form a hard mask. The substrate is then etched to form steep trenches between adjacent devices. Finally, filling oxide into the trench to form an element isolation structure. Although the STI process has better isolation characteristics than the LOCOS process, a large number of etching defects may be generated due to plasma damage, and a steep trench having a sharp Corner may also cause Corner Parasitic leakage (Corner Parasitic leakage), thereby degrading the isolation characteristics of the STI.
The primary technique for selective oxidation for sub-0.25 um processes is Shallow Trench Isolation (STI). The primary insulating material in STI technology is deposited oxide. The selective oxidation is accomplished using a mask, typically silicon nitride. The mask is deposited and patterned. The trench is formed after etching the silicon. At the region exposed by the mask pattern, thermal oxidation
Figure BDA0003720870880000011
The silicon can be etched to form the trench after the thick oxide layer. This thermally grown oxide is silicon surface passivation and can isolate the deposited oxide of the shallow trench fill from the silicon. The method can also be used as an effective barrier layer to avoid the generation of side wall leakage current in the device.
In the STI etching process, an etching deviation ET Bias = AEI (trench size formed by etching) CD — ADI (trench size formed at the time of exposure) CD. CD is the minimum size for lithography.
Due to the loss of photoresist during etching, and the adjustment of the photoresist, the adjustment of the hard mask causes the CD value to shrink, the ET bias is usually negative, i.e., the AEI CD becomes smaller.
Therefore, a new method is required to form STI of the forward ET Bias.
Disclosure of Invention
The invention aims to solve the technical problem of providing an STI for forming a forward ET Bias, wherein the size of a groove formed by etching is closer to a design value.
In order to solve the above problems, the STI etching method for forming a positive deviation CD value according to the present invention includes:
providing a semiconductor substrate, coating a DARC layer and a pattern conducting layer on the surface of the semiconductor substrate, wherein the DARC layer covers the pattern conducting layer, and the pattern conducting layer covers the surface of the semiconductor substrate;
during photoetching, photoresist opens an etching window, the DARC layer is etched, an inclined appearance is etched on the DARC layer, and the inclined appearance is conducted on the pattern conducting layer when the pattern conducting layer is further etched;
the STI trenches remain linear with the hard mask.
In a further improvement, the patterned conductive layer is an APF layer; the DARC layer and the pattern conducting layer complete the transfer of the pattern of the photoresist.
In a further improvement, the APF layer is a hard mask layer containing amorphous carbon; the etching selectivity ratio is larger than 6, the DARC as a barrier layer has the topography damaged in the subsequent etching process, and the APF can maintain the topography due to the characteristic of high selectivity ratio.
In a further improvement, the patterned conductive layer is deposited by a CVD process.
In a further improvement, the material of the patterned conducting layer is required to be capable of being easily removed by plasma etching.
In a further improvement, the etching selectivity of the patterned conductive layer is more than 10 for silicon oxide; for polysilicon, more than 6 is required.
In a further improvement, the patterned conductive layer has a low reflectivity upon exposure to light, wherein the reflectivity is less than 0.5%.
The STI etching method of the positive deviation CD value takes DARC and APF as pattern conducting materials, wherein the DARC is firstly etched with an inclined appearance, and the inclined appearance is conducted on the APF when the APF is further etched. The DARC can be used as a barrier layer, the morphology of the DARC can be damaged in the subsequent etching process, and the APF can maintain the morphology due to the characteristic of high selectivity ratio.
Drawings
FIG. 1 is a schematic of the process of the present invention.
Description of the reference numerals
1 is a substrate, 2 is a patterned conductive layer, 3 is a DARC layer, and 4 is a photoresist.
Detailed Description
The following detailed description of the present invention is given with reference to the accompanying drawings, and the technical solution of the present invention is clearly and completely described, but the present invention is not limited to the following embodiments. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are each provided with a non-precision ratio for the purpose of convenience and clarity in assisting in describing the embodiments of the present invention. All other embodiments obtained by a person skilled in the art without making any inventive step are within the scope of protection of the present invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity, and the same reference numerals denote the same elements throughout. It will be understood that when an element or layer is referred to as being "on," "over," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
In order to make the technical means, the creation characteristics, the achievement purposes and the effects of the invention easy to understand, the invention is further explained below by combining the specific drawings.
The STI etching method for forming the positive deviation CD value has the advantages that the size of the groove is closer to a set value, and the deviation between photoetching and etching is reduced.
The STI etching method for forming the positive deviation CD value, disclosed by the invention, is as shown in figure 1, a semiconductor substrate is provided, a DARC layer and a pattern conducting layer are coated on the surface of the semiconductor substrate, and the DARC layer is a common material, namely a dielectric antireflection layer. In a normal photolithography process, the photoresist is coated on the wafer before the photoresist is coated formally, and then the photoresist is spun on the DARC layer, because the surface of the wafer is polished to a mirror surface, the DARC layer can prevent or reduce the reflection of extreme ultraviolet light by the wafer during exposure.
The DARC layer is covered above the pattern conducting layer, and the pattern conducting layer covers the surface of the semiconductor substrate; the pattern conductive layer is an APF (Advanced Patterning Film) layer, which is a carbon-containing hard mask layer, mainly amorphous carbon. Having high selectivity, e.g. selectivity greater than 6, with only O 2 It can be etched effectively. The APF layer is deposited by a CVD process and has the property of being easily removed from the wafer, for example by plasma bombardment, to completely remove the APF layer.
The etching selection ratio of the APF layer is more than 10:1; for polysilicon, more than 6. The DARC as a barrier layer can be damaged in its topography during subsequent etching, while the APF can maintain the topography due to the high selectivity characteristic, as shown in fig. 1. The APF layer has a low reflectivity when exposed, and the reflectivity is lower than 0.5%.
During photoetching, the photoresist opens an etching window to etch the DARC layer, an inclined appearance is etched on the DARC, and the inclined appearance is conducted on the pattern conducting layer when the pattern conducting layer is further etched; the DARC layer together with the pattern conductive layer completes transfer of a pattern of photoresist.
The STI trench formed by etching keeps consistent with the linearity of the hard mask, referring to fig. 1 again, an APF layer is etched to form an angle 1, the inclined focus of the trench side wall formed by etching in the substrate material is an angle 2, the angle 2 is not more than the angle 1, and the etching deviation value is positive.
The STI etching method of the positive deviation CD value takes DARC and APF as pattern conducting materials, wherein the DARC is firstly etched with an inclined appearance, and the inclined appearance is conducted on the APF when the APF is further etched. In the subsequent etching process, the DARC is used as a barrier layer, the appearance of the DARC can be damaged, the APF can maintain the appearance due to the characteristic of high selection ratio, and the linearity of the STI trench and the hard mask is kept consistent.
The above are merely preferred embodiments of the present invention, and are not intended to limit the present invention. Various modifications and alterations to this invention will become apparent to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (9)

1. An STI etching method for forming positive deviation CD value is characterized in that:
providing a semiconductor substrate, coating a DARC layer and a pattern conducting layer on the surface of the semiconductor substrate, wherein the DARC layer covers the pattern conducting layer, and the pattern conducting layer covers the surface of the semiconductor substrate;
during photoetching, the photoresist opens an etching window to etch the DARC layer, an inclined appearance is etched on the DARC, and the inclined appearance is conducted on the pattern conducting layer when the pattern conducting layer is further etched;
the STI trenches remain linear with the hard mask.
2. The STI etching method for forming a positive deviation CD value according to claim 1, characterized in that: the pattern conducting layer is an APF layer; the DARC layer and the pattern conducting layer complete the transfer of the pattern of the photoresist.
3. The STI etching method for forming a positive deviation CD value according to claim 2, characterized in that: the APF layer is a hard mask layer containing amorphous carbon; the etching selectivity ratio is larger than 6, the DARC as a barrier layer has the topography damaged in the subsequent etching process, and the APF can maintain the topography due to the characteristic of high selectivity ratio.
4. The STI etching method for forming a positive deviation CD value according to claim 1, characterized in that: the patterned conductive layer is deposited by a CVD process.
5. The STI etching method for forming a positive deviation CD value according to claim 1, wherein: the material of the pattern conducting layer is required to be capable of being easily removed by plasma etching.
6. The STI etching method for forming a positive deviation CD value according to claim 1, characterized in that: the etching selection ratio of the pattern conducting layer is more than 10 for silicon oxide; for polysilicon, more than 6 is required.
7. The STI etching method for forming a positive deviation CD value according to claim 1, wherein: the patterned conductive layer has a low reflectivity upon exposure, which is less than 0.5%.
8. The STI etching method for forming a positive deviation CD value according to claim 1, wherein: and after the groove is etched, filling a medium in the groove.
9. The STI etching method for forming a positive deviation CD value according to claim 8, wherein: the filled dielectric comprises silicon oxide or silicon nitride.
CN202210760422.3A 2022-06-29 2022-06-29 STI etching method for forming positive deviation CD value Pending CN115172256A (en)

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