KR100868925B1 - Method for forming the Isolation Layer of Semiconductor Device - Google Patents

Method for forming the Isolation Layer of Semiconductor Device Download PDF

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KR100868925B1
KR100868925B1 KR1020020038402A KR20020038402A KR100868925B1 KR 100868925 B1 KR100868925 B1 KR 100868925B1 KR 1020020038402 A KR1020020038402 A KR 1020020038402A KR 20020038402 A KR20020038402 A KR 20020038402A KR 100868925 B1 KR100868925 B1 KR 100868925B1
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film
trench
silicon substrate
forming
oxide film
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KR20040003650A (en
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원용식
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매그나칩 반도체 유한회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
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Abstract

본 발명은 반도체 소자의 제조 공정 중 소자분리막 형성 공정에 있어서, 특히 큰 트렌치 피치에서 발생하는 갭필산화막의 디슁 현상을 개선하기 위한 것으로 실리콘기판을 식각하여 트렌치의 일부를 형성한 후, 결과물 상에 질화막과 반사방지막 및 실리콘기판의 선택적 옥시데이션 공정을 진행하여 소자분리막 형성을 위한 갭필산화막 증착 시, 큰 트렌치 피치에서의 낮은 갭필산화막 단차를 보상함으로써, 후속 CMP공정에서 갭필 산화막의 디슁 현상을 방지하여 평탄화 효율을 높일 수 있고, 평탄화에 따른 게이트 포토 공정 마진을 확보하도록 하여 반도체 소자의 고집적화를 가능하게 하는 기술이다.
The present invention is to improve the leveling of the gap fill oxide film, which occurs in a large trench pitch, in the process of forming a device isolation film during the manufacturing process of a semiconductor device, and after etching a silicon substrate to form a portion of the trench, the nitride film is formed on the resultant. Selective oxidation process of the anti-reflection film and the silicon substrate to compensate for the gap gap of the gapfill oxide film at the large trench pitch when depositing the gapfill oxide film to form the device isolation film, thereby preventing flattening of the gapfill oxide film in the subsequent CMP process It is a technology that can increase the efficiency and ensure a gate photo process margin due to planarization to enable high integration of semiconductor devices.

트렌치, 소자분리막, 평탄화, 디슁Trench, Device Isolation, Planarization, Dimming

Description

반도체 소자의 소자분리막 형성방법 {Method for forming the Isolation Layer of Semiconductor Device} Method for forming the isolation layer of semiconductor device             

도 1a 내지 도 1c는 종래의 반도체소자의 소자분리막 제조방법을 설명하기 위해 순차적으로 나타낸 단면도이다.1A through 1C are cross-sectional views sequentially illustrating a method of manufacturing a device isolation film of a conventional semiconductor device.

도 2a 내지 도 2g는 본 발명의 실시예에 따른 반도체소자의 소자분리막 제조방법을 설명하기 위해 순차적으로 나타낸 단면도이다.
2A through 2G are cross-sectional views sequentially illustrating a method of manufacturing a device isolation film of a semiconductor device according to an embodiment of the present invention.

* 도면의 주요부분에 대한 부호의 설명 *   Explanation of symbols on the main parts of the drawings

100 : 실리콘기판 105 : 패드산화막100: silicon substrate 105: pad oxide film

110 : 질화막 120 : 쉘로우 트렌치110: nitride film 120: shallow trench

130 : 희생질화막 140 : 반사방지막130: sacrificial nitride film 140: antireflection film

150 : 산화막 160 : 딥 트렌치150: oxide film 160: deep trench

170 : 갭필산화막 180 : 소자분리막
170: gap fill oxide film 180: device isolation film

본 발명은 반도체 소자의 소자분리막 형성방법에 관한 것으로서, 보다 상세하게는 소자분리막 형성을 위한 갭필 산화막 증착 시, 큰 트렌치 피치에서의 낮은 갭필산화막 단차를 보상하여 큰 트렌치 피치에서 발생하는 갭필 산화막의 디슁 현상을 개선하도록 하여 갭필산화막의 평탄화 효율을 높일 수 있는 반도체 소자의 소자분리막 형성방법에 관한 것이다.The present invention relates to a method for forming a device isolation film of a semiconductor device, and more particularly, to depositing a gap fill oxide film generated at a large trench pitch by compensating for a low gap fill oxide step at a large trench pitch when a gap fill oxide film is deposited for forming a device isolation film. The present invention relates to a method of forming a device isolation film of a semiconductor device capable of improving the phenomenon and increasing the planarization efficiency of the gapfill oxide film.

일반적으로, 실리콘기판 상에 트렌지스터와 커패시터등을 형성하기 위하여 실리콘기판에는 전기적으로 통전이 가능한 활성영역과 전기적으로 통전되는 것을 방지하고 소자를 서로 분리하도록 하는 소자분리영역을 형성하게 된다. In general, in order to form transistors, capacitors, and the like on a silicon substrate, an silicon isolation region is formed in the silicon substrate to prevent electrically conduction from an electrically conductable active region and to separate devices from each other.

이와 같이, 실리콘기판에 일정한 깊이를 갖는 트렌치를 형성하고서 이 트렌치에 산화막을 증착시킨 후 화학기계적연마공정으로 이 산화막의 불필요한 부분을 식각하므로 소자분리영역을 반도체 기판에 형성시키는 STI(Shallow Trench Isolation)공정이 최근에 많이 이용되고 있다.As such, a trench having a predetermined depth is formed on the silicon substrate, and an oxide film is deposited on the trench, and a chemical mechanical polishing process etches an unnecessary portion of the oxide film, thereby forming an isolation region on the semiconductor substrate. The process has been used a lot lately.

도 1a 내지 도 1c는 종래의 반도체소자의 소자분리막 형성방법을 설명하기 위해 순차적으로 나타낸 단면도이다.1A to 1C are cross-sectional views sequentially illustrating a method of forming a device isolation film of a conventional semiconductor device.

종래의 반도체장치에서 트렌치를 형성하여 소자분리막을 형성하는 상태를 개략적으로 설명하면, 도 1a에 도시된 바와 같이, 실리콘 기판(1) 상에 소정의 두께를 갖고서 절연을 하도록 패드산화막(2)을 적층하고, 그 위에 상,하층간에 보호 역할을 하는 질화막(3)을 적층하며, 이 질화막(3)은 트렌치 식각공정 시, 식각 마스크로 사용할 수 있으며, 혹은 후속 공정인 화학기계적연마 공정에서 식각정지막으 로 사용된다.In the semiconductor device of the related art, a state in which a device isolation film is formed by forming a trench is schematically described. As shown in FIG. 1A, the pad oxide film 2 is insulated from the silicon substrate 1 to have a predetermined thickness. The nitride layer 3, which acts as a protective layer between the upper and lower layers, is laminated thereon, and the nitride layer 3 may be used as an etching mask during the trench etching process, or may be etch stop in the subsequent chemical mechanical polishing process. Used as a membrane.

이어서, 상기 질화막(3) 상부에 감광막을 도포하고, 노광 및 현상 공정을 진행하여 감광막 패턴(미도시함)을 형성한 후, 이를 마스크로 질화막(3)과 패드산화막(2)을 순차적으로 식각하여 실리콘기판(1)의 소자분리영역을 노출시킨다.Subsequently, a photoresist film is coated on the nitride film 3, an exposure and development process is performed to form a photoresist pattern (not shown), and the nitride film 3 and the pad oxide film 2 are sequentially etched using the mask. As a result, the device isolation region of the silicon substrate 1 is exposed.

그 후, 상기 감광막 패턴(미도시함)을 제거한 후, 질화막(3)을 식각마스크로 건식식각공정을 진행하여 실리콘기판(1) 내에 다양한 피치(pitch)의 트렌치(4)를 형성한다.Thereafter, after removing the photoresist pattern (not shown), a dry etching process is performed using the nitride film 3 as an etching mask to form trenches 4 of various pitches in the silicon substrate 1.

그리고, 도 1b에 도시된 바와 같이, 상기 결과물 상에 화학기상증착법으로 갭필산화막(5)을 증착하며, 이때, 실리콘기판(1) 내에 형성된 다양한 피치(pitch)의 트렌치로 인하여 증착된 갭필산화막(5)에 단차가 형성된다.As shown in FIG. 1B, the gap fill oxide film 5 is deposited on the resultant by chemical vapor deposition. In this case, the gap fill oxide film deposited due to various pitch trenches formed in the silicon substrate 1 may be deposited. A step is formed in 5).

이어서, 도 1c에 도시된 바와 같이, 상기 결과물을 화학기계적연마 공정에 의해 질화막(3) 상부까지 연마하여 결과물을 평탄화시켜 소자분리막(6)을 형성한다.Subsequently, as shown in FIG. 1C, the resultant is polished to the upper portion of the nitride film 3 by a chemical mechanical polishing process to planarize the resultant to form the device isolation film 6.

그러나, 상기와 같은 종래의 소자분리막 형성방법은 다양한 피치의 트렌치로 인하여 트렌치의 피치가 클 경우에 갭필산화막을 증착 단계에서 발생된 단차에 의해 화학기계적 연마 공정 시, 소자분리막(6)이 움푹 패이는 "A"와 같은 디슁(dishing)현상 발생되어 반도체소자의 특성 및 신뢰성이 저하되는 문제점이 있었다.
However, in the conventional method of forming a device isolation film as described above, when the pitch of the trench is large due to various pitch trenches, the device isolation film 6 is dent in the chemical mechanical polishing process due to the step generated in the deposition step of the gapfill oxide film. This causes a dishing phenomenon such as "A" to deteriorate the characteristics and reliability of the semiconductor device.

본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로서, 본 발명의 목적은 소자분리막 형성을 위한 갭필 산화막 증착 시, 큰 트렌치 피치에서의 낮은 갭필산화막 단차를 보상함으로써, 후속 CMP공정에서 갭필 산화막의 디슁 현상을 방지하도록 하는 것이다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to compensate for a gap gap in a large trench pitch during deposition of a gap fill oxide for forming a device isolation film, thereby to compensate for the gap fill oxide in a subsequent CMP process. It is to prevent the phenomenon.

상기 목적을 달성하기 위하여, 본 발명은 실리콘기판 상에 소자분리영역을 노출시키는 패드산화막 및 질화막을 형성하는 단계, 질화막을 마스크로 실리콘기판에 제1 트렌치와, 상기 제1 트렌치보다 넓은 폭의 제2 트렌치를 형성하는 단계, 제1 및 제2 트렌치가 형성된 결과물 상에 희생질화막과 반사방지막을 순차적으로 형성하는 단계, 반사방지막에 에치백 공정을 진행하여 제2 트렌치의 중심부의 희생질화막을 노출시키는 단계, 노출된 희생질화막을 식각하여 실리콘기판을 노출시키는 단계, 반사방지막을 제거하고 제2 트렌치 바닥의 노출된 실리콘기판에 산화막을 형성하는 단계, 희생질화막을 제거하는 단계, 질화막과 산화막을 식각마스크로 하여, 제1 및 제2 트렌치 바닥의 노출된 실리콘기판을 식각하여 제3 트렌치를 형성하는 단계, 및 제1 내지 제3 트렌치를 절연막으로 매립하여 소자분리막을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체소자의 소자분리막 형성방법을 제공한다.In order to achieve the above object, the present invention is to form a pad oxide film and a nitride film to expose the device isolation region on the silicon substrate, the first trench in the silicon substrate with a nitride film as a mask, a wider width than the first trench Forming a trench, sequentially forming a sacrificial nitride film and an antireflective film on the resultant formed first and second trenches, and performing an etch back process on the antireflective film to expose the sacrificial nitride film in the center of the second trench. Exposing the silicon substrate by etching the exposed sacrificial nitride film, removing the antireflection film and forming an oxide film on the exposed silicon substrate at the bottom of the second trench, removing the sacrificial nitride film, etching the nitride film and the oxide film Etching the exposed silicon substrates of the first and second trench bottoms to form third trenches, and the first to Filling the trench with an insulating film 3 to provide a device isolation method for forming a semiconductor device comprising the steps of forming the device isolation film.

상기 제2 트렌치 바닥의 노출된 실리콘기판에 산화막을 형성하는 단계에서, 상기 질화막을 마스크로 하여 개방된 부위만 산화시켜 산화막을 형성할 수 있다.
상기 반사방지막 에치백 공정 시, N2 가스와 O2가스를 사용하여 식각할 수 있다.
상기 희생질화막을 식각하여 상기 실리콘기판을 노출시키는 단계에서, CHF3, CF4, Ar 가스를 사용하여 상기 희생질화막을 식각할 수 있다.
상기 희생질화막을 제거하는 단계에서, 상기 희생질화막을 습식식각 방법으로 제거할 수 있다.In the forming of the oxide film on the exposed silicon substrate on the bottom of the second trench, the oxide film may be formed by oxidizing only the open portion using the nitride film as a mask.
In the anti-reflection film etchback process, it may be etched using N 2 gas and O 2 gas.
In the etching of the sacrificial nitride layer to expose the silicon substrate, the sacrificial nitride layer may be etched using CHF 3 , CF 4 , or Ar gas.
In the removing of the sacrificial nitride layer, the sacrificial nitride layer may be removed by a wet etching method.

삭제delete

이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2g는 본 발명의 실시예에 따른 반도체소자의 소자분리막 제조방법을 설명하기 위해 순차적으로 나타낸 단면도이다.2A through 2G are cross-sectional views sequentially illustrating a method of manufacturing a device isolation film of a semiconductor device according to an embodiment of the present invention.

도 2a에 도시된 바와 같이, 실리콘기판(100) 상에 패드산화막(105)과 질화막(110)을 순차적으로 증착한 후 질화막(110) 상에 트렌치를 형성하기 위한 감광막 패턴(미도시함)을 형성한다.As shown in FIG. 2A, after the pad oxide film 105 and the nitride film 110 are sequentially deposited on the silicon substrate 100, a photoresist pattern (not shown) for forming a trench on the nitride film 110 is formed. Form.

이때, 상기 질화막(110)은 1000 ~ 1500Å 두께로 증착하여 후속 트렌치 식각공정 시, 식각 마스크로 사용할 수 있으며, 혹은 후속 공정인 화학기계적연마 공정에서 식각정지막으로 사용된다.In this case, the nitride layer 110 is deposited to a thickness of 1000 ~ 1500Å can be used as an etching mask during the subsequent trench etching process, or used as an etch stop layer in the chemical mechanical polishing process, which is a subsequent process.

그리고, 상기 감광막 패턴(미도시함)을 마스크로 이용하여 실리콘기판(100)의 필드영역(A)이 노출되도록 질화막(110)과 패드산화막(105)을 순차적으로 식각하고, 감광막 패턴(미도시함)을 제거하여 필드영역(A)의 실리콘기판(100)을 노출시킨다.The nitride film 110 and the pad oxide film 105 are sequentially etched to expose the field region A of the silicon substrate 100 using the photoresist pattern (not shown) as a mask, and the photoresist pattern (not shown) is exposed. The silicon substrate 100 in the field region A is exposed.

이어서, 상기 질화막(110)을 마스크로 건식식각하여 실리콘기판(100) 내에 쉘로우 트렌치(120)를 형성한다.Subsequently, the nitride film 110 is dry-etched using a mask to form a shallow trench 120 in the silicon substrate 100.

도 2b에 도시된 바와 같이, 상기 결과물 상에 희생질화막(130)과 반사방지막(140)을 순차적으로 형성한다. 이때, 피치가 큰 쉘로우 트렌치(도 2a의 124)에 형성된 반사방지막(140)은 피치가 작은 쉘로우 트렌치(도 2a의 122)에 형성된 반사방지막(140)보다 얇게 형성된다.As shown in FIG. 2B, the sacrificial nitride film 130 and the anti-reflection film 140 are sequentially formed on the resultant. In this case, the anti-reflection film 140 formed in the shallow pitch trench 124 of FIG. 2A is thinner than the anti-reflection film 140 formed in the shallow trench trench 122 of FIG. 2A.

그리고, 도 2c에 도시된 바와 같이, 상기 결과물에 건식식각공정으로 N2 가스와 O2가스를 사용하여 하부 희생질화막(130)을 보호하면서 반사방지막(140)을 식각하는 에치백 공정을 진행한다.As shown in FIG. 2C, an etchback process of etching the anti-reflection film 140 while protecting the lower sacrificial nitride film 130 using N 2 gas and O 2 gas is performed on the resultant by a dry etching process. .

이때, 상기 피치가 작은 쉘로우 트렌치에 형성된 반사방지막(140)은 트렌치(120) 내에 잔류하며, 피치가 큰 쉘로우 트렌치의 중심부에 형성된 반사방지막(140)은 두께가 얇아서 제거된다.At this time, the anti-reflection film 140 formed in the shallow trench trench is left in the trench 120, and the anti-reflection film 140 formed in the center of the shallow pitch trench is thin and removed.

이어서, 상기 반사방지막(140)이 제거된 피치가 큰 쉘로우 트렌치(124)에 CHF3, CF4, Ar 가스를 식각가스로 사용하여 노출된 희생질화막(130)을 제거하여 하부 실리콘기판(100)을 노출시킨다.Subsequently, the sacrificial nitride film 130 is removed using CHF 3 , CF 4 , and Ar gas as an etching gas in the shallow pitch trench 124 from which the anti-reflection film 140 is removed, thereby removing the lower silicon substrate 100. Expose

그리고, 도 2d에 도시된 바와 같이, 상기 결과물 상의 반사방지막(미도시함)을 제거하고 O2 분위기에서 노출된 실리콘기판(100)에 옥시데이션 공정을 진행하여 산화막(150)을 형성한 후, 인산을 이용한 습식식각에 의해 피치가 작은 쉘로우 트렌치 내부와 피치가 큰 쉘로우 트렌치의 내부 측벽의 희생질화막(미도시함)을 제거한다.As shown in FIG. 2D, after removing the anti-reflection film (not shown) on the resultant and performing an oxidization process on the silicon substrate 100 exposed in an O 2 atmosphere, an oxide film 150 is formed. Wet etching using phosphoric acid removes the sacrificial nitride film (not shown) inside the shallow pitch trench and the inner sidewalls of the shallow pitch trench.

그 후, 도 2e에 도시된 바와 같이, 상기 질화막(110)과 산화막(150)을 식각마스크로 실리콘기판(100)을 식각하여 딥 트렌치(160)를 형성한다. 피치가 큰 쉘로우 트렌치의 중심부에는 산화막(150)이 형성되어 있어 식각되지 않는다.Thereafter, as illustrated in FIG. 2E, the deep trench 160 is formed by etching the silicon substrate 100 using the nitride film 110 and the oxide film 150 as an etch mask. The oxide film 150 is formed in the center of the shallow trench, and the pitch is not etched.

도 2f에 도시된 바와 같이, 상기 결과물 상에 화학기상증착법에 의해 갭필 산화막(170)을 증착하여 딥 트렌치를 매립함으로써, "B"와 같이 피치가 큰 딥 트렌치의 중앙과 에지부분의 단차를 보상하여 준다.As shown in FIG. 2F, the gap fill oxide film 170 is deposited on the resultant by filling the gap fill oxide to fill the deep trench, thereby compensating for the difference between the center and the edge portion of the deep trench, such as “B”. Give it.

그리고, 도 2g에 도시된 바와 같이, 상기 결과물을 화학기계적연마(CMP) 공정에 의해 질화막(110) 상부까지 평탄화하여 소자분리막(180)을 형성한다.
As shown in FIG. 2G, the resultant is planarized to the upper portion of the nitride film 110 by a chemical mechanical polishing (CMP) process to form the device isolation film 180.

따라서, 본 발명에 따른 반도체 소자의 소자분리막 형성방법을 이용하면 실리콘기판을 식각하여 트렌치의 일부를 형성한 후, 결과물 상에 질화막과 반사방지막 및 실리콘기판의 선택적 옥시데이션 공정을 진행하여 소자분리막 형성을 위한 갭필 산화막 증착 시, 큰 트렌치 피치에서의 낮은 갭필산화막 단차를 보상함으로써, 후속 CMP공정에서 갭필 산화막의 디슁 현상을 방지하여 평탄화 효율을 높일 수 있고, 평탄화에 따른 게이트 포토 공정 마진을 확보하도록 하여 반도체 소자의 고 집적화를 가능하게 하는 효과가 있다.Therefore, using the method of forming a device isolation film of a semiconductor device according to the present invention, after forming a portion of a trench by etching a silicon substrate, a device isolation film is formed by performing a selective oxidization process of a nitride film, an antireflection film, and a silicon substrate on the resultant. By compensating for a low gap fill oxide step in a large trench pitch when depositing a gap fill oxide for the purpose, it is possible to prevent flattening of the gap fill oxide film in a subsequent CMP process to increase planarization efficiency and to secure a gate photo process margin due to planarization. There is an effect of enabling high integration of the semiconductor device.

Claims (5)

실리콘기판 상에 소자분리영역을 노출시키는 패드산화막 및 질화막을 형성하는 단계;Forming a pad oxide film and a nitride film exposing the device isolation region on the silicon substrate; 상기 질화막을 마스크로 상기 실리콘기판에 제1 트렌치와, 상기 제1 트렌치보다 넓은 폭의 제2 트렌치를 형성하는 단계;Forming a first trench and a second trench having a width wider than the first trench in the silicon substrate using the nitride film as a mask; 상기 제1 및 제2 트렌치가 형성된 결과물 상에 희생질화막과 반사방지막을 순차적으로 형성하는 단계;Sequentially forming a sacrificial nitride film and an anti-reflection film on a resultant product in which the first and second trenches are formed; 상기 반사방지막에 에치백 공정을 진행하여 상기 제2 트렌치의 중심부의 희생질화막을 노출시키는 단계;Performing an etch back process on the anti-reflection film to expose the sacrificial nitride film in the central portion of the second trench; 노출된 상기 희생질화막을 식각하여 상기 실리콘기판을 노출시키는 단계;Etching the exposed sacrificial nitride layer to expose the silicon substrate; 상기 반사방지막을 제거하고 제2 트렌치 바닥의 노출된 실리콘기판에 산화막을 형성하는 단계;Removing the anti-reflection film and forming an oxide film on the exposed silicon substrate on the bottom of the second trench; 상기 희생질화막을 제거하는 단계;Removing the sacrificial nitride film; 상기 질화막과 산화막을 식각마스크로 하여, 제1 및 제2 트렌치 바닥의 노출된 실리콘기판을 식각하여 제3 트렌치를 형성하는 단계; 및Etching the exposed silicon substrates on the bottom of the first and second trenches by using the nitride film and the oxide film as an etching mask to form a third trench; And 상기 제1 내지 제3 트렌치를 절연막으로 매립하여 소자분리막을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체소자의 소자분리막 형성방법.And forming a device isolation film by filling the first to third trenches with an insulating film. 제1항에 있어서,The method of claim 1, 상기 제2 트렌치 바닥의 노출된 실리콘기판에 산화막을 형성하는 단계에서,In the step of forming an oxide film on the exposed silicon substrate of the bottom of the second trench, 상기 질화막을 마스크로 하여 개방된 부위만 산화시켜 산화막을 형성하는 것을 특징으로 하는 반도체소자의 소자분리막 형성방법.Forming an oxide film by oxidizing only an open portion using the nitride film as a mask. 제 1항에 있어서, 상기 반사방지막 에치백 공정 시, N2 가스와 O2가스를 사용하여 식각하는 것을 특징으로 반도체소자의 소자분리막 형성방법.The method of claim 1, wherein in the anti-reflection film etchback process, etching is performed using N 2 gas and O 2 gas. 제1항에 있어서,The method of claim 1, 상기 희생질화막을 식각하여 상기 실리콘기판을 노출시키는 단계에서,Etching the sacrificial nitride layer to expose the silicon substrate; CHF3, CF4, Ar 가스를 사용하여 상기 희생질화막을 식각하는 것을 특징으로 하는 반도체소자의 소자분리막 형성방법.And etching the sacrificial nitride film using CHF 3 , CF 4 , or Ar gas. 제1항에 있어서,The method of claim 1, 상기 희생질화막을 제거하는 단계에서,In the step of removing the sacrificial nitride film, 상기 희생질화막을 습식식각 방법으로 제거하는 것을 특징으로 하는 반도체소자의 소자분리막 형성방법.And removing the sacrificial nitride film by a wet etching method.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10622364B2 (en) 2015-05-13 2020-04-14 Samsung Electronics Co., Ltd. Method of fabricating semiconductor device
US10748906B2 (en) 2015-05-13 2020-08-18 Samsung Electronics Co., Ltd. Semiconductor device and method of fabricating the same

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101026374B1 (en) * 2004-06-22 2011-04-07 주식회사 하이닉스반도체 Isolation of semiconductor device and forming method thereof

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR970018383A (en) * 1995-09-27 1997-04-30 김주용 Trench device isolation method
KR20000061225A (en) * 1999-03-24 2000-10-16 김영환 Method for fabricating trench of semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR970018383A (en) * 1995-09-27 1997-04-30 김주용 Trench device isolation method
KR20000061225A (en) * 1999-03-24 2000-10-16 김영환 Method for fabricating trench of semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10622364B2 (en) 2015-05-13 2020-04-14 Samsung Electronics Co., Ltd. Method of fabricating semiconductor device
US10748906B2 (en) 2015-05-13 2020-08-18 Samsung Electronics Co., Ltd. Semiconductor device and method of fabricating the same
US10756092B2 (en) 2015-05-13 2020-08-25 Samsung Electronics Co., Ltd. Method of fabricating semiconductor device
US10777560B2 (en) 2015-05-13 2020-09-15 Samsung Electronics Co., Ltd. Semiconductor device and method of fabricating the same

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