KR20040003649A - Method for planation in semiconductor device - Google Patents
Method for planation in semiconductor device Download PDFInfo
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- KR20040003649A KR20040003649A KR1020020038401A KR20020038401A KR20040003649A KR 20040003649 A KR20040003649 A KR 20040003649A KR 1020020038401 A KR1020020038401 A KR 1020020038401A KR 20020038401 A KR20020038401 A KR 20020038401A KR 20040003649 A KR20040003649 A KR 20040003649A
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- oxide film
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- 238000000034 method Methods 0.000 title claims abstract description 34
- 239000004065 semiconductor Substances 0.000 title abstract description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 18
- 238000002955 isolation Methods 0.000 claims abstract description 18
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 18
- 239000010703 silicon Substances 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 150000004767 nitrides Chemical class 0.000 claims abstract description 14
- 239000000463 material Substances 0.000 claims abstract description 8
- 229920002120 photoresistant polymer Polymers 0.000 claims description 18
- 239000000126 substance Substances 0.000 claims description 10
- 238000007517 polishing process Methods 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 5
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 238000005498 polishing Methods 0.000 claims description 3
- 239000002002 slurry Substances 0.000 claims description 3
- 238000011049 filling Methods 0.000 claims description 2
- 239000011521 glass Substances 0.000 abstract description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
- H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Element Separation (AREA)
Abstract
Description
본 발명은 반도체소자의 평탄화방법에 관한 것으로서, 보다 상세하게는 STI공정 중에 형성되는 소자분리영역과 활성영역의 단차를 제거하는 방법으로서, SOG를 이용하여 갭필산화막 단차를 보상하여 갭필산화막의 평탄화 효율을 높일 수 있는 반도체소자의 평탄화방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a planarization method of a semiconductor device, and more particularly, to a method of removing a step between an isolation region and an active region formed during an STI process. It relates to a planarization method of a semiconductor device that can increase the.
일반적으로, 실리콘기판 상에 트렌지스터와 커패시터등을 형성하기 위하여 실리콘기판에는 전기적으로 통전이 가능한 활성영역과 전기적으로 통전되는 것을 방지하고 소자를 서로 분리하도록 하는 소자분리영역을 형성하게 된다.In general, in order to form transistors, capacitors, and the like on a silicon substrate, an silicon isolation region is formed in the silicon substrate to prevent electrically conduction from an electrically conductable active region and to separate devices from each other.
이와 같이, 실리콘기판에 일정한 깊이를 갖는 트렌치를 형성하고서 이 트렌치에 산화막을 증착시킨 후 화학기계적연마공정으로 이 산화막의 불필요한 부분을 식각하므로 소자분리영역을 반도체 기판에 형성시키는 STI(Shallow Trench Isolation)공정이 최근에 많이 이용되고 있다.As such, a trench having a predetermined depth is formed on the silicon substrate, and an oxide film is deposited on the trench, and a chemical mechanical polishing process etches an unnecessary portion of the oxide film, thereby forming an isolation region on the semiconductor substrate. The process has been used a lot lately.
도 1a 내지 도 1d는 종래 반도체소자의 평탄화방법을 순차적으로 설명하기 위해 나타낸 단면도이다.1A to 1D are cross-sectional views sequentially illustrating a planarization method of a conventional semiconductor device.
도 1a에 도시된 바와 같이, 실리콘기판(1) 상에 패드 산화막(3), 패드 질화막(5) 및 감광막(미도시함)을 순차적으로 증착하여 감광막 패턴을 형성한 후, 상기 감광막 패턴을 사용하여 트렌치 식각 공정에 의해 트렌치(미도시함)가 형성된다.As shown in FIG. 1A, the pad oxide layer 3, the pad nitride layer 5, and the photoresist layer (not shown) are sequentially deposited on the silicon substrate 1 to form a photoresist pattern, and then the photoresist pattern is used. Thus, trenches (not shown) are formed by the trench etching process.
그리고, 상기 트렌치(미도시함)가 형성된 반도체 기판(1) 상에 갭필산화막(13)을 증착하여 트렌치(미도시함)를 매립한다.The gap fill oxide layer 13 is deposited on the semiconductor substrate 1 having the trench (not shown) to fill the trench (not shown).
이어서, 도 1b에 도시된 바와 같이, 상기 결과물 상에 감광막을 도포하여 노광 및 현상 공정에 의해 트렌치의 형성으로 인해 소자분리영역과 활성영역의 단차가 발생된 부분에 감광막 패턴(15)을 형성한다.Subsequently, as illustrated in FIG. 1B, a photoresist film is coated on the resultant to form a photoresist pattern 15 in a portion where a step difference between the device isolation region and the active region occurs due to the formation of the trench by the exposure and development processes. .
그 후, 도 1c에 도시된 바와 같이, 상기 감광막 패턴(미도시함)을 마스크로 갭필산화막(13)을 건식식각하여 단차를 줄인 후, 감광막 패턴(미도시함)을 제거한다.Thereafter, as shown in FIG. 1C, the gap fill oxide layer 13 is dry-etched using the photoresist pattern (not shown) as a mask to reduce a step, and then the photoresist pattern (not shown) is removed.
그리고, 도 1d에 도시된 바와 같이, 상기 줄어든 단차 위로 화학기계적연마 공정을 질화막(5) 상부까지 진행하여 결과물을 평탄화한다.As shown in FIG. 1D, the chemical mechanical polishing process is performed to the upper portion of the nitride film 5 above the reduced step to planarize the resultant product.
그러나, 상기와 같은 종래 반도체소자의 평탄화방법은 소자분리영역과 활성영역의 단차를 줄이기 위해 감광막 패턴을 마스크로 건식식각하기 때문에 감광막 패턴의 위치가 틀어지거나 증착된 갭필산화막의 두께가 서로 상이하면 도 2와 같이 갭필산화막(13)이 부분적으로 파이는 현상이 발생되어 반도체소자의 특성 및 신뢰성이 저하되는 문제점이 있었다.However, the planarization method of the conventional semiconductor device as described above is dry etching the photoresist pattern with a mask to reduce the step difference between the device isolation region and the active region, so that the position of the photoresist pattern is different or the thicknesses of the deposited gap fill oxide layers are different from each other. As shown in FIG. 2, a phenomenon in which the gap fill oxide layer 13 is partially pied occurs, thereby deteriorating characteristics and reliability of the semiconductor device.
본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로서, 본 발명의 목적은 STI공정 중에 형성되는 소자분리영역과 활성영역의 단차를 제거하는 것으로 SOG를 이용하여 그 단차를 줄인 다음 화학기계적연마 공정에 의해 평탄화함으로써, 평탄화 효율을 높일 수 있는 기술이다.The present invention has been made to solve the above problems, an object of the present invention is to remove the step between the device isolation region and the active region formed during the STI process to reduce the step using SOG and then chemical mechanical polishing process It is a technique which can improve planarization efficiency by planarizing by.
도 1a 내지 도 1d는 종래의 반도체소자의 평탄화방법을 설명하기 위해 순차적으로 나타낸 단면도이다.1A through 1D are cross-sectional views sequentially illustrating a planarization method of a conventional semiconductor device.
도 2는 종래의 반도체소자의 평탄화방법에 의해 평탄화된 반도체소자의 문제점을 나타낸 단면도이다.2 is a cross-sectional view illustrating a problem of a semiconductor device planarized by a conventional semiconductor device planarization method.
도 3a 내지 도 3d는 본 발명의 실시예에 따른 반도체소자의 평탄화방법을 설명하기 위해 순차적으로 나타낸 단면도이다.3A to 3D are cross-sectional views sequentially illustrating a planarization method of a semiconductor device according to an exemplary embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
100 : 실리콘기판 110 : 패드산화막100: silicon substrate 110: pad oxide film
120 : 질화막 130 : 갭필산화막120 nitride film 130 gap gap oxide film
140 : SOG 물질 150 : 소자분리막140: SOG material 150: device isolation film
상기 목적을 달성하기 위하여, 본 발명은 실리콘기판 상에 패드산화막 및 패드질화막을 순차적으로 증착한 후 감광막을 도포하여 감광막 패턴을 형성하는 단계와, 상기 감광막 패턴을 마스크로 식각공정을 진행하여 실리콘기판 내에 트렌치를 형성하고 고밀도플라즈마 화학기상증착법에 의해 갭필산화막을 증착하여 트렌치를 매립하는 단계와, 상기 결과물 상에 갭필산화막과 동일한 계열의 SOG물질을 증착한 후 베이킹 및 큐어링 열공정을 진행하는 단계와, 상기 SOG물질과 갭필산화막을 동시에 드라이 에치백 공정을 진행하여 소자분리영역과 활성영역의 단차를 줄이는 단계와, 상기 드라이 에치백 공정에 의해 단차가 감소된 갭필산화막을 질화막까지 화학기계적연마 공정을 진행하여 평탄화하는 단계를 포함하여 이루어진 것을 특징으로 하는 반도체소자의 평탄화방법을 제공한다.In order to achieve the above object, the present invention sequentially deposits a pad oxide film and a pad nitride film on a silicon substrate, and then forms a photoresist pattern by applying a photoresist layer, and etching the photoresist pattern with a mask to perform a silicon substrate. Forming a trench in the trench and depositing a gapfill oxide film by high density plasma chemical vapor deposition to fill the trench; In addition, the step of dry etching back the SOG material and the gap-fill oxide film at the same time to reduce the step between the device isolation region and the active region, and the chemical mechanical polishing process of the gap-fill oxide film having a reduced step by the dry etchback process to the nitride film Peninsula characterized in that it comprises a step of flattening by proceeding It provides a method of planarizing element.
바람직하게 본 발명은 상기 드라이 에치 백 공정 시, C와 F를 주성분으로 하여 이루어진 플라즈마를 사용하여 소자분리영역과 활성영역의 단차를 줄이며, 상기 화학기계적연마 공정 시에는, KOH 또는 NH4OH를 포함한 슬러리를 이용하여 연마하는 것을 특징으로 한다.Preferably, the present invention reduces the step difference between the device isolation region and the active region by using a plasma composed mainly of C and F during the dry etch back process, and includes KOH or NH 4 OH during the chemical mechanical polishing process. It is characterized by polishing using a slurry.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 3a 내지 도 3d는 본 발명의 실시예에 따른 반도체소자의 소자분리막 제조방법을 설명하기 위해 순차적으로 나타낸 단면도이다.3A to 3D are cross-sectional views sequentially illustrating a method of manufacturing a device isolation film of a semiconductor device according to an embodiment of the present invention.
도 3a에 도시된 바와 같이, 실리콘기판(100) 상에 패드산화막(110)과질화막(120)을 순차적으로 증착한 후 질화막(120) 상에 트렌치를 형성하기 위한 감광막 패턴(미도시함)을 형성한다.As shown in FIG. 3A, after the pad oxide film 110 and the nitride film 120 are sequentially deposited on the silicon substrate 100, a photoresist pattern (not shown) for forming a trench on the nitride film 120 is formed. Form.
이때, 상기 질화막(120)은 후속 트렌치 식각공정 시, 식각 마스크로 사용할 수 있으며, 혹은 후속 공정인 화학기계적연마 공정에서 식각정지막으로 사용된다.In this case, the nitride film 120 may be used as an etching mask in a subsequent trench etching process, or may be used as an etch stop layer in a subsequent chemical mechanical polishing process.
그리고, 상기 감광막 패턴(미도시함)을 마스크로 이용하여 실리콘기판(100) 상의 필드영역이 노출되도록 질화막(120)과 패드산화막(110)을 순차적으로 식각하고, 감광막 패턴(미도시함)을 제거하여 필드 영역의 실리콘기판(100)을 노출시킨다.The nitride film 120 and the pad oxide film 110 are sequentially etched to expose the field region on the silicon substrate 100 using the photoresist pattern (not shown) as a mask, and the photoresist pattern (not shown) is etched. It removes and exposes the silicon substrate 100 of a field area.
이어서, 상기 질화막(120)을 마스크로 건식식각하여 실리콘기판(100) 내에 트렌치(미도시함)를 형성하고, 고밀도플라즈마 화학기상증착법에 의해 갭필산화막(130)인 SiO2막을 증착하여 트렌치를 매립한다.Subsequently, the nitride film 120 is dry-etched with a mask to form a trench (not shown) in the silicon substrate 100, and a SiO 2 film, which is a gap fill oxide film 130, is deposited by high density plasma chemical vapor deposition (CVD) to fill the trench. do.
그러나, 이때, 상기 실리콘기판(100) 내에 형성된 트렌치에 의해 갭필산화막(130)인 SiO2막을 증착시, 실리콘기판(100) 내에 형성된 트렌치에 의해 소자분리영역과 활성영역의 단차가 발생된다.However, at this time, when the SiO 2 film, which is the gap fill oxide film 130, is deposited by the trench formed in the silicon substrate 100, a step between the device isolation region and the active region is generated by the trench formed in the silicon substrate 100.
그리고, 도 3b에 도시된 바와 같이, 상기 갭필산화막(130)인 SiO2막 상에 SiO2계열의 SOG(Silicon-On-Glass)물질(140)을 스핀 코팅 방법으로 증착한 후, 고온의 베이킹(Baking) 및 큐어링(Curing) 열공정을 진행하여 SOG물질(140)을 단단하게 한다.And, as shown in Figure 3b, after depositing a SiO 2 series SOG (Silicon-On-Glass) material 140 of the SiO 2 series on the SiO 2 film, the gap-fill oxide film 130 by a spin coating method, high temperature baking The baking and curing heat process is performed to harden the SOG material 140.
이어서, 도 3c에 도시된 바와 같이, 상기 SOG물질(140)과 갭필산화막(130)을동시에 C와 F를 주성분으로 하여 이루어진 플라즈마를 사용하여 드라이 에치백 공정을 진행함으로써, 실리콘기판(100) 내에 형성된 트렌치에 의한 소자분리영역과 활성영역의 단차를 줄인다.Subsequently, as shown in FIG. 3C, the SOG material 140 and the gap-fill oxide film 130 are subjected to a dry etch back process using a plasma composed of C and F as the main components at the same time. The step difference between the device isolation region and the active region by the formed trench is reduced.
그 후, 도 3d에 도시된 바와 같이, 상기 결과물을 KOH 또는 NH4OH를 포함한 슬러리를 이용한 화학기계적연마(CMP) 공정에 의해 질화막(120) 상부까지 평탄화하여 소자분리막(150)을 형성한다.Thereafter, as shown in FIG. 3D, the resultant is planarized to the upper portion of the nitride film 120 by a chemical mechanical polishing (CMP) process using a slurry including KOH or NH 4 OH to form the device isolation film 150.
따라서, 본 발명에 따른 반도체 소자의 소자분리막 형성방법을 이용하면 STI공정 중에 형성되는 소자분리영역과 활성영역의 단차를 제거하는 방법으로서, 트렌치를 갭필산화막에 의해 매립한 후, SOG를 이용하여 단차를 줄인 다음 화학기계적연마 공정에 의해 평탄화함으로써, 평탄화 효율을 높일 수 있고, 평탄화에 따른 후속공정의 안정화를 추구할 수 있으며, 그로 인해 반도체소자의 제조수율을 향상시킬 수 있는 효과가 있다.Therefore, the method of forming a device isolation film of a semiconductor device according to the present invention is a method of removing the step difference between the device isolation region and the active region formed during the STI process, and after filling the trench with a gapfill oxide film, By reducing and then planarizing by a chemical mechanical polishing process, it is possible to increase the planarization efficiency, to pursue the stabilization of the subsequent process according to the planarization, thereby improving the manufacturing yield of the semiconductor device.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7608543B2 (en) | 2006-06-30 | 2009-10-27 | Hynix Semiconductor Inc. | Method for planarizing thin layer of semiconductor device |
| CN110931421A (en) * | 2018-09-20 | 2020-03-27 | 长鑫存储技术有限公司 | Shallow trench isolation structure and manufacturing method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7608543B2 (en) | 2006-06-30 | 2009-10-27 | Hynix Semiconductor Inc. | Method for planarizing thin layer of semiconductor device |
| CN110931421A (en) * | 2018-09-20 | 2020-03-27 | 长鑫存储技术有限公司 | Shallow trench isolation structure and manufacturing method |
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