KR970018383A - Trench device isolation method - Google Patents

Trench device isolation method Download PDF

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Publication number
KR970018383A
KR970018383A KR1019950032092A KR19950032092A KR970018383A KR 970018383 A KR970018383 A KR 970018383A KR 1019950032092 A KR1019950032092 A KR 1019950032092A KR 19950032092 A KR19950032092 A KR 19950032092A KR 970018383 A KR970018383 A KR 970018383A
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South Korea
Prior art keywords
film
oxide film
layer
trench
oxide
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KR1019950032092A
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Korean (ko)
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권성구
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김주용
현대전자산업 주식회사
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Priority to KR1019950032092A priority Critical patent/KR970018383A/en
Publication of KR970018383A publication Critical patent/KR970018383A/en

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Abstract

본 발명은 반도체소자의 소자분리막 제조방법에 관한 것으로, 트렌치 구조의 소자분리막을 형성할 때 듀얼 구조의 트렌치로 형성하여 산화막 두께를 얇게 하고 에치백 공정으로 듀얼 트렌치의 상부에만 산화막을 남겨 듀얼 소자분리막을 형성함으로 인하여 산화막을 적게 증착하여도 되며, 트렌치에 산화막을 채우는 공정이 용이하고, 산화막의 에치백을 정확하게 제어 할수가 있다.The present invention relates to a method for manufacturing a device isolation film of a semiconductor device, when forming a device isolation film of a trench structure formed of a dual-structure trench to reduce the thickness of the oxide film and leave the oxide film only on the upper portion of the dual trench in the etchback process dual device isolation film Since the oxide film may be deposited less, the process of filling the trench with the oxide film is easy, and the etchback of the oxide film can be precisely controlled.

Description

트렌치 소자분리막 제조방법Trench device isolation method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1A도 내지 제1H도는 본 발명의 제1실시예에 의해 듀얼 트렌치 소자분리막을 형성하는 단계를 도시한 단면도.1A to 1H are cross-sectional views illustrating a step of forming a dual trench device isolation film in accordance with a first embodiment of the present invention.

Claims (12)

트렌치 소자분리막 제조방법에 있어서, 반도체 기판에 패드산화막, 질화막, 제1산화막을 각각 일정 두계적층하고, 그 상부에 소자분리 마스크를 이용한 식각공정으로 제1산화막, 질화막 패턴을 형성하는 단계가 전체적으로 실리콘이 도포된 실리콘층을 증착하고, 실리콘층의 요부에 제2산화막을 매립하는 단계와, 제2산화막을 마스크로 이용하여 상기 실리콘층을 식각하고, 계속하여 노출되는 패드산화막과 그하부의 반도체기판의 일정깊이 까지 식각하여 듀얼 트렌치를 형성하는 단계와, 제3산화막을 두껍게 증착하고, 제3산화막을 상기 질화막이 노출되도록 에치백하여 듀얼 트렌치 상부의 요부에만 제3산화막을 남기는 단계와, 남아있는 질화막과 패드산화막을 제거하여 듀얼 트렌치 소자분리막을 형성하는 단계를 포함하는 트렌치 소자분리막 제조방법.In the method of fabricating a trench isolation layer, a step of forming a first oxide layer and a nitride layer pattern on the semiconductor substrate by laminating a pad oxide layer, a nitride layer, and a first oxide layer on the semiconductor substrate by an etching process using a device isolation mask thereon. Depositing the coated silicon layer, embedding a second oxide film in the recess of the silicon layer, etching the silicon layer using the second oxide film as a mask, and subsequently exposing the pad oxide film and a semiconductor substrate thereunder; Forming a dual trench by etching to a predetermined depth, depositing a third oxide layer thickly, and etching back the third oxide layer to expose the nitride layer, leaving only the third oxide layer only in the upper portion of the dual trench. Fabrication of a trench device isolation film comprising removing the nitride film and the pad oxide film to form a dual trench device isolation film Law. 제1항에 있어서, 상기 제2산화막은 CVD 산화막을 증착하고, 그 상부에 BPSG막 또는 SOG막으로 평탄화시킨 것을 특징으로 하는 트렌치 소자분리막 제조방법.The method of claim 1, wherein the second oxide film is deposited with a CVD oxide film and flattened with a BPSG film or an SOG film thereon. 제1항에 있어서, 상기 듀얼 트렌치의 깊이는 500-2000Å인 것을 특징으로 하는 트렌치 소자분리막 제조방법.The method of claim 1, wherein the depth of the dual trench is 500-2000 μs. 제1항에 있어서, 상기 듀얼 트렌치 상부의 요부에만 제3산화막을 암긴 다음에 남아있는 실리콘층을 산화시키는 공정을 포함하는 트렌치 소자불리막 제조방법.The method of claim 1, further comprising oxidizing a silicon layer remaining after the third oxide film is only embedded in the upper portion of the dual trench. 제1항에 있어서, 상기의 패드산화막은 50-300Å의 두께로 형성하고, 상기 질화막은 1000-3000Å의 두께로 형성하고, 상기 제1산화막은 50-500Å의 두께로 형성하는 것을 특징으로 하는 트렌치 소자분리막 제조방법.The trench of claim 1, wherein the pad oxide film is formed to a thickness of 50-300 kPa, the nitride film is formed to a thickness of 1000-3000 kPa, and the first oxide film is formed to a thickness of 50-500 kPa. Device isolation film manufacturing method. 제1항에 있어서, 상기 실리콘층은 DVD 증착방법으로 300-1000Å의 두께로 형성되는 것을 특징으로 하는 트렌치 소자분리막 제조방법.The method of claim 1, wherein the silicon layer is formed to a thickness of 300-1000 Å by a DVD deposition method. 제1항에 있어서, 상기 실리콘층의 요부에 제2산화막을 매립하는 것은 제2산화막을 두껍게 증착하고 에치백하는 단계로 이루어지는 것을 특징으로 하는 트렌치 소자분리막 제조방법.The method of claim 1, wherein the buried second oxide film is formed in the recess of the silicon layer, wherein the second oxide film is thickly deposited and etched back. 트렌치 소자분리막 제조방법에 있어서, 반도체 기판에 패드산화막, 질화막, 제1산화막을 각각 일정 두께 적층하고, 소자분리 마스크를 이용한 식각 공정으로 제1산화막, 질화막을 식각하여 소자분리 마스크용 패턴을 형성하는 단계와, 상기 질화막과 제1산화막 패턴이 측벽에 실리콘 스페이서를 형성하는 단계와, 상기 제2산화막을 실리콘 스페이서 사이의 요부에만 남도록 형성하는 단계와, 상기 제2 산화막을 마스크로 이용하여 상기 실리콘 스페이서을 식각하고, 계속하여 노출되는 패드산화막과 그 하부의 반도체기판의 일정깊이까지 듀얼 트렌치를 형성하는 단계와, 전체적으로 제3산화막을 그 상부에 평탄화막을 형성하는 단계와, 상기 평탄화막과 제3산화막을 상기 질화막이 노출되도록 에치백하여 듀얼 트렌치 상부의 요부에만 제3산화막이 남도록 하여 듀얼 트렌치 소자분리산화막을 형성하는 단계를 포함하는 트렌치 소자분리막 제조방법.In the method of manufacturing a trench isolation film, a pad oxide film, a nitride film, and a first oxide film are laminated on a semiconductor substrate by a predetermined thickness, and the first oxide film and the nitride film are etched by an etching process using an device isolation mask to form a device isolation mask pattern. Forming a silicon spacer on a sidewall of the nitride film and the first oxide film pattern, leaving the second oxide film only in a recess between the silicon spacers, and using the second oxide film as a mask. Etching and forming a dual trench to a predetermined depth of the pad oxide film and the semiconductor substrate under the exposed portion, forming a planarization film on the third oxide film as a whole, and forming the planarization film and the third oxide film The oxide is etched back so that the nitride film is exposed so that the third oxide layer remains only in the recessed portion of the upper portion of the dual trench. The method of manufacturing a trench device isolation film and forming a dual trench isolation oxide film. 제9항에 있어서, 상기 제2산화막은 CVD 산화막을 증착하고, 그 상부에 BPSG막 또는 SOG막으로 평탄화시킨 것을 특징으로 하는 트렌치 소자분리막 제조방법.10. The method of claim 9, wherein the second oxide film is formed by depositing a CVD oxide film and planarizing a BPSG film or an SOG film thereon. 제9항에 있어서, 상기 듀얼 트렌치의 깊이는 500-2000Å인 것을 특징으로 하는 트렌치 소자분리막 제조방법.10. The method of claim 9, wherein the depth of the dual trench is 500-2000 microns. 제9항에 있어서, 상기 패드산화막은 50-300Å의 두께로 형성하고, 상기 질화막은 1000-3000Å의 두께로 형성하고 상기 제1산화막은 50-500Å의 두께로 형성하는 것을 특징으로 하는 트렌치 소자분리막 제조방법.10. The trench isolation layer as claimed in claim 9, wherein the pad oxide film is formed to a thickness of 50-300 kPa, the nitride film is formed to a thickness of 1000-3000 kPa, and the first oxide film is formed to a thickness of 50-500 kPa. Manufacturing method. 제9항에 있어서, 상기 실리콘층은 CVD 증착방법으로 300-1000Å의 두께로 형성하는 것을 특징으로 하는 트렌치 소자분리막 제조방법.10. The method of claim 9, wherein the silicon layer is formed by a thickness of 300-1000 Å by CVD deposition.
KR1019950032092A 1995-09-27 1995-09-27 Trench device isolation method KR970018383A (en)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100390894B1 (en) * 1997-12-16 2003-10-10 주식회사 하이닉스반도체 Method of forming isolation film for semiconductor device
KR100480625B1 (en) * 2002-10-24 2005-03-31 삼성전자주식회사 Method for forming trench isolation and semiconductor device comprising the same
KR100712985B1 (en) * 2001-02-08 2007-05-02 주식회사 하이닉스반도체 Method for forming the Isolation Layer in Semiconductor Device
KR100714901B1 (en) * 2006-07-31 2007-05-04 삼성전자주식회사 Methods of forming contact structure
KR100868925B1 (en) * 2002-07-03 2008-11-17 매그나칩 반도체 유한회사 Method for forming the Isolation Layer of Semiconductor Device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100390894B1 (en) * 1997-12-16 2003-10-10 주식회사 하이닉스반도체 Method of forming isolation film for semiconductor device
KR100712985B1 (en) * 2001-02-08 2007-05-02 주식회사 하이닉스반도체 Method for forming the Isolation Layer in Semiconductor Device
KR100868925B1 (en) * 2002-07-03 2008-11-17 매그나칩 반도체 유한회사 Method for forming the Isolation Layer of Semiconductor Device
KR100480625B1 (en) * 2002-10-24 2005-03-31 삼성전자주식회사 Method for forming trench isolation and semiconductor device comprising the same
KR100714901B1 (en) * 2006-07-31 2007-05-04 삼성전자주식회사 Methods of forming contact structure

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