KR0168164B1 - Method of fabricating semiconductor device - Google Patents
Method of fabricating semiconductor device Download PDFInfo
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- KR0168164B1 KR0168164B1 KR1019950041456A KR19950041456A KR0168164B1 KR 0168164 B1 KR0168164 B1 KR 0168164B1 KR 1019950041456 A KR1019950041456 A KR 1019950041456A KR 19950041456 A KR19950041456 A KR 19950041456A KR 0168164 B1 KR0168164 B1 KR 0168164B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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Abstract
본 발명은 반도체 소자의 제조방법이 개시된다.The present invention discloses a method for manufacturing a semiconductor device.
다수의 금속배선이 형성된 기판상에 HDP 산화막과 SOG막을 순차적으로 형성한 후, SOG막이 완전히 제거되는 시점까지 블랭켓 식각공정을 실시하여 표면 평탄화를 이룬 금속층간 절연막을 형성한다.After the HDP oxide film and the SOG film are sequentially formed on the substrate on which the plurality of metal wirings are formed, a blanket etching process is performed until the SOG film is completely removed to form an interlayer insulating film having a surface planarization.
따라서, 본 발명은 단순한 공정에 의한 금속층간 절연막의 평탄화로 생산단가를 줄일 수 있고, SOG막으로 인한 문제점을 근본적으로 해결하여 소자의 신뢰성을 향상시킬 수 있다.Therefore, the present invention can reduce the production cost by planarizing the interlayer insulating film by a simple process, and can fundamentally solve the problems caused by the SOG film, thereby improving the reliability of the device.
Description
제1도는 종래 제1실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 소자의 단면도.1 is a cross-sectional view of a device for explaining a method of manufacturing a semiconductor device according to the first embodiment of the prior art.
제2a 및 2b도는 종래 제2실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 소자의 단면도.2A and 2B are cross-sectional views of a device for explaining a method of manufacturing a semiconductor device according to a second embodiment of the prior art.
제3a 내지 3c도는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 소자의 단면도.3A to 3C are cross-sectional views of devices for describing a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
21 : 실리콘 기판 22 : 하부층21 silicon substrate 22 lower layer
23a, 23b, 23c : 금속배선 24 : 금속층간 절연막23a, 23b, 23c: metal wiring 24: metal interlayer insulating film
24a : HDP 산화막 24b : SOG 막24a: HDP oxide film 24b: SOG film
25 : 비아홀25: Via Hole
a : 셀 지역 b : 주변회로 지역a: cell area b: peripheral circuit area
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 다층 금속 배선구조에서 금속층간 절연막의 평탄화를 용이하게 이룰 수 있는 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device that can easily planarize an insulating film between metal layers in a multilayer metal wiring structure.
반도체 소자가 고집적화됨에 따라 금속배선은 다층 구조로 이루어지고 있으며, 이들 다층 금속배선간을 절연시키는 금속층간 절연막으로는 SOG(Spin On Glass)가 많이 사용되고 있다.As semiconductor devices have been highly integrated, metal wirings have a multi-layered structure, and SOG (Spin On Glass) is widely used as an interlayer insulating film that insulates the multilayer metal wirings.
제1도는 금속층간 절연막의 평탄화를 위해 SOG를 사용한 종래 제1실시예를 도시한 소자의 단면도이다. 일반적인 공정에 따라 실리콘 기판(1)상에 예정된 단위셀(도시않음)이 형성된다. 단위셀을 포함한 실리콘 기판(1)상부에 하부층(2)이 형성되는데, 이 하부층(2)은 외부요인으로부터 단위셀을 보호하기 위하여, 플로우(flow)특성이 우수한 BPSG(Born Phosphorous Silicate Glass)등과 같은 절연물로 형성된다. 하부층(2)은 셀지역(a)과 주변회로 지역(b)사이에서 토플러지(topology)가 심화된다. 하부층(2)상에 다수의 금속배선(3a, 3b 및 3c)이 형성된다. 이들 금속배선(3a, 3b 및 3c)의 상부쪽에 형성될 다른 금속배선(도시않음)과 전기적으로 절연하기 위하여, 금속층간 절연막(4)이 금속배선들(3a, 3b 및 3c)을 포함한 하부층(2)상에 형성된다. 금속층간 절연막(4)은 제1절연막(4a), 제2절연막(4b) 및 제3절연막(4c)을 순차적으로 형성하여 3층 구조로 이루어진다. 제1절연막(4a)은 TEOS를 얇게 증착하여 형성되고, 제2절연막(4b)은 금속층간 절연막(4)의 표면 평탄화를 개선시키기 위해 SOG를 도포하여 형성되며, 제3절연막(4c)은 TEOS를 두껍게 증착하여 형성된다. SOG 막(4b)은 고도(高度)가 높은 지역인 셀 지역(a)에서는 금속배선들(3a 및 3b)사이에 형성되고, 고도가 낮은 지역인 주변회로 지역(b)에서는 금속배선(3c)상부쪽을 포함한 전체구조상에 형성되어 표면 평탄화를 이루게 한다. 금속콘택공정을 통해 금속층간 절연막(4)의 일정부분을 시작함에 의해 주변회로 지역(b)에 형성된 금속배선(3c)의 일부분이 노출되는 비아홀(5)이 형성된다. 비아홀(5)의 측벽에는 SOG막(4b)이 일부 노출되는데, SOG막(4b)은 물성(物性)상 수분이 다량 함유되어 있기 때문에 이후 진행되는 공정동안 비아홀(5)부분으로부터 수분이 유출되어 반도체 소자의 신뢰성을 저하시키는 문제가 있다.FIG. 1 is a cross-sectional view of a device showing a conventional first embodiment using SOG for planarization of an intermetallic insulating film. According to a general process, a predetermined unit cell (not shown) is formed on the silicon substrate 1. The lower layer 2 is formed on the silicon substrate 1 including the unit cell, and the lower layer 2 is formed of BPSG (Born Phosphorous Silicate Glass) having excellent flow characteristics in order to protect the unit cell from external factors. It is formed of the same insulation. In the lower layer 2, the topology is deepened between the cell region a and the peripheral circuit region b. A plurality of metal wires 3a, 3b and 3c are formed on the lower layer 2. In order to electrically insulate with other metal wires (not shown) to be formed on the upper sides of these metal wires 3a, 3b, and 3c, the interlayer insulating film 4 includes a lower layer including metal wires 3a, 3b, and 3c ( 2) is formed on the phase. The interlayer insulating film 4 has a three-layer structure by sequentially forming a first insulating film 4a, a second insulating film 4b, and a third insulating film 4c. The first insulating film 4a is formed by thinly depositing TEOS, the second insulating film 4b is formed by applying SOG to improve the surface planarization of the interlayer insulating film 4, and the third insulating film 4c is formed by TEOS. It is formed by depositing thick. The SOG film 4b is formed between the metal wires 3a and 3b in the cell area (a), which is a high altitude area, and the metal wiring 3c in the peripheral circuit area (b), a low altitude area. It is formed on the entire structure including the upper side to achieve surface planarization. By starting a portion of the interlayer insulating film 4 through the metal contact process, a via hole 5 through which a portion of the metal wiring 3c formed in the peripheral circuit region b is exposed is formed. Part of the SOG film 4b is exposed on the sidewall of the via hole 5, and since the SOG film 4b contains a large amount of water in its physical property, water is leaked from the via hole 5 during the subsequent process. There is a problem of lowering the reliability of the semiconductor device.
비아홀(5)의 측벽에 SOG막(4b)이 노출되는 것을 방지하기 위한 방법으로 SOG막(4b)을 형성한후, 주변회로 지역(b)의 금속배선(3c)상부의 SOG막(4b)이 제거될 때까지 에치백(etch back)공정을 실시한다. 이 방법은 비아홀(5)에서 SOG막(4b)이 노출되는 것을 방지하여 상기한 문제점을 해결할 수 있지만, 공정수가 많아짐에 따라 생산단가가 높아지고, 양호한 표면 평탄화를 이룰 수 없는 문제가 있다.After the SOG film 4b is formed in a way to prevent the SOG film 4b from being exposed on the sidewall of the via hole 5, the SOG film 4b on the metal wiring 3c in the peripheral circuit area b is formed. The etch back process is performed until this is removed. This method can solve the above-mentioned problem by preventing the SOG film 4b from being exposed in the via hole 5, but there is a problem that the production cost increases as the number of processes increases, and that a good surface planarization cannot be achieved.
제2a 및 2b 도는 SOG를 사용하지 않고 금속층간 절연막을 평탄화 하는 종래 제2실시예를 도시한 소자의 단면도이다. 전술한 제1실시예와 마찬가지로 일반적인 공정에 따라 실리콘 기판(11)상에 사부층(12)이 형성되고, 하부층(12)상에 다수의 금속배선(13a, 13b 및 13c)이 형성된다. 이들 금속배선(13a, 13b 및 13c)의 상부쪽에 형성될 다른 금속배선(도시않음)과 전기적으로 절연하기 위하여, 금속층간 절연막(14)이 금속배선들(13a, 13b 및 13c)을 포함한 하부층(12)상에 형성된다. 금속층간 절연막(14)은 제1절연막(14a) 및 제2절연막(14b)을 순차적으로 형성하여 2층 구조로 이루어진다. 제1절연막(14a)은 스텝커버리지(stepcoverage) 특성이 우수한 HDP(High Density Plasma)산화막이며, 제2절연막(14b)은 TEOS를 두껍게 증착하여 형성된다. 고도가 높은 지역인 셀 지역(a)과 고도가 낮은 지역인 주변회로 지역(b)사이에서 심화된 토플러지와 하부층(12)상에 형성된 다수의 금속배선(13a, 13b 및 13c)에 의해 금속층간 절연막(14)의 표면은 굴곡이 심하게 형성된다.(제2a도). 금속층간 절연막(14)의 표면 평탄화를 이루기 위하여, 화학기계적 연마(Chemical Mechnical Polishing; CMP)공정으로 금속층간 절연막(14)의 표면을 일정깊이 연마함에 의해 금속층간 절연막(14)의 표면은 평탄화된다. 금속콘택공정을 통해 금속층간 절연막(14)의 일정부분을 식각함에 의해 주변회로 지역(b)에 형성된 금속배선(13c)의 일부분이 노출되는 비아홀(15)이 형성된다. 그런데, 금속층간 절연막(14)의 표면 평탄화는 아주 우수하지만, 반면에 주변회로 지역(b)에 형성된 금속배선 (13c)을 덮고 있는 금속층간 절연막(14)의 두께가 두꺼운 관계로 비아홀(15)의 깊이가 깊어져 금속배선(13c)과 연결되는 다른 금속배선(도시않됨)을 형성할 때 스텝커버리지가 나빠지는 문제가 있다.2A and 2B are cross-sectional views of a device showing a second embodiment of the prior art planarizing the interlayer insulating film without using SOG. Similar to the first embodiment described above, a quadrilateral layer 12 is formed on the silicon substrate 11 and a plurality of metal wires 13a, 13b, and 13c are formed on the lower layer 12 according to a general process. In order to electrically insulate with other metal wires (not shown) to be formed on the upper sides of these metal wires 13a, 13b, and 13c, the interlayer insulating film 14 includes a lower layer including the metal wires 13a, 13b, and 13c ( 12) is formed on. The interlayer insulating film 14 is formed in a two-layer structure by sequentially forming the first insulating film 14a and the second insulating film 14b. The first insulating film 14a is a high density plasma (HDP) oxide film having excellent step coverage, and the second insulating film 14b is formed by thickly depositing TEOS. Metal is formed by a plurality of metallizations 13a, 13b, and 13c formed on the lower layer 12 and a deep topflop between the cell region (a), which is a high altitude, and the peripheral circuit region (b), which is a high altitude. The surface of the interlayer insulating film 14 is heavily curved. (FIG. 2A). In order to achieve surface planarization of the interlayer insulating film 14, the surface of the interlayer insulating film 14 is planarized by polishing the surface of the interlayer insulating film 14 in a predetermined depth by a chemical mechanical polishing (CMP) process. . By etching a portion of the interlayer insulating layer 14 through a metal contact process, a via hole 15 through which a portion of the metal wiring 13c formed in the peripheral circuit region b is exposed is formed. By the way, although the surface planarization of the interlayer insulating film 14 is excellent, on the other hand, since the thickness of the interlayer insulating film 14 covering the metal wiring 13c formed in the peripheral circuit area b is thick, the via hole 15 is formed. There is a problem that the step coverage is worse when the depth of the deeper to form another metal wiring (not shown) connected to the metal wiring 13c.
따라서, 본 발명은 비아홀에서 SOG막의 노출로 인한 문제점을 해결하여 소자의 신뢰성을 향상시킬 수 있는 반도체 소자의 제조방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device capable of improving the reliability of the device by solving the problem caused by the exposure of the SOG film in the via hole.
본 발명의 다른 목적은 비아홀의 깊이를 줄여 후속공정시 스텝커버리지를 개선할수 있는 반도체 소자의 제조방법을 제공함에 있다.Another object of the present invention is to provide a method of manufacturing a semiconductor device that can reduce the depth of via holes and improve step coverage in subsequent processes.
본 발명의 또다른 목적은 공정의 단순화를 통해 생산단가를 줄일 수 있는 반도체 소자의 제조방법을 제공함에 있다.Another object of the present invention is to provide a method of manufacturing a semiconductor device that can reduce the production cost through the simplification of the process.
이러한 목적들을 달성하기 위한 본 발명의 반도체 소자 제조방법은 다수의 금속배선이 형성된 기판이 제공되는 단계와, 상기 다수의 금속배선을 포함한 상기 기판상에 HDP산화막이 형성되는 단계와, 상기 HDP산화막상에 SOG막이 형성되는 단계와, 상기 SOG 막을 블랭켓 식각공정으로 식각함에 의해 표면 평탄화를 이룬 금속층간 절연막이 형성되는 단계로 이루어지는 것을 특징으로 한다.The semiconductor device manufacturing method of the present invention for achieving these objects is provided with a step of providing a substrate having a plurality of metal wiring, the step of forming an HDP oxide film on the substrate including the plurality of metal wiring, and on the HDP oxide film Forming an SOG film on the substrate; and forming an interlayer insulating film having a surface planarization by etching the SOG film by a blanket etching process.
이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제3a 내지 3c도는 본 발명의 실시예에 따른 금속층간 절연막의 평탄화방법을 설명하기 위한 소자의 단면도이다.3A to 3C are cross-sectional views of devices for explaining the planarization method of the interlayer insulating film according to the embodiment of the present invention.
제3a도를 참조하면, 일반적인 공정에 따라 실리콘 기판(21)상에 예정된 다누이셀(도시않음)이 형성된다. 단위셀을 포함한 실리콘 기판(21)상부에 하부층(22)이 형성되는데, 이 하부층(22)은 외부요인으로부터 단위셀을 보호하기 위하여, 플로우(flow)특성이 우수한 BPSG(Born Phosphorous Silicate Glass)등과 같은 절연물로 형성된다. 하부층(22)은 셀 지역(a)과 주변회로 지역(b) 사이에서 토플러지(topology)가 심화된다. 하부층(22)상에 다수의 금속배선(23a, 23b 및 23c)이 형성된다. 이들 금속배선(23a, 23b 및 23c)을 포함한 하부층(22) 상에 스텝커버리지 특성이 우수한 HDP산화막(24a)이 형성된다. HDP 산화막(24a)은 8000 내지 14000Å의 두께로 형성되며, 고도가 높은 지역인 셀 지역(a)과 고도가 낮은 지역인 주변회로 지역(b)사이에서 심화된 토플러지와 하부층(22)상에 형성된 다수의 금속배선(23a, 23b 및 23c)에 의해 그 표면에 굴곡이 심하게 나타난다.Referring to FIG. 3A, a predetermined Danui cell (not shown) is formed on the silicon substrate 21 according to a general process. A lower layer 22 is formed on the silicon substrate 21 including the unit cells. The lower layer 22 is formed of BPSG (Born Phosphorous Silicate Glass) having excellent flow characteristics in order to protect the unit cells from external factors. It is formed of the same insulation. The top layer 22 is deepened between the cell region a and the peripheral circuit region b. A plurality of metal wires 23a, 23b and 23c are formed on the lower layer 22. An HDP oxide film 24a having excellent step coverage characteristics is formed on the lower layer 22 including these metal wirings 23a, 23b, and 23c. The HDP oxide film 24a is formed to a thickness of 8000 to 14000Å, and is formed on the top layer and the lower layer 22 between the cell region (a), which is a high altitude region, and the peripheral circuit region (b), which is a high altitude region. A plurality of metal wires 23a, 23b, and 23c formed cause severe bending on the surface.
제3b도를 참조하면, 평탄화 특성이 우수한 SOG막(24b)은 HDP 산화막(24a)상에 형성된다. SOG막(24b)은 1000 내지 2000Å의 두께로 형성되며, 우수한 평탄화 특성으로 인하여 굴곡진 표면을 매끄럽게 한다. 그러나 이러한 상태에서 비아홀을 형성할 경우, 종래 제1실시예에서 설명된 바와같은 SOG막의 노출로 인한 문제점을 극복할 수 없다.Referring to FIG. 3B, an SOG film 24b having excellent planarization characteristics is formed on the HDP oxide film 24a. The SOG film 24b is formed to a thickness of 1000 to 2000 GPa, and smooth the curved surface due to the excellent planarization characteristics. However, when the via hole is formed in this state, the problem caused by the exposure of the SOG film as described in the first embodiment cannot be overcome.
제3c도를 참조하면, 블랭켓 식각(blanket etch)공정을 SOG막(24b)이 완전히 제거될 시점까지 예를들어, 3000내지 5000Å의 식각 타겟(target)으로 실시함에 의해 표면 평탄화를 이룬 본 발명의 금속층간 절연막(24)이 형성된다. 블랭켓 식각공정시 SOG막(24b)과 HDP 산화막(24a)의 식각 선택비는 1 : 1이 되도록 한다. 금속콘택공정을 통해 금속층간 절연막(24)의 일정부분을 식각함에 의해 주변회로 지역(b)에 형성된 금속배선 (23c)의 일부분이 노출되는 비아홀(25)이 형성된다.Referring to FIG. 3C, the present invention achieves surface planarization by performing a blanket etch process with an etching target of, for example, 3000 to 5000 kPa until the SOG film 24b is completely removed. An intermetallic insulating film 24 is formed. In the blanket etching process, the etching selectivity of the SOG film 24b and the HDP oxide film 24a is 1: 1. By etching a portion of the interlayer insulating film 24 through a metal contact process, a via hole 25 through which a portion of the metal wiring 23c formed in the peripheral circuit region b is exposed is formed.
상술한 바와같이 본 발명에 의하면, HDP 산화막과 SOG막을 형성하는 공정과 블랭켓 식각공정만으로 평탄화를 이룬 금속층간 절연막을 형성할 수 있다.As described above, according to the present invention, a planarized interlayer insulating film can be formed only by the steps of forming the HDP oxide film and the SOG film and the blanket etching process.
따라서, 본 발명은 단순한 공정에 의한 금속층간 절연막의 평탄화로 생산단가를 줄일 수 있고, SOG막으로 인한 문제점을 근본적으로 해결하여 소자의 신뢰성을 향상시킬 수 있으며, 또한 비아홀의 애스팩트비(aspect ratio)를 낮추어 후속 금속콘택공정시 스텝커버리지를 개선할 수 있다.Therefore, the present invention can reduce the production cost by the planarization of the interlayer insulating film by a simple process, fundamentally solve the problems caused by the SOG film, and improve the reliability of the device, and also the aspect ratio of the via hole. Step coverage can be improved in subsequent metal contact processes.
Claims (7)
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| KR1019950041456A KR0168164B1 (en) | 1995-11-15 | 1995-11-15 | Method of fabricating semiconductor device |
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