KR100241516B1 - Method of forming interlayer insulating film of semiconductor device - Google Patents
Method of forming interlayer insulating film of semiconductor device Download PDFInfo
- Publication number
- KR100241516B1 KR100241516B1 KR1019930027001A KR930027001A KR100241516B1 KR 100241516 B1 KR100241516 B1 KR 100241516B1 KR 1019930027001 A KR1019930027001 A KR 1019930027001A KR 930027001 A KR930027001 A KR 930027001A KR 100241516 B1 KR100241516 B1 KR 100241516B1
- Authority
- KR
- South Korea
- Prior art keywords
- silicon oxide
- film
- oxide film
- semiconductor device
- interlayer insulating
- Prior art date
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Abstract
본 발명은 반도체 소자의 층간 절연막을 형성하는 방법에 관한 것으로, 반도체 소자의 다층 금속배선 공정중 금속층간을 절연하는 층간 절연막으로 O3-TEOS(O3-Tetra Ethylene Ortho Silicate)막을 사용하여 평탄화 할때, 금속배선 공정이 완료된 반도체 소자상에 PECVD 방법으로 실리콘 산화막을 증착하고, 건식 방법으로 상기 PECVD 실리콘 산화막을 부분적으로 식각시키는 것에 의하여 PECVD 실리콘 산화막의 표면을 거칠게 만든후, 그 상부에 O3-TEOS 막을 증착하므로 O3-TEOS막의 실리콘 산화막에 대한 표면의존성을 제거시켜 보이드(Void) 발생과 같은 결함을 제거할 수 있는 반도체 소자의 층간 절연막을 형성하는 방법에 관해 기술된다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming an interlayer insulating film of a semiconductor device, and to planarize using an O 3 -TEOS (O 3 -Tetra Ethylene Ortho Silicate) film as an interlayer insulating film that insulates metal layers during a multilayer metallization process of a semiconductor device. When the silicon oxide film is deposited on the semiconductor device on which the metallization process is completed, the surface of the PECVD silicon oxide film is roughened by partially etching the PECVD silicon oxide film by a dry method, and then on the top of the O 3- . A method of forming an interlayer insulating film of a semiconductor device capable of removing defects such as void generation by removing the surface dependency of the O 3 -TEOS film on the silicon oxide film by depositing a TEOS film is described.
Description
제1(a)도 내지 제1(c)도는 본 발명에 의한 반도체 소자의 층간 절연막을 형성하는 단계를 설명하기 위해 도시한 단면도.1 (a) to 1 (c) are cross-sectional views for explaining the steps of forming an interlayer insulating film of a semiconductor device according to the present invention.
제2(a)도 내지 제2(c)도는 본 발명의 다른 실시예에 의한 반도체 소자의 층간 절연막을 형성하는 단계를 설명하기 위해 도시한 단면도.2 (a) to 2 (c) are cross-sectional views for explaining a step of forming an interlayer insulating film of a semiconductor device according to another embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 실리콘 기판 2 : BPSG막1: silicon substrate 2: BPSG film
3 : 금속배선 4, 4A, 4B : 실리콘 산화막3: metallization 4, 4A, 4B: silicon oxide film
5 : O3-TEOS 막 6 : 포토레지스트5: O 3 -TEOS film 6: photoresist
본 발명은 반도체 소자의 층간 절연막을 형성하는 방법에 관한 것으로, 특히 반도체 소자의 다층 금속배선 공정중 금속층간을 절연하는 층간 절연막으로 O3-TEOS(O3-Tetra Ethylene Ortho Silicate)막을 사용하여 평탄화 할때, 금속배선 공정이 완료된 반도체 소자상에 PECVD 방법으로 실리콘 산화막을 증착하고, 건식 방법으로 상기 PECVD 실리콘 산화막을 부분적으로 식각시키는 것에 의하여 PECVD 실리콘 산화막의 표면을 거칠게 만든후, 그 상부에 O3-TEOS 막을 증착하므로 O3-TEOS막의 실리콘 산화막에 대한 표면의존성을 제거시켜 보이드(Void) 발생과 같은 결함을 제거할 수 있는 반도체 소자의 층간 절연막을 형성하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an interlayer insulating film of a semiconductor device, and in particular, planarization using an O 3 -TEOS (O 3 -Tetra Ethylene Ortho Silicate) film as an interlayer insulating film that insulates metal layers during a multilayer metallization process of a semiconductor device. When the silicon oxide film is deposited on the semiconductor device on which the metallization process is completed, the surface of the PECVD silicon oxide film is roughened by partially etching the PECVD silicon oxide film by a dry method, and then on top of the O 3 layer. The present invention relates to a method of forming an interlayer insulating film of a semiconductor device capable of eliminating defects such as voids by removing surface dependence of the O 3 -TEOS film on the silicon oxide film.
일반적으로, 반도체 소자의 다층 금속배선 공정에서의 금속층간을 절연하는 절연막으로 O3-TEOS 막을 사용할때, 금속배선 상부에 PECVD 방법으로 실리콘 산화막을 증착하고 그 위에 O3-TEOS막을 직접 증착한다. 그러나 이 방법은 O3-TEOS막의 실리콘 산화막에 대한 표면 의존성 때문에 PECVD 실리콘 산화막의 증착조건에 따라 O3-TEOS막의 성질이 변할 수 있으며, 또한 금속배선의 폭이 좁아짐에 따라 금속배선사이에 보이드와 같은 결함을 유발시키는 문제점이 있다.In general, when an O 3 -TEOS film is used as an insulating film for insulating between metal layers in a multi-layer metallization process of a semiconductor device, a silicon oxide film is deposited by a PECVD method on the metallization, and an O 3 -TEOS film is directly deposited thereon. This method, however, since the surface-dependent O 3 -TEOS film on the silicon oxide film may change the O 3 -TEOS film properties depending on the deposition conditions of the PECVD silicon oxide film, and also the voids between the metal wire in accordance with the width of metal wiring is narrowed There is a problem that causes the same defect.
따라서, 본 발명은 상기의 문제점을 해결하기 위해, 금속배선 공정까지 완료된 반도체 소자 상부에 PECVD 방법으로 실리콘 산화막을 증착하고 건식방법으로 PECVD 실리콘 산화막을 일부분 식각시켜 PECVD 실리콘 산화막의 표면을 거칠게 만들어 주는것에 의하여 O3-TEOS막 증착시 생기는 실리콘 산화막에 대한 표면 의존성을 제거시켜 PECVD 산화막의 증착조건에 무관하고 좋은 성질을 갖으며 결함발생을 방지할 수 있도록 한 반도체 소자의 층간 절연막을 형성하는 방법을 제공하는데 그 목적이 있다.Therefore, in order to solve the above problems, the silicon oxide film is deposited on the semiconductor device completed up to the metallization process by PECVD, and the PECVD silicon oxide film is partially etched by the dry method to roughen the surface of the PECVD silicon oxide film. This method provides a method of forming an interlayer insulating film of a semiconductor device by removing the surface dependency on the silicon oxide film generated during the deposition of O 3 -TEOS film, thereby having a good property irrespective of the deposition conditions of the PECVD oxide film and preventing defects. Its purpose is to.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제1(a)도 내지 제1(c)도는 본 발명에 의한 반도체 소자의 층간 절연막을 형성하는 단계를 설명하기 위해 도시한 단면도로서, 제1(a)도는 소정의 단위셀(도시않음)이 형성된 실리콘 기판(1)상에 BPSG막(2)을 증착 평탄화한 상태에서, 다수의 금속배선(3)을 형성하고, 상기 다수의 금속배선(3)을 포함한 전체구조 상부에 PECVD방법으로 실리콘 산화막(4)을 증착한 상태를 도시한 것이다.1 (a) to 1 (c) are cross-sectional views for explaining the step of forming an interlayer insulating film of a semiconductor device according to the present invention, Figure 1 (a) is a predetermined unit cell (not shown) In the state where the BPSG film 2 is deposited and planarized on the formed silicon substrate 1, a plurality of metal wirings 3 are formed, and a silicon oxide film is formed on the entire structure including the plurality of metal wirings 3 by PECVD. The state which deposited (4) is shown.
제1(b)도는 상기 실리콘 산화막(4)을 건식식각방법으로 식각하여 표면 전체부분이 거친 실리콘 산화막(4A)을 형성한 상태를 도시한 것이다.FIG. 1 (b) shows a state in which the silicon oxide film 4 is etched by dry etching to form a silicon oxide film 4A having a coarse surface portion.
상기 실리콘 산화막(4)의 표면을 거칠게하기 위하여 건식식각방법대신 N2, NH3, Ar 플라즈마를 이용하는 방법, HF 또는 습식식각방법을 사용할 수 있다.In order to roughen the surface of the silicon oxide film 4, a method using N 2 , NH 3 , Ar plasma, HF or wet etching may be used instead of the dry etching method.
제1(c)도는 상기 표면이 거친 실리콘 산화막(4A) 상부에 층간 절연막으로 O3-TEOS막(5)을 증착하므로 O3-TEOS막(5)의 실리콘 산화막(4)에 대한 표면 의존성을 제거시킬 수 있다.Claim 1 (c) to turn the surface dependent on the silicon oxide film 4 of the O 3 -TEOS film 5 so depositing the O 3 -TEOS film 5, the interlayer insulating film on the upper coarse silicon oxide film (4A) the surface Can be removed.
제2(a)도 내지 제2(c)도는 본 발명의 다른 실시예를 도시한 것으로, 상술한 제1(a)도 내지 제1(c)도의 공정단계를 참조하되, 제2(b)도에 도시한 바와같이 다수의 금속배선(3)을 포함한 전체구조 상부에 실리콘 산화막(4)을 증착한 상태에서, 상기 다수의 금속배선(3) 상부에 패턴화된 포토레지스트(6)를 위치시켜, 이 패턴화된 포토레지스트(6)를 이용한 건식식각방법으로 실리콘 산화막(4)을 식각하여 금속배선(3) 측면과 하부의 BPSG막(2) 상부면의 실리콘 산화막(4)의 표면이 거친 실리콘 산화막(4B)을 형성한다.2 (a) to 2 (c) show another embodiment of the present invention, referring to the above-described process steps of FIGS. 1 (a) to 1 (c), wherein the second (b) As shown in the figure, the patterned photoresist 6 is positioned on the plurality of metal wires 3 while the silicon oxide film 4 is deposited on the entire structure including the plurality of metal wires 3. Then, the silicon oxide film 4 is etched by the dry etching method using the patterned photoresist 6 so that the surface of the silicon oxide film 4 on the side of the metal wiring 3 and the upper surface of the BPSG film 2 on the lower side is etched. A rough silicon oxide film 4B is formed.
상기 공정후 제2(c)도에 도시된 바와같이 표면이 거친 실리콘 산화막(4B) 상부에 층간 절연막으로 O3-TEOS막(5)을 증착, 평탄화한다.After the above process, as shown in FIG. 2 (c), the O 3 -TEOS film 5 is deposited and planarized on the roughened silicon oxide film 4B as an interlayer insulating film.
상술한 바와같이 본 발명에 의하면 층간 절연막으로서 O3-TEOS 증착전 금속배선 상부에 형성된 PECVD 실리콘 산화막을 식각방법에 의해 표면을 거칠게 한 후 O3-TEOS를 증착하므로써, O3-TEOS의 PECVD 실리콘 산화막에 대한 표면 의존성을 제거시켜 보이드와 같은 결함 발생을 제거하며, 또한 PECVD 실리콘 산화막의 표면이 거칠기 때문에 O3-TEOS 증착속도가 증가되어 평탄도가 향상된다.By, according to the present invention deposited the O 3 -TEOS deposited before the upper metal line O 3 -TEOS after roughening the surface by a PECVD silicon oxide film formed on the etching method as an interlayer insulation film, as described above, the O 3 -TEOS PECVD silicon The surface dependency on the oxide film is removed to eliminate defects such as voids, and because the surface of the PECVD silicon oxide film is rough, the O 3 -TEOS deposition rate is increased to improve flatness.
Claims (3)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019930027001A KR100241516B1 (en) | 1993-12-09 | 1993-12-09 | Method of forming interlayer insulating film of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019930027001A KR100241516B1 (en) | 1993-12-09 | 1993-12-09 | Method of forming interlayer insulating film of semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
KR950021354A KR950021354A (en) | 1995-07-26 |
KR100241516B1 true KR100241516B1 (en) | 2000-03-02 |
Family
ID=66850449
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019930027001A KR100241516B1 (en) | 1993-12-09 | 1993-12-09 | Method of forming interlayer insulating film of semiconductor device |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR100241516B1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100657149B1 (en) | 2005-11-15 | 2006-12-13 | 동부일렉트로닉스 주식회사 | Semiconductor device and manufacturing method therof |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100416696B1 (en) * | 1996-10-01 | 2004-03-26 | 주식회사 하이닉스반도체 | Method for planarizing semiconductor device |
-
1993
- 1993-12-09 KR KR1019930027001A patent/KR100241516B1/en not_active IP Right Cessation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100657149B1 (en) | 2005-11-15 | 2006-12-13 | 동부일렉트로닉스 주식회사 | Semiconductor device and manufacturing method therof |
Also Published As
Publication number | Publication date |
---|---|
KR950021354A (en) | 1995-07-26 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR950002948B1 (en) | Insulating film forming method between the metal layer of semiconductor device | |
KR19980086535A (en) | How to prevent copper contamination of integrated circuit structures | |
KR100241516B1 (en) | Method of forming interlayer insulating film of semiconductor device | |
US20020055202A1 (en) | Method for forming a dielectric layer in a semiconductor device by using etch stop layers | |
US6399482B1 (en) | Method and structure for a conductive and a dielectric layer | |
KR100664339B1 (en) | Method for forming metal line of semiconductor device | |
KR0168164B1 (en) | Method of fabricating semiconductor device | |
US6709975B2 (en) | Method of forming inter-metal dielectric | |
KR19980025403A (en) | Planarization Method of Semiconductor Device | |
KR100427539B1 (en) | Method of forming multilayer metal of semiconductor device using improved intermetal dielectric | |
KR100198636B1 (en) | Interconnecting method of semiconductor device | |
KR100668961B1 (en) | Method of fabricating metal-insulator-metal capacitor | |
KR100458078B1 (en) | Method for forming metal interconnection of semiconductor device to reduce em phenomenon and leakage current | |
KR0166826B1 (en) | Method of interlayer insulating film in a semiconductor device | |
KR0167282B1 (en) | Method for forming multilayer interconnection | |
JPH0669154A (en) | Through hole structure and its manufacture | |
KR100399901B1 (en) | Method for forming intermetal dielectric of semiconductor device | |
KR100546296B1 (en) | Method of manufacturing metal line preventing metal bridge for semiconductor device | |
KR100410810B1 (en) | Method for forming multilayer metal line of semiconductor device | |
KR100406740B1 (en) | Formation method of inter metal dielectric layer in semiconductor device | |
KR100277867B1 (en) | Method for forming metal line of semiconductor device | |
KR100315849B1 (en) | a forming method of a contact for multi-level interconnects | |
KR0179006B1 (en) | Method of manufacturing dielectric membrane between metals | |
KR970005683B1 (en) | Metal wiring method in semiconductor device | |
KR100253338B1 (en) | Method for forming wire of semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20101025 Year of fee payment: 12 |
|
LAPS | Lapse due to unpaid annual fee |