KR0161458B1 - Planerizing method of semiconductor device - Google Patents
Planerizing method of semiconductor device Download PDFInfo
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- KR0161458B1 KR0161458B1 KR1019950042619A KR19950042619A KR0161458B1 KR 0161458 B1 KR0161458 B1 KR 0161458B1 KR 1019950042619 A KR1019950042619 A KR 1019950042619A KR 19950042619 A KR19950042619 A KR 19950042619A KR 0161458 B1 KR0161458 B1 KR 0161458B1
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Abstract
본 발명은 반도체장치의 층간절연막 평탄화 방법에 관한 것으로, 경사진 표면을 갖는 절연막이 형성된 반도체기판 상에 하부 금속막 패턴을 형성하는 단계; 상기 하부 금속막 패턴이 형성된 반도체기판 전면에 제1 층간절연막 및 제2 층간절연막을 차례로 형성하는 단계; 상기 제2 층간절연막이 형성된 반도체기판 전면에 평탄화물질층을 형성하는 단계; 상기 제2 층간절연막을 식각 저지막으로하여 상기 평탄화 물질층을 건식식각 방법으로 전면 에치백함으로써 상기 하부 금속막 패턴 상부의 제2 층간절연막을 노출시키는 단계; 및 상기 결과물 전면에 제3 층간절연막을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체장치의 층간절연막 평탄화 방법을 제공한다. 본 발명에 의하면, 하부 금속막 패턴 상부의 제2 층간절연막이 모두 노출될 때까지 평탄화 물질층을 에치백할 수 있으므로 하부 금속막 패턴 표면에 식각손상이 가해지는 문제점을 제거할 수 있다.The present invention relates to a method of planarizing an interlayer insulating film of a semiconductor device, comprising: forming a lower metal film pattern on a semiconductor substrate on which an insulating film having an inclined surface is formed; Sequentially forming a first interlayer insulating film and a second interlayer insulating film on an entire surface of the semiconductor substrate on which the lower metal film pattern is formed; Forming a planarization material layer on an entire surface of the semiconductor substrate on which the second interlayer insulating film is formed; Exposing the second interlayer dielectric layer on the lower metal layer pattern by etching the entire planarization material layer by dry etching using the second interlayer dielectric layer as an etch stop layer; And forming a third interlayer insulating film on the entire surface of the resultant product. According to the present invention, the planarization material layer can be etched back until all of the second interlayer insulating film on the lower metal film pattern is exposed, thereby eliminating the problem of etching damage on the surface of the lower metal film pattern.
Description
제1도 내지 제4도는 종래기술에 의한 층간절연막의 평탄화 방법을 설명하기 위한 단면도들이다.1 to 4 are cross-sectional views illustrating a planarization method of an interlayer insulating film according to the prior art.
제5도 내지 제8도는 본 발명에 의한 층간절연막의 평탄화 방법을 설명하기 위한 단면도들이다.5 to 8 are cross-sectional views illustrating a planarization method of an interlayer insulating film according to the present invention.
본 발명은 반도체장치의 층간절연막 평탄화 방법에 관한 것으로, 특히 다층 구조의 금속막을 갖는 반도체장치에 있어서 금속막 사이의 층간절연막을 평탄화시키는 방법에 관한 것이다.The present invention relates to a method of planarizing an interlayer insulating film of a semiconductor device, and more particularly to a method of planarizing an interlayer insulating film between metal films in a semiconductor device having a metal film of a multi-layer structure.
최근 반도체장치의 집적도가 증가하고 그 동작속도가 빨라지면서 금속배선 공정이 매우 중요시 되고 있다. 이는 금속배선이 반도체장치의 소자들, 예컨대 트랜지스터들을 서로 연결시키어 전기적인 신호를 전달하는 수단으로 사용되며, 이러한 금속배선의 배치가 집적도와 매우 밀접한 관계가 있기 때문이다. 다시 말해서, 동일한 면적 내에 많은 금속배선을 효율적으로 배치함으로써 집적도를 증가시킬 수 있고, 이와 아울러 신호의 전달시간을 빠르게 할 수 있기 때문이다. 따라서, 금속배선을 효율적으로 배치하기 위해서 2층 이상의 금속막을 사용하는 공정이 널리 사용되고 있다. 이때, 상부의 금속배선과 하부의 금속배선을 전기적으로 서로 분리시키고 상부 금속배선의 패턴을 용이하게 형성하기 위해서는 평탄도가 우수한 층간절연막을 형성하여야 한다. 또한, 상/하부의 금속배선을 전기적으로 서로 연결시키기 위해서는 상기 층간절연막의 소정부분을 식각하여 콘택홀, 즉 비아홀을 형성하여야 한다. 이와 같이 층간절연막은 상부 금속배선의 패턴 및 비아홀 형성과 밀접한 관계가 있다.Recently, as the degree of integration of semiconductor devices has increased and the operation speed thereof has increased, the metallization process has become very important. This is because metal wiring is used as a means for transmitting electrical signals by connecting elements of semiconductor devices, such as transistors, to each other, and the arrangement of such metal wiring is closely related to the degree of integration. In other words, by efficiently arranging a large number of metal wires in the same area, the degree of integration can be increased, and the signal transfer time can be increased. Therefore, in order to arrange metal wiring efficiently, the process of using two or more metal films is widely used. In this case, in order to electrically separate the upper metal wiring and the lower metal wiring from each other and easily form the pattern of the upper metal wiring, an interlayer insulating film having excellent flatness should be formed. In addition, in order to electrically connect the upper and lower metal wires to each other, a predetermined portion of the interlayer insulating layer must be etched to form contact holes, that is, via holes. As such, the interlayer insulating film is closely related to the pattern of the upper metal wiring and the via hole formation.
제1도 내지 제4도는 종래기술에 의한 층간절연막 평탄화 방법을 설명하기 위한 단면도들이다.1 to 4 are cross-sectional views illustrating a method of planarizing an interlayer insulating film according to the prior art.
제1도는 하부 금속막 패턴(5a, 5b, 5c)을 형성하는 단계를 도시한 것이다. 먼저, 반도체기판(1)의 전면에 형성된 경사진 절연층(3)의 전면에 금속막, 예컨대 알루미늄막을 형성한다. 다음에, 상기 금속막을 통상의 사진/식각 공정으로 패터닝하여 하부 금속막 패턴(5a, 5b, 5c)을 형성한다. 이때, 상기 절연층(3)의 표면이 높은 부분과 낮은 부분에 각각 하부 금속막 패턴(5a)와 하부 금속막 패턴(5b, 5c)가 형성된다.FIG. 1 illustrates the steps of forming the lower metal film patterns 5a, 5b, and 5c. First, a metal film, for example, an aluminum film is formed on the entire surface of the inclined insulating layer 3 formed on the entire surface of the semiconductor substrate 1. Next, the metal film is patterned by a conventional photo / etch process to form lower metal film patterns 5a, 5b, and 5c. In this case, the lower metal film patterns 5a and the lower metal film patterns 5b and 5c are formed at portions of the upper and lower portions of the insulating layer 3, respectively.
제2도는 제1층간절연층(7) 및 평탄화 물질층(9)을 형성하는 단계를 도시한 것이다. 구체적으로 상기 하부 금속막 패턴(5a,5b,5c)이 형성된 반도체기판 전면에 제1층간 절연층(7)을 형성한다. 여기서, 상기 제1층간 절연층(7)으로는 얇은 TEOS 산화막이 널리 사용되며, 이러한 TEOS 산화막은 상기 하부 금속막 패턴(5a, 5b, 5c)에 의해 형성된 표면 요철을 그대로 유지하면서 형성된다. 이어서, 평면요철을 갖는 상기 제1층간 절연층(7) 전면에 평탄화 물질층(9), 예컨대 SOG(spin on glass)를 도포한다. 이때, 도시된 바와 같이 상기 평탄화 물질층(9), 즉 SOG는 액상이므로 상기 하부 금속막 패턴(5a, 5b, 5c) 사이의 요부를 채우면서 굴곡이 완화된 표면을 갖는다. 따라서, 상기 절연층(3)의 단차에 의해 높은 부분에 형성된 하부 금속막 패턴(5a) 상부의 평탄화 물질층(9)은 그 두께가 얇게 형성되며, 낮은 부분에 형성된 하부 금속막 패턴(5b, 5c) 상부의 평탄화 물질층(9)은 그 두께가 두껍게 형성된다.2 shows the steps of forming the first interlayer insulating layer 7 and the planarization material layer 9. Specifically, the first interlayer insulating layer 7 is formed on the entire surface of the semiconductor substrate on which the lower metal film patterns 5a, 5b, and 5c are formed. Here, a thin TEOS oxide film is widely used as the first interlayer insulating layer 7, and the TEOS oxide film is formed while maintaining the surface irregularities formed by the lower metal film patterns 5a, 5b, and 5c. Subsequently, a planarization material layer 9, for example, spin on glass (SOG), is applied to the entire surface of the first interlayer insulating layer 7 having planar irregularities. In this case, the planarization material layer 9, that is, SOG is a liquid phase, so as to fill the recesses between the lower metal layer patterns 5a, 5b, and 5c, and have a curved surface. Accordingly, the planarization material layer 9 on the lower metal film pattern 5a formed on the high portion due to the step of the insulating layer 3 has a thin thickness, and the lower metal film pattern 5b, formed on the lower portion, 5c) The upper planarization material layer 9 is formed to have a thick thickness.
제3도는 에치백된 평탄화 물질층(9a) 및 제2 층간절연층(11)을 형성하는 단계를 도시한 것이다. 좀 더 상세히, 상기 평탄화 물질층(9)을 전면 에치백하여 전체적으로 얇은 두께를 갖는 에치백된 평탄화 물질층(9a)를 형성한다. 이와 같이 상기 평탄화 물질층(9)을 전면 에치백하는 이유는 후속공정시 하부 금속막 패턴(5a, 5b, 5c) 상에 최소한의 두께를 갖는 층간절연막을 형성함으로써 상기 하부 금속막 패턴을 노출시키기 위한 콘택홀 형성시 그 종횡비를 낮추기 위함이다. 이때, 상기 평탄화 물질층(9)을 너무 많이 에치백하게 되면 도시된 바와 같이 높은 부위에 형성된 하부 금속막 패턴(5a) 상부의 제1 충간절연막(7)이 함께 삭각되어 제1 층간절연막(7a)이 형성되고 하부 금속막 패턴(5a) 표면이 노출된다. 따라서, 하부 금속막 패턴(5a) 표면이 식각손상을 입게된다. 이러한 식각손상은 하부 금속막 패턴(5a) 표면에 다중합체(polymer)와 같은 원치않는 물질을 형성시키어 차후 상기 노출된 하부 금속막 패턴(5a) 상에 콘택홀을 형성할 때 그 표면이 완전히 노출되지 않을 수 있다. 결과적으로, 하부 금속막 패턴(5a)와 이와 접촉하는 상부 금속막 패턴(도시하지 않음)과의 접촉저항이 증가하는 문제점이 발생한다. 반면에, 상기 평탄화 물질층(9)을 너무 조금 에치백하게 되면 낮은 부분에 형성된 상기 하부 금속막 패(5b,5c) 상부에 두꺼운 에치백된 평탄화 물질층(9a)이 남는 문제가 발생한다. 이와 같이 평탄화 물질층(9)을 적절히 에치백하지 않으면 후속공정에서 원하는 콘택홀을 형성하기가 어려운 문제점을 발생시킨다.3 shows the steps of forming the etched back planarization material layer 9a and the second interlayer dielectric layer 11. In more detail, the planarization material layer 9 is entirely etched back to form an etched planarization material layer 9a having an overall thin thickness. The reason why the entire surface of the planarization material layer 9 is etched back is to expose the lower metal layer pattern by forming an interlayer insulating layer having a minimum thickness on the lower metal layer patterns 5a, 5b, and 5c in a subsequent process. This is to lower the aspect ratio when forming a contact hole. At this time, if the planarization material layer 9 is etched back too much, the first interlayer insulating film 7 on the lower metal film pattern 5a formed on the high portion is cut together, as shown in the drawing, and thus the first interlayer insulating film 7a. ) Is formed and the surface of the lower metal film pattern 5a is exposed. Therefore, the surface of the lower metal film pattern 5a is etched. This etching damage forms an unwanted material such as a polymer on the surface of the lower metal film pattern 5a so that the surface is completely exposed when a contact hole is formed on the exposed lower metal film pattern 5a. It may not be. As a result, a problem arises in that the contact resistance between the lower metal film pattern 5a and the upper metal film pattern (not shown) in contact therewith increases. On the other hand, if the planarization material layer 9 is etched back too little, a problem occurs that a thick etched back planarization material layer 9a remains on the lower metal film pads 5b and 5c formed at the lower portion. As such, if the planarization material layer 9 is not etched back properly, it is difficult to form a desired contact hole in a subsequent process.
이어서, 상기 에치백된 평탄화 물질층(9a)이 형성된 반도체기판 전면에 제2 층간절연막(11), 예컨대 TEOS 산화막을 형성한다.Subsequently, a second interlayer insulating film 11, eg, a TEOS oxide film, is formed on the entire surface of the semiconductor substrate on which the etched back planarization material layer 9a is formed.
제4도는 상기 하부 금속막 패턴(5a, 5b) 상에 콘택홀을 형성하는 단계를 도시한 것이다. 먼저, 상기 제2 층간절연막(11) 상에 상기하부 금속막 패턴(5a, 5b)의 상부의 제2 층간절연막(11)을 노출시키는 감광막 패턴(도시하지 않음)을 형성한다. 다음에, 상기 감광막 패턴을 식각마스크로하여 상기 제2 층간절연막(11)의 일부를 습식식각한 후, 계속해서 상기 제2 층간절연막(11), 상기 에치백된 평탄화 물질층(9a) 및 상기 제1 층간절연막 패턴(7a)을 연속적으로 이방성식각하여 상기 하부 금속막 패턴(5a, 5b) 표면을 노출시키는 콘택홀을 형성함과 동시에 제2 층간절연막 패턴(11a), 평탄화 물질층 패턴(9b) 및 제1층 층간절연막 패턴(7b)를 형성한다. 이때, 상기 콘택홀의 윗부분은 도시된 바와 같이 습식식각공정에 의해 경사진 측벽을 갖게 된다. 이러한 경사진 측벽을 형성하는 목적은 상기 콘택홀의 종횡비를 낮추는 효과를 얻기 위함이다. 이와 같이 종횡비를 낮추게 되면 차후 콘택홀을 덮는 상부 금속막(도시하지 않음) 형성시 단차도포성(step coverage)이 좀 더 개선되어 결과적으로 상부 금속막의 신뢰성이 개선된다. 여기서, 낮은 부분에 형성된 하부 금속막 패턴(5b) 상부에 종횡비가 더욱 낮은 콘택홀을 형성하기 위하여 상기 등방성 식각을 과도하게 실시하면 높은 부분에 형성된 하부 금속막 패턴(5a)이 노출되면서 콘택홀의 가장자리가 하부 금속막 패턴(5a) 옆에 까지 확장될 수 있다. 반면에, 이러한 현상을 방지하기 위하여 상기 등방성 식각을 불충분하게 실시하게 되면 낮은 부분에 형성된 하부 금속막 패턴(5b) 상부에 남는 평탄화 물질층 패턴(9b) 및 제2 절연막 패턴(11a)의 두께가 커지게 되므로 상기 이방성 식각에 의해 형성되는 홀의 깊이가 증가하게 된다. 따라서, 콘택홀의 종횡비가 커지므로 후속공정에서 상기 콘택홀을 덮는 상부 금속막 형성시 단차도포성이 매우 불량하게 된다. 결과적으로, 상기 등방성 식각공정을 최적화시키기가 어려운 문제점이 발생한다.4 illustrates forming contact holes on the lower metal layer patterns 5a and 5b. First, a photosensitive film pattern (not shown) is formed on the second interlayer insulating film 11 to expose the second interlayer insulating film 11 on the lower metal film patterns 5a and 5b. Next, after wet etching a part of the second interlayer insulating film 11 using the photoresist pattern as an etch mask, the second interlayer insulating film 11, the etched back planarization material layer 9a, and the By continuously anisotropically etching the first interlayer insulating film pattern 7a to form contact holes exposing the surfaces of the lower metal film patterns 5a and 5b, the second interlayer insulating film pattern 11a and the planarization material layer pattern 9b. And the first interlayer insulating film pattern 7b. At this time, the upper portion of the contact hole has a side wall inclined by a wet etching process as shown. The purpose of forming the inclined sidewall is to obtain an effect of lowering the aspect ratio of the contact hole. As such, when the aspect ratio is lowered, step coverage is further improved when the upper metal film (not shown) covering the contact hole is subsequently formed, thereby improving reliability of the upper metal film. Here, when the isotropic etching is excessively performed to form a contact hole with a lower aspect ratio on the lower metal film pattern 5b formed in the lower portion, the lower metal film pattern 5a formed in the high portion is exposed and the edge of the contact hole is exposed. May extend to the side of the lower metal film pattern 5a. On the other hand, if the isotropic etching is insufficient to prevent such a phenomenon, the thicknesses of the planarization material layer pattern 9b and the second insulating layer pattern 11a remaining on the lower metal layer pattern 5b formed on the lower portion may be reduced. As it becomes larger, the depth of the hole formed by the anisotropic etching is increased. Therefore, since the aspect ratio of the contact hole increases, the step coating property is very poor in forming the upper metal film covering the contact hole in a subsequent process. As a result, a problem arises that it is difficult to optimize the isotropic etching process.
상술한 바와 같이, 종래의 층간절연막 평탄화 방법은 평탄화 물질층을 적절히 에치백하기가 어려운 문제점이 있다. 따라서, 에치백이 과도하게 진행된 경우 높은 부분에 형성된 하부 금속막 패턴이 노출되어 그 표면에 식각손상이 가해진다. 이러한 식각손상이 가해진 하부 금속막 패턴 표면에 콘택홀을 형성할 경우 그 표면에 식각손상에 의해 형성된 다중합체에 의해 콘택저항을 증가시키는 문제점이 발생한다.As described above, the conventional interlayer insulating film planarization method has a problem that it is difficult to properly etch back the planarization material layer. Therefore, when the etch back is excessively progressed, the lower metal film pattern formed at the high portion is exposed, and etch damage is applied to the surface thereof. When the contact hole is formed on the surface of the lower metal layer pattern to which the etch damage is applied, a problem arises in that the contact resistance is increased by the polypolymer formed by the etch damage on the surface.
또한, 높은 부분과 낮은 부분에 각각 형성된 하부 금속막 패턴 상부에 평탄화 물질층 패턴 및 제2 층간절연막의 두께가 서로 다르게 형성되어 일정한 깊이의 콘택홀을 형성하기 어려운 문제점이 발생한다.In addition, since the thicknesses of the planarization material layer pattern and the second interlayer insulating layer are formed differently on the lower metal layer patterns respectively formed on the high and low portions, it is difficult to form contact holes having a constant depth.
따라서, 본 발명의 목적은 하부 금속막 패턴 상부에 하부 금속막 패턴을 보호하기 위한 질화막 계열의 제2 층간절연막을 형성하여 평탄화 물질층을 에치백할 때 하부 금속막 패턴에 식각손상이 가해지는 현상을 방지할 수 있음은 물론, 일정깊이의 콘택홀을 형성시킬 수 있는 반도체장치의 층간절연막 평탄화 방법을 제공하는 데 있다.Accordingly, an object of the present invention is to form an nitride layer-based second interlayer insulating layer on the lower metal layer pattern to etch back the planarization material layer to etch back the lower metal layer pattern. The present invention provides a method for planarizing an interlayer insulating film of a semiconductor device, which can prevent the defects and can form contact holes having a predetermined depth.
상기 목적을 달성하기 위하여 본 발명은, 경사진 표면을 갖는 절연막이 형성된 반도체기판 상에 하부 금속막 패턴을 형성하는 단계; 상기 하부 금속막 패턴이 형성된 반도체기판 전면에 제1 층간절연막 및 제2 층간절연막을 차례로 형성하는 단계; 상기 제2 층간절연막이 형성된 반도체기판 전면에 평탄화물질층을 형성하는 단계; 상기 하부 금속막 패턴 상부의 제2 층간절연막이 노출되도록 상기 평탄화 물질층을 전면 에치백하는 단계; 및 상기 결과물 전면에 제3 층간절연막을 형성하는 단계를 포함하는것을 특징으로 하는 반도체장치의 층간절연막 평탄화 방법을 제공한다.In order to achieve the above object, the present invention comprises the steps of forming a lower metal film pattern on a semiconductor substrate having an insulating film having an inclined surface; Sequentially forming a first interlayer insulating film and a second interlayer insulating film on an entire surface of the semiconductor substrate on which the lower metal film pattern is formed; Forming a planarization material layer on an entire surface of the semiconductor substrate on which the second interlayer insulating film is formed; Etching the entire surface of the planarization material layer to expose the second interlayer insulating layer on the lower metal layer pattern; And forming a third interlayer insulating film on the entire surface of the resultant product.
이하, 첨부도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제5도 내지 제8도는 본 발명의 바람직한 실시예를 설명하기 위한 단면도들이다.5 to 8 are cross-sectional views for describing a preferred embodiment of the present invention.
제5도는 하부 금속막 패턴(25,25b,25c)을 형성하는 단계를 도시한 것이다. 먼저, 반도체기판(21)의 전면에 형성된 경사진 절연층(23)의 전면에 금속막, 예컨대 알루미늄막을 형성한다. 다음에, 상기 금속막을 통상의 사진/식각 공정으로 패터닝하여 하부 금속막 패턴(25, 25b, 25c)을 형성한다. 이때, 상기 절연층(23)의 표면이 높은 부분과 낮은 부분에 각각 하부 금속막 패턴(25)와 하부 금속막 패턴(25b, 25c)가 형성된다.5 illustrates forming the lower metal layer patterns 25, 25b and 25c. First, a metal film, for example, an aluminum film is formed on the front surface of the inclined insulating layer 23 formed on the front surface of the semiconductor substrate 21. Next, the metal film is patterned by a conventional photo / etch process to form lower metal film patterns 25, 25b and 25c. In this case, the lower metal film patterns 25 and the lower metal film patterns 25b and 25c are formed on the high and low portions of the insulating layer 23, respectively.
제6도는 제1 층간절연막(27), 제2 층간절연막(29), 및 평탄화 물질층(31)을 형성하는 단계를 도시한 것이다. 구체적으로, 상기 하부 금속막 패턴(25, 25b, 25c)이 형성된 반도체기판 전면에 제1 층간절연막(27) 및 제2 층간절연막(29)을 차례로 형성한다. 여기서, 상기 제1 층간절연막(27) 및 제2 층간절연막(29)은 각각 얇은 PE-TEOS산화막(plasma enhanced TEOS oxide film)과 얇은 실리콘 질화막으로 형성하는 것이 가장 바람직하다. 이때, 상기 제1 층간절연막(27) 및 제2 층간절연막(29)은 상기 하부 금속막 패턴(25, 25b, 25c)의 표면요철을 따라 형성되므로 서로 인접한 하부 금속막 패턴(25, 25b, 25c) 사이의 공간을 채우지 못한다. 따라서, 상기 결과물 전면에 평탄도가 우수한 평탄화 물질층(31), 예컨대 액상의 SOG막을 도포하여 서로 인접한 하부 금속막 패턴 사이의 공간을 채우면서 평탄화된 표면을 형성한다. 다음에, 상기 평탄화 물질층(31), 즉 액상의 SOG막을 300℃내지 450℃ 사이의 적정온도에서 베이킹함으로써, 그 내부에 함유된 용매를 증발시키어 고체상태의 산화막으로 변형된 평탄화 물질층(31)을 형성한다.FIG. 6 illustrates the steps of forming the first interlayer insulating film 27, the second interlayer insulating film 29, and the planarization material layer 31. Specifically, the first interlayer insulating layer 27 and the second interlayer insulating layer 29 are sequentially formed on the entire surface of the semiconductor substrate on which the lower metal layer patterns 25, 25b, and 25c are formed. The first interlayer dielectric layer 27 and the second interlayer dielectric layer 29 may be formed of a thin PE-TEOS oxide film and a thin silicon nitride layer, respectively. In this case, since the first interlayer insulating layer 27 and the second interlayer insulating layer 29 are formed along the surface irregularities of the lower metal layer patterns 25, 25b and 25c, the lower metal layer patterns 25, 25b and 25c adjacent to each other. Cannot fill the space between Therefore, a flattening material layer 31 having excellent flatness, for example, a liquid SOG film, is applied to the entire surface of the resultant to form a planarized surface while filling a space between adjacent lower metal film patterns. Next, the planarization material layer 31, that is, the liquid SOG film is baked at an appropriate temperature between 300 ° C. and 450 ° C., so that the solvent contained therein is evaporated to deform into a solid oxide film 31. ).
제7도는 에치백된 평탄화 물질층(31a) 및 제3 층간절연막(33)을 형성하는 단계를 도시한 것이다. 좀 더 상세히, 상기 하부 금속막 패턴(5, 5b, 5c) 상부의 제2 층간절연막(29)이 노출되도록 상기 평탄화 물질층(31)을 전면 에치백하여 평탄화 물질층 패턴(31a)을 형성한다. 이때, 도시된 바와 같이 상기 평탄화 물질층 패턴(31a)은 상기 하부 금속막 패턴(25, 25b, 25c)들 사이의 공간에만 잔존하며, 상기 노출된 제2 층간절연막(29)은 식각되지 않는다. 이는, 상기 평탄화 물질층(31)을 에치백할 때 상기 제2 층간절연막(29)에 대한 식각률을 작게 조절함으로써 상기 제2 층간절연막(29)이 식각저지막 역할을 하기 때문이다. 따라서, 상기 금속막 패턴(25, 25b, 25c)은 식각손상을 입지 않도록 보호되어진다. 다음에, 상기 평탄화 물질층 패턴(31a)이 형성된 반도체기판 전면에 제3 층간절연막(33), 예컨대 PE-TEOS 산화막을 형성한다.FIG. 7 illustrates the steps of forming the etched back planarization material layer 31a and the third interlayer insulating film 33. In more detail, the planarization material layer pattern 31a is formed by etching the entire surface of the planarization material layer 31 so that the second interlayer insulating layer 29 on the lower metal layer patterns 5, 5b and 5c is exposed. . In this case, the planarization material layer pattern 31a remains only in the space between the lower metal layer patterns 25, 25b and 25c, and the exposed second interlayer insulating layer 29 is not etched. This is because the second interlayer insulating layer 29 serves as an etch stop layer by controlling the etch rate with respect to the second interlayer insulating layer 29 to be small when the planarization material layer 31 is etched back. Therefore, the metal film patterns 25, 25b, and 25c are protected from etching damage. Next, a third interlayer insulating film 33, for example, a PE-TEOS oxide film, is formed on the entire surface of the semiconductor substrate on which the planarization material layer pattern 31a is formed.
제8도는 콘택홀을 형성하는 단계를 도시한 것으로, 먼저 상기 하부 금속막 패턴(25, 25b) 상부의 제3 층간절여막(33)이 노출되도록 포토레지스트 패턴(도시하지 않음)을 형성하다. 이어서 상기 포토레지스트 패턴을 식각 마스크로하여 상기 노출된 제3 층간절연막(33)을 등방성 식각, 예컨대 습식식각함으로써 경사진 개구부를 형성함과 동시에 제3 층간절연막 패턴(33a)을 형성한다. 이때, 상기 하부 금속막 패턴(25, 25b) 상부의 제2 층간절연막(29)이 노출될때까지 상기 등방성식각을 충분히 실시할 수 도 있다. 다음에, 상기 하부 금속막 패턴(25a, 25b) 상부에 잔존하는 제3 층간절연막 패턴(33a), 제2 층간절연막(29) 및 제1 층간절연막(27)을 이방성 식각하여 상기 하부 금속막 패턴(25a, 25b)을 노출시키는 콘택홀을 형성함과 동시에 제2 층간절연막 패턴(29a) 및 제1 층간절연막 패턴(27a)을 형성한다. 이와 같이 형성된 콘택홀은 도시된 바와 같이 모든 부분에서 일정 크기의 직경과 깊이를 갖는다.FIG. 8 illustrates a step of forming a contact hole. First, a photoresist pattern (not shown) is formed to expose the third interlayer thin film 33 on the lower metal layer patterns 25 and 25b. Subsequently, an inclined opening is formed by isotropic etching (eg, wet etching) the exposed third interlayer insulating layer 33 using the photoresist pattern as an etching mask, and at the same time, a third interlayer insulating layer pattern 33a is formed. In this case, the isotropic etching may be sufficiently performed until the second interlayer insulating layer 29 on the lower metal layer patterns 25 and 25b is exposed. Next, anisotropic etching of the third interlayer insulating layer pattern 33a, the second interlayer insulating layer 29, and the first interlayer insulating layer 27 remaining on the lower metal layer patterns 25a and 25b is performed to form the lower metal layer pattern. While forming contact holes exposing the portions 25a and 25b, a second interlayer insulating film pattern 29a and a first interlayer insulating film pattern 27a are formed. The contact hole thus formed has a diameter and depth of a predetermined size in all portions as shown.
상술한 본 발명의 실시예에 의하면, 하부 금속막 패턴을 둘러싸는 질화막 계열의 제2 층간절연막을 형성함으로써 평탄화 물질층을 에치백할때 하부 금속막 패턴이 노출되는 현상을 방지할 수 있으므로 그 표면에 식각손상이 가해지는 문제점을 제거할 수 있다. 또한, 하부 금속막 패턴상에 콘택홀을 형성하기 위하여 최상부에 형성된 제3 층간절연막을 습식식각할 때 제2 층간절연막이 식각저지막 역할을 하므로 모든 콘택홀을 동일한 크기로 형성할 수 있다. 따라서, 다층 금속배선 구조를 갖는 반도체장치를 제조함에 있어서 금속배선 구조를 갖는 반도체장치를 제조함에 있어서 금속배선 및 콘택저항의 신뢰성을 크게 개선시킬 수 있다.According to the above-described embodiment of the present invention, the second metal interlayer insulating film surrounding the lower metal film pattern is formed to prevent the lower metal film pattern from being exposed when the planarization material layer is etched back. Eliminates the problem of etching damage to the. In addition, when the third interlayer insulating layer formed on the uppermost portion of the lower metal layer pattern is wet-etched, the second interlayer insulating layer serves as an etch stop layer, and thus all contact holes may be formed to have the same size. Therefore, in manufacturing a semiconductor device having a multi-layer metal wiring structure, it is possible to greatly improve the reliability of the metal wiring and contact resistance in manufacturing a semiconductor device having a metal wiring structure.
본 발명이 상기 실시예에 한정되지 않으며, 많은 변형이 본 발명의 기술적 사상내에서 당 분야에서 통상의 지식을 가진자에 의하여 가능함은 명백하다.The present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical idea of the present invention.
Claims (4)
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| KR100457340B1 (en) * | 1997-09-30 | 2005-01-17 | 삼성전자주식회사 | Method for fabricating semiconductor device to improve planarization and reduce fabricating cost |
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