KR100203138B1 - Method of fabrication isolatin film of semiconductor device - Google Patents
Method of fabrication isolatin film of semiconductor device Download PDFInfo
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- KR100203138B1 KR100203138B1 KR1019960025718A KR19960025718A KR100203138B1 KR 100203138 B1 KR100203138 B1 KR 100203138B1 KR 1019960025718 A KR1019960025718 A KR 1019960025718A KR 19960025718 A KR19960025718 A KR 19960025718A KR 100203138 B1 KR100203138 B1 KR 100203138B1
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- oxide film
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 title abstract description 8
- 238000002955 isolation Methods 0.000 claims abstract description 45
- 238000000034 method Methods 0.000 claims abstract description 36
- 150000004767 nitrides Chemical class 0.000 claims abstract description 33
- 239000010410 layer Substances 0.000 claims abstract description 21
- 239000011229 interlayer Substances 0.000 claims abstract description 16
- 238000005530 etching Methods 0.000 claims abstract description 10
- 239000005380 borophosphosilicate glass Substances 0.000 claims abstract 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 4
- 230000001590 oxidative effect Effects 0.000 claims description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052796 boron Inorganic materials 0.000 abstract description 2
- 238000009792 diffusion process Methods 0.000 abstract description 2
- 230000000694 effects Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009834 vaporization Methods 0.000 description 1
- 230000008016 vaporization Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Element Separation (AREA)
Abstract
본 발명은 반도체 소자의 소자분리막 제조방법에 관한 것으로, 트랜치 식각후 CVD 산화막으로 소자분리영역을 매립한 다음 층간 질화막과 BPSG 막을 증착하여 이후 CMP 공정시 넓은 소자분리영역에서 나타나는 디싱(dishing) 효과를 감소시켜 좁은 영역과 넓은 영역의 소자분리영역의 산화막간의 단차를 줄일 수 있게 하여 CMP 공정에 의한 평탄화가 용이하고, 또한 층간 질화막을 사용함으로 최상층 BPSG 산화막에서 그 하층부로의 Boron 과 Posphorus 의 확산을 억제할 수 있어 반도체 소자의 제조수율 및 신뢰성을 향상시킬 수 있다.The present invention relates to a method for manufacturing a device isolation film of a semiconductor device, and after trench etching, the device isolation region is filled with a CVD oxide film, and then an interlayer nitride film and a BPSG film are deposited. It is possible to reduce the step difference between the oxide films in the narrow and wide device isolation regions by facilitating the planarization by the CMP process. Also, by using the interlayer nitride film, the diffusion of Boron and Posphorus from the uppermost BPSG oxide film to the lower layer is suppressed. It is possible to improve the production yield and reliability of the semiconductor device.
Description
제1도는 종래의 기술에 따라 형성된 반도체 소자의 소자분리막 형성상태를 도시한 단면도.1 is a cross-sectional view showing a device isolation film formation state of a semiconductor device formed according to the prior art.
제2a도 내지 제2g도는 본 발명의 기술에 따른 반도체 소자의 소자 분리막 제조 공정도.2A through 2G are diagrams illustrating a process of fabricating an isolation layer of a semiconductor device in accordance with the disclosed technology.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10 : 좁은 소자분리 영역 20 : 넓은 소자분리 영역10: narrow device isolation region 20: wide device isolation region
20 : 실리콘 기판 21 : 패드 산화막20 silicon substrate 21 pad oxide film
23,26 : 질화막 24 : 트랜치(Trench)23,26: nitride layer 24: trench
25 : CVD 산화막 27 : BPSG 막25 CVD oxide film 27 BPSG film
본 발명은 반도체 소자의 소자분리막 제조방법에 관한 것으로, 특히 트랜치 식각후 CVD 산화막으로 소자분리영역을 매립한 후 층간 질화막과 BPSG(Boro Posphorus Silligate)막을 증착하여 이후 평탄화공정시 넓은 소자분리영역에서 나타나는 디싱(dishing) 효과를 감소시켜 반도체 소자의 제조수율 및 신뢰성을 향상시킬 수 있는 반도체 소자의 소자 분리막 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a device isolation film of a semiconductor device, and in particular, after filling a device isolation region with a CVD oxide film after trench etching, depositing an interlayer nitride film and a BPSG (Boro Posphorus Silligate) film and then appearing in a wide device isolation region during a planarization process. The present invention relates to a device isolation film manufacturing method of a semiconductor device capable of reducing a dishing effect and improving a manufacturing yield and reliability of the semiconductor device.
종래의 기술에 따라 형성된 반도체 소자의 소자분리막 형성상태를 제1도에 도시 하였다.1 shows a device isolation film formation state of a semiconductor device formed according to the prior art.
상기 제1도에 도시한 바와같이, 종래의 트랜치 소자분리공정은 좁은 소자 분리 영역(10)과 넓은 소자분리 영역(20) 사이의 CVD 산화막을 CMP 공정등에 의해 제거할 때 좁은 지역의 산화막에 단차를 맞추면 넓은 지역의 산화막도 다소간에 제거가 되어서(30) 하나의 마스크 공정으로 소자분리막을 형성하기가 어려운 문제점이 있다.As shown in FIG. 1, in the conventional trench device isolation process, when the CVD oxide film between the narrow device isolation region 10 and the wide device isolation region 20 is removed by a CMP process or the like, a step is formed in the narrow region oxide film. In this case, the oxide film in a large area is also somewhat removed (30), which makes it difficult to form the device isolation film in one mask process.
따라서 본 발명은 상기의 문제점을 해결하기 위하여 트랜치 식각후 CVD 산화막으로 소자분리영역을 매립한 후 층간 질화막과 BPSG 막을 증착하여 이후 CMP 공정등에 의한 평탄화공정시 넓은 소자분리영역에서 나타나는 디싱 효과를 감소키켜 반도체 소자의 제조수율 및 신뢰성을 향상시킬 수 있는 반도체 소자의 소자 분리막 제조방법을 제공함에 그 목적이 있다.Therefore, in order to solve the above problems, the present invention reduces the dishing effect appearing in the wide device isolation region during the planarization process by CMP process by depositing the interlayer nitride layer and the BPSG layer after etching the device isolation region with the CVD oxide film after the trench etching. It is an object of the present invention to provide a method for manufacturing a device separator of a semiconductor device capable of improving the yield and reliability of the semiconductor device.
상기 목적을 달성하기 위한 본 발명의 방법에 의하면, 실리콘 기판 상부 표면을 산화시켜 패드 산화막을 형성하는 단계와, 상기 패드 산화막 상부에 질화막을 형성하는 단계와, 마스크 공정으로 소자분리 영역을 정의하는 단계와, 상기 소자분리영역으로 정의된 지역의 질화막과 패드 사화막을 차례로 건식식각하여 제거한 후 노출된 실리콘 기판을 일정깊이로 식각하여 트랜치를 형성하는 단계와, 전체구조 상부에 소자분리 산화막을 증착하여 상기 식각된 소자 분리 영역을 매립하는 단계와, 전체 구조 상부에 층간 질화막을 소정두께로 형성하는 단계와, 상기 질화막 상부에 평탄화 산화막을 일정두께로 형성하는 단계와, 상기 최상층의 평탄화 산화막과 층간 질화막 그리고 그 하층부의 소자분리 산화막을 제거하는 단계와, 습식식각으로 상가 소자영역의 질화막과 패드 산화막을 게거하는 단계로 구성됨을 특징으로 한다.According to the method of the present invention for achieving the above object, the step of oxidizing the upper surface of the silicon substrate to form a pad oxide film, forming a nitride film on the pad oxide film, and defining a device isolation region by a mask process Dry etching the nitride film in the region defined by the device isolation region and the pad vaporization film in order to form a trench by etching the exposed silicon substrate to a predetermined depth; and depositing a device isolation oxide film on the entire structure. Filling the etched device isolation region, forming an interlayer nitride film with a predetermined thickness on the entire structure, forming a planarization oxide film with a predetermined thickness on the nitride film, the top planarization oxide film and the interlayer nitride film, and Removing the device isolation oxide film at the lower layer, and adding the device by wet etching. Characterized by consisting of a step of a station gegeo nitride film and the pad oxide film.
이하 본 발명에 따른 반도체 소자의 소자분리막 제조방법에 대해 첨부 도면을 참조하여 보다 상세히 설명하기로 한다.Hereinafter, a device isolation film manufacturing method of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
제2a도 내지 제2g도는 본 발명의 방법에 따른 반도체 소자의 소자분리막 제조 공정도이다.2A through 2G are diagrams illustrating a process of fabricating an isolation layer of a semiconductor device according to the method of the present invention.
제2a도를 참조하면, 실리콘 기판(20)의 상부 표면을 산화시켜 패드 산화막(11)을 얇은 두께 예컨대, 약 50∼300Å로 형성한 후, 상기 패드 산화막(11) 위에 질화막(23)을 1000∼5000Å 형성한다.Referring to FIG. 2A, after the upper surface of the silicon substrate 20 is oxidized to form the pad oxide film 11 in a thin thickness, for example, about 50 to 300 kPa, the nitride film 23 is formed on the pad oxide film 11. It forms -5000 microseconds.
다음 마스크 공정으로 소자분리 영역을 정의한 후 상기 정의된 영역의 질화막(23)과 패드 산화막(21)을 차례로 건식식각하여 제거한다. 이어 노출된 실리콘 기판(20)을 2000∼5000Å 두께로 식각하여 트랜치(24)를 형성한다.After the device isolation region is defined by the next mask process, the nitride layer 23 and the pad oxide layer 21 of the defined region are sequentially removed by dry etching. Subsequently, the exposed silicon substrate 20 is etched to a thickness of 2000 to 5000 Å to form a trench 24.
이때, 소자분리 영역중 α 는 좁은 지역이고, β 는 넓은 지역이다.(제2a도 참조)At this time, α is a narrow region and β is a large region in the device isolation region (see also FIG. 2a).
다음 전체구조 상부에 CVD 산화막(25) 예컨대, O3-TEOS, BPSG, MTO 등의 산화막을 사용하여 2000∼10,000Å 두께로 증착하여 상기 식각된 소자분리 영역을 2000∼10,000Å 충분히 매립한 후, 그 위에 층간 질화막(26)을 500∼3000Å 증착하고 그 상부에 다시 BPSG(27)를 1000∼5000Å 두께로 증착한다.(제2b도 참조)Next, the CVD oxide layer 25, for example, O 3 -TEOS, BPSG, MTO or the like, was deposited to a thickness of 2000 to 10,000 Å on the entire structure to sufficiently fill the etched device isolation region 2000 to 10,000 Å. The interlayer nitride film 26 is deposited thereon at 500 to 3000 microseconds, and then the BPSG 27 is deposited at a thickness of 1000 to 5000 microseconds on the upper portion thereof (see also FIG. 2b).
다음 상기 최상층의 BPSG 산화막(27)을 CMP 공정으로 폴리싱(Polishing) 해서 제거한다.Next, the uppermost BPSG oxide film 27 is polished and removed by a CMP process.
이때 제2c도에 도시된 바와 같이 α 영역 위의 층간 질화막(26)이 노출 될 때 β 소자분리 영역의 BPSG 최상층 산화막(27)이 다소 남게 된다.In this case, as shown in FIG. 2C, when the interlayer nitride film 26 over the α region is exposed, the BPSG uppermost oxide layer 27 in the β device isolation region remains slightly.
이때 상기 산화막과 질화막을 CMP 공정으로 제거할 때 산화막이 질화막보다 식각속도가 빠르다.(제2c도 참조)At this time, when the oxide film and the nitride film are removed by the CMP process, the oxide film has a faster etching rate than the nitride film (see also FIG. 2C).
다음 α 소자분리 영역의 층간 질화막(26)을 CMP 공정으로 제거한다.Next, the interlayer nitride film 26 in the α device isolation region is removed by a CMP process.
이때 제2d도에 도시된 것처럼 β 소자분리 영역의 남아 있는 최상층 BPSG 산화막(27)막은 모두 제거되고 그 하층부의 층간 질화막(26)이 노출된다.(제2D도 참조)At this time, as shown in FIG. 2D, all of the remaining top layer BPSG oxide film 27 of the? Device isolation region is removed and the interlayer nitride film 26 of the lower layer is exposed (see also FIG. 2D).
β 소자분리 영역의 층간 질화막(26)을 계속해서 CMP 공정으로 제거한다. 이때 α 소자분리 영역의 CVD 산화막(25)이 층간 질화막(26)보다 빨리 식각되므로 제2e도에 도시한 것처럼 전체적인 평탄화가 이루어 진다(제2e도 참조).The interlayer nitride film 26 in the? device isolation region is subsequently removed by a CMP process. At this time, since the CVD oxide film 25 in the? Device isolation region is etched faster than the interlayer nitride film 26, the entire planarization is performed as shown in FIG. 2E (see FIG. 2E).
계속하여 CMP 공정으로 질화막(23) 위에 남아 있는 CVD 산화막(25)을 식각해서 질화막(23)의 상부표면이 모두 드러 나도록 한다(제2f도 참조).Subsequently, the CVD oxide film 25 remaining on the nitride film 23 is etched by the CMP process so that all of the upper surface of the nitride film 23 is exposed (see also 2f).
상기 노출된 질화막(23)과 그 하층부의 패드 산화막(21)을 제거하여 최종 소자분리용 산화막(50,50')을 형성한다.The exposed nitride film 23 and the pad oxide film 21 under the lower layer are removed to form the final device isolation oxide films 50 and 50 '.
이대, 상기 패드 산화막(21) 식각시 충분히 식각이 이뤄지도록 하여 안정된 형상의 소자분리 산화막(50,50')이 완성되게 한다.Subsequently, when the pad oxide film 21 is etched, the etching is sufficiently performed to complete the device isolation oxide films 50 and 50 'of a stable shape.
이상 상기한 바와 같은 본 발명에 따른 반도체 소자의 소자분리막 형성방법은 최상층에 BPSG 산화막을 사용함으로써 좁은 영역과 넓은 영역의 소자분리 영역의 산화막간의 단차를 줄일 수 있어 CMP 공정에 의한 평탄화가 용이하고, 또한 층간 질화막을 사용함으로 최상층 BPSG 산화막에서 그 하층부로의 Boron 과 Posphorus 의 확산(diffusion)을 억제할 수 있고 CMP 공정의 디싱효과도 줄일 수 있다.As described above, the device isolation film forming method of the semiconductor device according to the present invention can reduce the step difference between the oxide film of the narrow region and the large region of the device isolation region by using a BPSG oxide film on the uppermost layer, thereby making it easier to planarize by the CMP process. In addition, the use of an interlayer nitride film can suppress the diffusion of Boron and Posphorus from the top layer of BPSG oxide to the lower layer, and reduce the dishing effect of the CMP process.
Claims (10)
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| KR1019960025718A KR100203138B1 (en) | 1996-06-29 | 1996-06-29 | Method of fabrication isolatin film of semiconductor device |
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| KR1019960025718A KR100203138B1 (en) | 1996-06-29 | 1996-06-29 | Method of fabrication isolatin film of semiconductor device |
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| KR980005841A KR980005841A (en) | 1998-03-30 |
| KR100203138B1 true KR100203138B1 (en) | 1999-06-15 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019960025718A KR100203138B1 (en) | 1996-06-29 | 1996-06-29 | Method of fabrication isolatin film of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100203138B1 (en) |
-
1996
- 1996-06-29 KR KR1019960025718A patent/KR100203138B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR980005841A (en) | 1998-03-30 |
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