GB2333644A

GB2333644A - A method of forming void free trench isolation

Info

Publication number: GB2333644A
Application number: GB9901480A
Authority: GB
Inventors: Chang-Ki Hong
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 1998-01-26
Filing date: 1999-01-22
Publication date: 1999-07-28
Also published as: FR2776126A1; GB9901480D0; JPH11260903A; KR19990066454A; DE19902999A1; TW412834B

Abstract

A method of forming an isolating trench in a semiconductor substrate 30 so as to form void free patterns of isolation within the substrate 30 and to prevent a recess from being generated at side edges of the trench during subsequent etching steps. With the method, a trench forming mask 38 is formed on the substrate 30, in which the trench forming mask is composed of first and second material layers 34,36 having an etch ratio different from each other. The substrate 30 is etched using the trench forming mask 38 to form a trench 40, and then the first material layer 34 is wet-etched to remove both sidewalls of the first material layer 34 and to thereby form an under-cut profile of the trench forming mask 38. Finally, a trench filling insulation layer 44 is deposited over the substrate filling up the trench forming mask 38, wherein deposition speed of the trench filling Insulation layer 44 is slower at the sidewalls of the first material layer 34 than at an interior of the trench. Alternatively, the pad oxide 32 may be etched back prior to trench refilling (figure 3b). In another embodiment a thermal oxide film 54 is provided between the trench oxide field region and the active region, which prevents 'dipping' of the trench oxide during subsequent cleaning stages.

Description

z 1 U 2333644 A METHOD OF FORMING A VOID FREE TRENCH ISOLATION

Field of the Invention

The present invention relates to a method of forming an isolating trench in a semiconductor substrate so as to form void free patterns of isolation within the substrate and to prevent a recess from being generated at side edges of the trench during subsequent etching steps.

Background of the Inventio

In fabrication of trench isolation, a known problem has been that of voids caused by the insulating material fill in the trench on the silicon substrate. A form of trench isolation :10 is disclosed in the H.B. Pogge U.S. Pat. No. 4,256,514. Pogge describes isolation formation wherein chemical vapor deposition Or the like is used to deposit insulating material such as, silicon dioxide or polycrystalline silicon into the pattern of trenches. Such systems involve a homogeneous gas phase reaction wherein the silicon dioxide, polycrystalline silicon or the like is formed in the gas from the reactive species present and is deposited therefrom onto the surfaces and into the pattern of trenches. The problem with this method of deposition is that there is a tendency to form voids within the trench patterns particularly where trenches cross one another. Also, the refilling deposition can produce structurally deficient or loosely packed material which may not be the best isolation structures in integrated circuits. The presence of voids and this loose structure have a tendency to magnify the formation of defects in silicon areas which are later to serve as active or passive device regions.

Figs. I A through I D show the process steps of a prior art method of forming a trench isolation. Referring to Fig. 1A, an oxide layer 12, an silicon nitride layer 14 and an oxide layer 16 are sequentially formed on a silicon substrate 10. A photolithography is carried out to form a pattern of photoresist on the oxide layer 16, and then an etching step is carried out 1 c is using the patterned photoresist layer as a mask. As a result, a trench forming mask 18 is formed. Well-known RIE (reaction ion etching) process in the art is carried out using the trench forming mask 18 to remove a portion of the oxide layer 12 and thereby expose a portion of the substrate 10. The RIE process continues to be carried out to form a trench 20.

After formation of the trench 20, a thermal oxidation process is carried out to form a thermal oxide layer 22 on the interior of the trench 20.

Subsequently, as shown in Fig. 1B, an insulating material 24 is deposited by CVD (chemical vapor deposition) process as disclosed in the above mentioned U. S. Pat. No.

4,256,514. When the insulating material 24 is deposited, it is done faster at both sidewalls (referring to a symbol "A" depicted in a dotted circle of Fig. 1B) of the trench forming mask 18 than at the interior (referring to a symbol "B" depicted in a dotted circle of Fig. 1B) of the trench 20. The insulating material 24 formed thus is thicker at both sidewalls of the trench forming mask 18 than at the interior of the trench 20. As a result, a void 26 is generated due to the deposition speed difference of the insulating material 24, as shown in Fig. I C.

Finally, if planarization such as CMP (chemical mechanical polishing) process is carried out until the substrate surface is exposed, whereby to form a trench filling insulation layer 24. As can be seen from Fig. I D, the void 26 is normally formed at the center portion of the trench filling isolation 24. This is because the inlet of the trench 20 is sealed with the insulating material before the interior thereof is completely filled up with the insulating material 24. If a conductive material is filled up the void 26 according to subsequent steps, there arises a serious problem that a circuit-short between circuit devices may be generated.

Also, a recess or a groove (referring to a symbol "C" depicted in a dotted circle of Fig. ID) is formed at an interface between active and field regions during subsequent etching (or cleaning) steps to cause a loose structure of trench isolation. This is called "dipping phenomenon". Such dipping is frequently generated, particularly, at edges of the trench. The presence of voids and this loose structure have a tendency to magnify the formation of defects in silicon areas which are later to serve as active or field region, as described above.

2 J Summary of the Invention

It is therefore an object of the invention to provide a method of forming an isolating trench in which a void is not formed within the trench.

It is a further object of the invention to provide a method of forming an isolating trench in which a recess (i.e., groove) is not formed at upper side edges of the trench during subsequent etching step.

It is another object of the invention to provide a method of forming an isolating trench in which a recess is not formed on an upper surface of the trench during subsequent cleaning step.

According to an aspect of the present invention, there is provided a method of forming a trench isolation in a semiconductor substrate. With the method, a trench forming mask is formed on the substrate, in which the trench forming mask is composed of first and second material layers having an etch ratio different from each other. The substrate is etched using the trench forming mask to form a trench, and then the first material layer is wet-etched to remove both sidewalls of the first material layer and to thereby form an under-cut profile of the trench forming mask. Finally, a trench filling insulation layer is deposited over the substrate filling up the trench forming mask, wherein deposition speed of the trench filling insulation layer is slower at the sidewalls of the first material layer than at an interior of the trench.

According to a further aspect of the present invention, there is provided a method of forming a trench isolation in a semiconductor substrate, which comprises sequentially forming a silicon nitride layer and a first oxide layer on the substrate. The silicon nitride layer and the first oxide layer are selectively etched to expose a portion of the substrate. The substrate is etched using the patterned silicon nitride layer as a trench forming mask to form a trench. The first oxide layer is wet-etched to remove sidewalls of the first oxide layer and expose a portion of the substrate in the vicinity of edges of the trench. A second oxide layer is formed on the exposed portion of the substrate in addition to an interior of the trench, and an insulating layer is formed over the substrate filling up the trench. Finally, the substrate is 3 1 planarized until an upper surface of the substrate is exposed.

According to another aspect of the present invention, there is provided a method of forming a trench isolation in a semiconductor substrate, which comprises forming a pattern of photoresist on the substrate to define active and field regions of the substrate. The field region of the substrate is oxidized to form an oxide layer. A spacer layer having etch selectivity with respect to the substrate is formed which is formed on both sidewalls of the photoresist layer. The oxide layer and the substrate are selectively etched using a pattern of the photoresist and spacer layers as a trench forming mask, a portion of the oxide layer remaining in the vicinity of edges of the trench. An insulating layer is formed over the substrate filling up the trench, and the insulating layer is planarized until an upper surface of the substrate is exposed.

Brief Descri13tion of the Attached Drawin s This invention may be understood and its object will become apparent to those skilled in the art by reference to the accompanying drawings as follows:

Figs. IA through ID are flow diagrams showing the process steps of a method of forming an isolating trench according to a prior art;

Figs. 2A through 2D are flow diagrams showing the process steps of a method of forming an isolating trench according to a first embodiment of the present invention; Figs. 3A through 3F are flow diagrams showing the process steps of a method of forming an isolating trench according to a second embodiment of the present invention; and Figs. 4A through 4D are flow diagrams showing the process steps of a method of forming an isolating trench according to a third embodiment of the present invention; Detailed Description of the Preferred Embodiments

EmbQdiment 1 Figs. 2A through 2D show the process steps of a novel method of forming an isolating trench according to a first embodiment of the present invention.

4 1-1/ Referring now to Fig. 2A, there is a portion of a silicon substrate (or epitaxial layer) having a pad oxide layer 32 of thickness about 100 30OG and an active mask 38 serving as a trench forming mask. Active and field regions of the substrate 30 are defined by the active mask 38. The pad oxide layer 32 is formed by thermal oxidation at a temperature of about 900 - 1300HC. The mask 38 is composed of two layers having the etch ratio different from each other, one of which is a first material layer 34 of thickness about 500 - 2000G, such as silicon nitride, and the other of which is a second material layer 36 such as CVD (chemical vapor deposition) oxide. The silicon nitride layer 34 is formed by CVD or PVD (physical vapor deposition) and used as an etch stopper during subsequent planarization of trench filling insulator, and the CVD oxide layer 36 may be an HTO (high- temperature oxide) layer formed by CVD process and used as a pattern layer to obtain a desired trench profile with a trench etching step. Also the pad oxide layer 32 is provided to mitigate the coefficient of expansion between the silicon substrate 30 and the silicon nitride layer 34. Pattern of the active mask 38 may be formed by RIE (reactive ion etching) process using a photoresist mask (not shown) which is formed by a well-known photolithography in the art.

After the active mask 38 is formed, a trench etching step such as RIE process using plasma is performed using the patterned mask 38, and thereby a trench 40 is formed corresponding to the field region. Next a thermal oxidation step is performed to form a thermal oxide layer 42 on the interior of the trench 40. The thermal oxide layer 42 is provided to stabilize the substrate surface.

With reference to Fig. 2B, a wet etching process is carried out to selectively etch both sidewalls of the silicon nitride layer 34, and thereby the active mask 38 has an under-cut profile as shown in this figure. The wet etching process is carried out on conditions that the etch ratio of the silicon nitride layer 34 to the CVD oxide layer 36 is in the range of 40:1 to 45:1 and etch speed of the silicon nitride layer 34 is controlled to thickness of forty angstroms per one minute, when a phosphoric acid solution is used as etchant. Alternatively, HF solution may be used as the etchant.

Subsequently, an insulating material 44 is deposited, as shown in Fig. 2B, by using CVD process over the substrate, filling up the interior of the trench 40. When the insulating material 44 is filled up the trench 40, the insulating material at both sidewalls of the active mask 38 is deposited at lower speed than that at the interior of the trench 40. This is because the insulating material 44 is moved to the under-cut portion of the active mask 38, i.e., the recessed portion of the silicon nitride layer 34 while deposited.

As described immediately above, it is a key feature of this embodiment that, because of the under-cut profile of the active mask 38, the insulating material is deposited slower at the inlet of the trench than at the interior thereof. Thus the insulating material may be entirely filled up the interior of the trench 40 before the inlet of the trench is sealed with the insulating material.

As shown in Figs. 2C and 2D, the deposition of the insulating material continues to be carried out on the condition of the under-cut profile structure of the active mask 38, and thereby the insulating material 44a is completely filled up the trench 40. Also we should give attention to the fact that the insulating material 44a is covered even on a portion of the active region of the substrate. For this reason, a recess is not formed on the upper surface of the trench 40 even though subsequent cleaning (or etching) steps are performed.

Finally, planarization is carried out using CMP (chemical mechanical polishing) until the surface of the silicon nitride layer 34 serving as the etch stopper is exposed, and then the silicon nitride layer 34 and the CVD oxide layer 36 are removed to thereby form a void free trench isolation. Here it is the other key feature of this embodiment that a difference step is generated between the trench isolation and the substrate, that is, the void free trench isolation is formed higher than the substrate. For this reason, although a subsequent etching steps are performed prior to the formation of a conductive lien, for example, a word line, such a recess is not formed on the void free trench isolation.

According to the above-described embodiment of the invention, when deposition of trench isolation is carried out using a trench forming mask, an insulating material is deposited slower at both sidewalls of the trench forming mask than at the interior of the trench. Therefore a void free trench isolation can be formed.

6 Also since the void free trench isolation is formed higher than the substrate, a recess is not formed on the void free trench isolation, even though subsequent cleaning (or etching) steps are performed prior to the formation of a conductive layer.

Embodiment Figs. 3A through 3F show the process steps of a novel method of forming an isolating trench according to a second embodiment of the present invention.

Referring to Fig. 3A, there is a portion of a silicon substrate (or epitaxial layer) having the same construction as the silicon substrate 30 of Fig. 2A except that a CVD oxide layer such as HTO is not formed on a silicon nitride layer, and hence identical parts are denoted by the same reference numerals to omit redundant description. In details, a single layer 34 of silicon nitride is provided on a pad oxide layer 32 to constitute a trench forming mask as an active mask. This trench forming mask is formed by patterning the silicon nitride layer 34 to define active and field regions. The pad oxide layer 32 is provided to mitigate the coefficient of expansion between the silicon substrate 30 and the silicon nitride layer 34. Pattern of the trench forming mask 34 may be formed by RIE process as in the first embodiment.

After the trench forming mask 34 is formed, a trench etching step such as RIE process using plasma continues to be performed using the mask 34, and thereby a trench 40 is forTned corresponding to the field region.

Figs. 3B and 3C show the most important process steps of the second embodiment.

Referring to Fig. 3B, an anisotropic etching process (or a wet etching process) is carried out using HF solution as etchant to selectively remove a portion of the pad oxide layer 32 in the vicinity of the edges of -the trench 40. The upper surface of the substrate 30 is partially exposed by the wet etching process. Next the trench forming mask 34 related to the pad oxide layer 32 has an under-cut profile as shown in Fig. 3B.

Subsequently, as shown in Fig. 3C, a thermal oxidation step is performed to form a thermal oxide layer 42a on the exposed portion of the upper surface of the substrate 30 in 7 addition to the interior of the trench 40. Then the thermal oxide layer 42a is formed of a rounded-shape at the top edges of the trench 40 as depicted by an expanded dotted-circle in Fig. 3C. The thermal oxide layer 42a is provided to stabilize the substrate surface and prevent a recess from being generated at the edges of the trench. Herein we should give attention to the fact that side surfaces of the silicon substrate 30 in the vicinity of the edges of the trench 40 are not exposed by the covered thermal oxide layer 42a. If deposition of an insulating material is carried out with the side surfaces of the substrate exposed, a dipping phenomenon is caused at the edges of the trench during subsequent etching steps.

With reference to Fig. 3D, an insulating material 44 is deposited by using CVD 10 process over the substrate, filling up the interior of the trench 40.

As shown in Figs. 3E and 3F, planarization of the insulating material is carried out using CMP (chemical mechanical polishing) process until the surface of the silicon nitride layer 34 serving as the etch stopper is exposed, and then the silicon nitride layer 34 is removed by a wet or dry etching process to thereby form a trench filling insulation layer. With the wet or dry etching process, a portion of the trench filling insulation layer 44 in addition to the silicon nitride layer 34 is removed as shown in Fig. 3E.

Subsequently, a wet or dry etching process is also carried out until the substrate surface is exposed, and thereby the pad oxide layer 32, a portion of the thermal oxide layer 42a and a portion of the insulating material 44 are removed. As a result, the trench filling insulation layer 44a is completely formed as shown in Fig. 3F. Since the thermal oxide layer 42a is made of the same component as the insulating material 32, the thermal oxide layer 42a is not depicted in Fig. 3F.

According to the second embodiment described above, since side surfaces of substrate in the vicinity of the edges of trench are not exposed by a thermal oxide layer covering the side surfaces, a dipping phenomenon is not generated at the edges of the trench during subsequent etching steps. Thus thickness of a gate oxide layer to be formed on the active region of the substrate can be constantly maintained whereby to considerably reduce a withstanding voltage of the gate oxide layer.

8 Embodiment Figs. 4A through 4D show the process steps of a novel method of forming an isolating trench according to a third embodiment of the present invention.

Referring to Fig. 4A, there is a portion of a silicon substrate (or epitaxial layer) 50 having a patterned photoresist layer 52 and an oxide layer 54 thereon. The oxide layer 54 is formed by thermal oxidation to thickness about 100 - 500G. During the thermal oxidation, oxide is penetrated into the interface between the substrate and the photoresist layer, and thereby a shape of bird's beak is formed as shown in Fig. 4A.

With reference to Fig. 4B, an insulating layer such as HTO or nitride having etch selectivity with respect to the substrate 50 is deposited and etched back to form a spacer 56 on both sidewalls of the photoresist layer 52. The spacer 56 has etch selectivity with respect to the substrate 50.

As shown in Fig. 4C, an anisotropic etching process such as RIE is carried out using a pattern of the photoresist and spacer layers as a trench forming mask to remove a portion of the oxide layer 54 and thereby expose the substrate. By the trench forming mask, active and field regions of the substrate 50 are defined. The RIE using the trench forming mask continues to be carried out to form a trench 58, and then an insulating material 60 such as USG (undoped silicate glass) or TEOS (tetra-ethyl-orthosilicate) oxide is deposited filling up the trench 58.

Finally, as shown in Fig. 4D, planarization is carried out using CMP process until the upper surface of the substrate 50 is exposed. Herein we should give attention to the fact that the thermal oxide 54 remains at an interface between the active and field regions. Thus a problem of dipping caused due to subsequent cleaning steps can be solved because of the remaining oxide 54.

According to the third embodiment described above, since an oxide layer which remains in the vicinity of edges of a trench, a dipping phenomenon is not generated, even though subsequent cleaning (or etching) steps are carried out.

Also, since a trench forming mask includes a spacer on both sidewalls thereof, the 9 trench may have a profile smaller in a bottom width than in a top width. Accordingly, a void free trench isolation can be formed.

Claims

T IS CLAIMED IS:

1. A method of forming a trench isolation in a semiconductor substrate comprising the steps of:

forming a trench forming mask on the semiconductor substrate, said trench forming mask being composed of first and second material layers having an etch ratio different from each other; etching the substrate using the trench forming mask to form a trench; wet-etching the first material layer to remove both sidewaIls of the first material layer and to thereby form an under-cut profile of the trench forming mask; and depositing a trench filling insulation layer over the substrate filling up the trench forming mask, wherein deposition speed of the trench filling insulation layer is slower at the sidewalls of the first material layer than at an interior of the trench.

2. The method according to Claim 1, wherein said first material layer is made of silicon nitride and said second material layer is made of CVD (chemical vapor oxide) oxide.

3. The method according to Claim 1, wherein said etch ratio of the first material layer to the second material layer is in the range of about 40:1 - 45: 1.

4. A method of forming a trench isolation in a semiconductor substrate comprising the steps of:

sequentially forming a silicon nitride layer and a first oxide layer on the substrate; patterning the silicon nitride layer and the first oxide layer to expose a portion of the substrate; etching the substrate using the patterned silicon nitride layer as a trench forming mask to form a trench; 11 1 wet-etching the first oxide layer to remove sidewalls of the first oxide layer and expose a portion of the substrate in the vicinity of edges of the trench; forming a second oxide layer on the exposed portion of the substrate in addition to an interior of the trench; forming an insulating layer over the substrate filling up the trench; and planarizing the substrate until an upper surface of the substrate is exposed.

5. The method according to Claim 4, wherein said second oxide layer is formed of a rounded-shape at the edges of the trench.

6. The method according to Claim 4, further comprising the step of forming an 10 HTO (high-temperature oxide) layer on the silicon nitride layer.

7. A method of forming a trench isolation in a semiconductor substrate comprising the steps of: forming a pattern of photoresist on the substrate to define active and field regions of the substrate; is oxidizing the field region of the substrate to form an oxide layer; forming a spacer layer having etch selectivity with respect to the substrate, said spacer layer being formed on both sidewalls of the photoresist layer; selectively etching the oxide layer and the substrate using a pattern of the photoresist and spacer layers as a trench forming mask, a portion of the oxide layer remaining in the vicinity of edges of the trench; forming an insulating layer over the substrate filling up the trench; and planarizing the insulating layer until an upper surface of the substrate is exposed.

8. The method according to Claim 7, wherein said spacer is made of HTO or nitride.

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9. The method according to Claim 7, wherein said trench has a profile smaller in a bottom width than in a top width.

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