KR19990000624A - SOI DRAM with a buried capacitor and a method of manufacturing the same - Google Patents

Abstract

Disclosed are a silicon on insulator (SOI) DRAM having a buried capacitor capable of patterning an upper electrode of a capacitor in a device isolation process without a separate photo process, and a manufacturing method thereof. The present invention provides a method of forming a buried oxide film on a first semiconductor substrate having a lower structure, patterning the buried oxide film to form first and second contact holes, and stacking a first conductive film on the resultant. And forming a lower electrode by forming a lower electrode, stacking and patterning an upper electrode layer formed of a dielectric film and a second conductive film on the lower electrode to form a capacitor, and stacking and planarizing a first insulating film on the resultant. Forming a SOI structure by etching back the back surface of the first semiconductor substrate, forming a pad oxide film and a second insulating film on the back surface of the first semiconductor substrate for a device isolation process; Patterning the oxide film and the second insulating film to form third and fourth contact holes, and using the patterned pad oxide film and the second insulating film as a mask to form a first semiconductor substrate. To be etched forming a trench, filling the isolation film on the etched SOI semiconductor substrate to provide a manufacturing method of a SOI DRAM having a buried capacitor comprising the step of removing the second insulating film.

Description

SOI DRAM with a buried capacitor and a method of manufacturing the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly, to a silicon on insulator (SOI) DRAM having a buried capacitor, and a method of manufacturing the same. .

SOI is a technology for more effectively separating semiconductor devices formed on a silicon substrate, which is more resistant to light and more resistant to high supply voltage than Junction Isolation. In addition, semiconductor devices formed on SOI substrates generally reduce the number of processes required for fabrication, rather than semiconductor devices formed on bulk silicon substrates, and individual devices formed on SOI substrates have the advantage of reducing capacitive coupling. . When manufacturing SOI DRAM using silicon direct bonding (SDB), the use of a buried capacitor structure not only achieves high integration, but also facilitates interconnection in metallization processes.

A DRAM structure adopting such an SOI structure to form a buried capacitor was filed in 1992 by Samsung Electronics Co., Ltd. under Korean Patent Application No. 26778 (Title: Method of Manufacturing DRAM Using SDB and SOI).

1 is a cross-sectional view illustrating a structure of a SOI DRAM having a buried capacitor according to the prior art and a method of manufacturing the same.

Referring to FIG. 1, a region in which a cell is formed and a region in which a core is formed is defined in the first semiconductor substrate 1, and a trench is formed by etching the semiconductor substrate. At this time, the cell region is etched deeper than the core region. Subsequently, the first insulating layer 3 for forming an isolation layer is laminated and patterned by using HTO (High Temperature Oxide), BPSG (Boro-Phosphorus Silicate Glass), or the like. Subsequently, an undoped polysilicon layer 5 and a doped polysilicon layer 7 are sequentially formed and patterned on the resultant patterned pattern of the first insulating layer 3 to form a capacitor lower electrode. do. Subsequently, a dielectric film (not shown) is laminated and an upper electrode layer 9 composed of a conductive layer is formed to form a capacitor. After stacking the second insulating film 11 including HTO and BPSG on the semiconductor substrate on which the capacitor is formed and performing the planarization process, the second semiconductor substrate 15 is attached by the SDB method. Lastly, the back side of the first semiconductor substrate is etched back to the etch stopper to form an SOI DRAM having an embedded capacitor.

In this case, when the capacitor upper electrode 9 is not patterned, the soft error rate of the DRAM memory cell increases due to unwanted noise such as an alpha line even after the semiconductor device is manufactured through a packaging process. Etc.

In addition, in the case of patterning, there is a problem in that an SDB process of bonding the second semiconductor substrate becomes difficult due to the addition of another photo process as well as the step difference of the thickness of the upper electrode.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide an SOI DRAM having an embedded capacitor capable of patterning an upper electrode of a capacitor through an isolation process performed on an SOI substrate after an SDB process without using an additional photo process.

Another object of the present invention is to provide a method of manufacturing an SOI DRAM having the buried capacitor.

1 is a cross-sectional view illustrating a structure of a SOI DRAM having a buried capacitor according to the prior art and a method of manufacturing the same.

2 to 9 are cross-sectional views illustrating a method of manufacturing an SOI DRAM having an embedded capacitor according to the present invention.

Brief description of symbols for the main parts of the drawings

100: first semiconductor substrate, 102: buried oxide film,

104: first contact hole, 106: second contact hole,

108: first conductive film, 110: lower electrode pattern,

112: upper electrode layer 114: first insulating film,

116: second semiconductor substrate, 118: pad oxide film,

120: second insulating film, 122: third contact hole,

124: fourth contact hole, 126: device isolation film.

MEANS TO SOLVE THE PROBLEM In order to achieve the said technical subject, this invention is a 2nd semiconductor substrate, the 1st semiconductor substrate comprised on the said 2nd semiconductor, the insulating film between the said 2nd semiconductor substrate and the 1st semiconductor substrate, and the said 1st semiconductor An SOI semiconductor memory device comprising a capacitor having a lower electrode, a dielectric film, and an upper electrode formed under a substrate, an SOI layer formed on the first semiconductor substrate, and an isolation layer formed on the SOI layer. One is provided with an SOI DRAM having an embedded capacitor connected to a lower electrode of the first semiconductor substrate and separating the upper electrode of the first semiconductor substrate into two.

In order to achieve the above technical problem, the present invention provides a method for forming a buried oxide film on a first semiconductor substrate on which a substructure is formed, and forming a first and a second contact hole by patterning the buried oxide film. A second step of forming a lower electrode by stacking and patterning a first conductive film on the resultant layer; and forming a capacitor by stacking and patterning an upper electrode layer consisting of a dielectric film and a second conductive film on the lower electrode. A fourth step of stacking and planarizing a first insulating film on the resultant; a sixth step of etching back the back surface of the first semiconductor substrate to form an SOI structure; A seventh step of forming a pad oxide film and a second insulating film on the back surface of the device isolation process, an eighth step of forming the third and fourth contact holes by patterning the pad oxide film and the second insulating film; A ninth step of forming a trench by etching the back surface of the first semiconductor substrate using the patterned pad oxide layer and the second insulating layer as a mask; and a tenth step of filling a device isolation layer in the etched SOI semiconductor substrate and removing the second insulating layer. It provides a method for manufacturing an SOI DRAM having an embedded capacitor, characterized in that it comprises a step.

According to a preferred embodiment of the present invention, it is preferable that the second contact hole of the second step is larger than the first contact hole in the region where the upper electrode of the capacitor is patterned, and pattern the first conductive film of the third step. The method may be suitably patterned such that overetching occurs in a region having the second contact hole so that a trench is formed in the first semiconductor substrate.

Preferably, in the method of stacking the second conductive film, the first contact hole is completely filled, and the second contact hole is preferably stacked so as not to be completely filled.

The method of planarizing the first insulating film is performed through a chemical mechanical polishing (CMP) process, and after the planarization process is finished, the second semiconductor substrate is formed on the top side of the first semiconductor substrate. It is suitable to bond

In addition, the fourth contact hole of the eighth step may be formed in an upper portion of the region where the second contact hole is formed, and when the trench is formed in the ninth step, the first insulating layer may be overetched with an etch stop layer to form a semiconductor. It is suitable to allow the upper electrode of the substrate to be bisected. In this case, in the region where the third contact hole is formed, overetching may be performed by using the buried oxide layer as an etch stop layer.

According to the present invention, the upper electrode of the capacitor can be patterned in the device isolation process of the SOI substrate without using an additional photo process, and the upper electrode of the patterned capacitor has a soft error rate of the semiconductor device even after packaging. rate can be reduced.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, in the SOI DRAM having the buried capacitor according to the present invention, the device isolation layer formed on the first semiconductor substrate which is the SOI substrate is connected to the lower electrode of the capacitor, and has a structural feature of separating the upper capacitor electrode into two.

2 to 9 are cross-sectional views illustrating a method of manufacturing an SOI DRAM having an embedded capacitor according to the present invention.

Referring to FIG. 2, a substructure such as a transistor is formed on a first semiconductor substrate 100 formed of a silicon single crystal, and a buried oxide film 102 is stacked. The first and second contact holes 104 and 106 are formed by coating the photoresist on the buried oxide film 102 and performing a photolithography and etching process to pattern the buried oxide film 102. In this case, the region where the second contact hole 106 is formed is a region where the capacitor upper electrode is patterned in a subsequent process. In addition, the second contact hole 106 has a size larger than that of the first contact hole, thereby ensuring sufficient space for the upper electrode of the capacitor to be patterned.

Referring to FIG. 3, a first conductive layer 108 made of polysilicon is stacked on an entire surface of a semiconductor substrate on which the first and second contact holes 104 and 106 are formed. In this case, the first conductive layer 108 may be formed by first stacking a polysilicon layer that is not doped with impurities, followed by a second laminate of the polysilicon layer that is doped with impurities. Here, it is suitable that the thickness of the polysilicon layer laminated secondly is thicker than the thickness of the polysilicon layer laminated firstly.

Referring to FIG. 4, a photoresist is applied on the first conductive layer 108, and a photoresist process is performed to form a capacitor lower electrode pattern 110. In this case, an actual lower electrode pattern is formed in the region having the first contact hole, and a dummy storage pattern is formed in the region having the second contact hole. Here, the buried oxide film 102 serves as an etch stop layer in the region having the first contact hole in the etching, and in the region having the second contact hole, the first semiconductor substrate is etched to sufficiently form the trench. It is appropriate to do

Referring to FIG. 5, one dielectric film (not shown) is formed on the entire surface of the lower electrode 110 in which the lower electrode 110 is patterned. The capacitor structure is completed by stacking the upper electrode layer 112 made of a second conductor film such as silicon. Here, in the method of stacking the upper electrode layer 112, it is preferable that the first contact hole 104 is completely buried, and the second contact hole 106 is not completely buried. Subsequently, a first insulating film 114 made of an oxide film is coated to deposit the second contact hole which is not completely buried, and to deposit a predetermined thickness on the semiconductor substrate. The first insulating layer 114 filling the inside of the second contact hole 106 serves as an etching stopper in the process of forming a trench in the first semiconductor substrate 100 in a subsequent device isolation process. Plays an important role. Therefore, it is possible to pattern the upper electrode layer 112 pursued in the present invention without performing a separate photo process.

Referring to FIG. 6, the first insulating layer is planarized through a chemical mechanical polishing process (CMP), and the handling wafer, which is the second semiconductor substrate 116, is bonded by SDB (Silicon Direct Bonding). Subsequently, a tinning process is performed on the back surface of the first semiconductor substrate 100 to form an SOI structure.

Referring to FIG. 7, a second insulating layer 120 using a pad oxide layer 118 and a nitride layer is formed on the back surface of the first semiconductor substrate. Subsequently, photoresist is applied to the pad oxide layer 118 and the second insulating layer 120, and a photo and etching process is performed to form a third contact hole 122 in the region of the first contact hole 104. The fourth contact hole 124 is formed on the contact hole 106.

Referring to FIG. 8, a first semiconductor substrate 100 under the third contact hole 122 and a fourth contact hole, that is, an SOI substrate, is formed by using the patterned pad oxide layer 118 and the second insulating layer 120 as a mask. Etch to form a trench. Such trench etching is preferably overetched using a difference in etching selectivity between silicon and an oxide film. The over-etching range is such that the buried oxide film 102 is an etch stop layer in the SOI substrate having the third contact hole 122, and the SOI substrate is formed in the region having the fourth contact hole 124. All of the capacitor upper electrodes 112 are also etched. Therefore, the upper electrode 112 under the fourth contact hole 124 is patterned to be divided into two. The bisected upper electrode 112 was additionally formed in the device isolation process without using a separate photo process, and has an effect of reducing the soft error rate due to alpha rays even after the subsequent packaging process. The object of the present invention is achieved.

Referring to FIG. 9, a device isolation layer 126 is formed by depositing and etching back a field oxide layer filling the trench. Finally, the second insulating film 120 and the pad oxide film 118 are removed to planarize the SOI substrate, thereby completing the manufacturing process of the SOI DRAM having the buried capacitor according to the present invention.

The present invention is not limited to the above-described embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical spirit to which the present invention belongs.

Therefore, according to the present invention described above, the capacitor upper electrode can be additionally patterned and separated in a subsequent device isolation process without a separate photo process in the DRAM manufacturing process using the SOI substrate. The upper electrode structure having this separated structure can reduce the soft error of the DRAM.

Claims (10)

A second semiconductor substrate, A first semiconductor substrate formed on the second semiconductor, An insulating film between the second semiconductor substrate and the first semiconductor substrate, A capacitor having a lower electrode, a dielectric film, and an upper electrode formed below the first semiconductor substrate; An SOI layer formed on the first semiconductor substrate; In an SOI semiconductor memory device comprising device isolation layers formed on the SOI layer, One of the device isolation film, Connected to the lower electrode of the first semiconductor substrate, SOI DRAM having a buried capacitor, characterized in that for separating the upper electrode of the first semiconductor substrate into two. Forming a buried oxide film on the first semiconductor substrate on which the substructure is formed; Patterning the buried oxide film to form first and second contact holes; Stacking and patterning a first conductive layer on the resultant to form a lower electrode; Stacking and patterning an upper electrode layer including a dielectric layer and a second conductive layer on the lower electrode to form a capacitor; Stacking and planarizing a first insulating film on the resultant material; A sixth step of etching back the back surface of the first semiconductor substrate to form an SOI structure; Forming a pad oxide film and a second insulating film on the back surface of the first semiconductor substrate for a device isolation process; An eighth step of patterning the pad oxide layer and the second insulating layer to form third and fourth contact holes; A ninth step of forming a trench by etching the back surface of the first semiconductor substrate using the patterned pad oxide layer and the second insulating layer as a mask; And embedding a device isolation layer in the etched SOI semiconductor substrate and removing a second insulating layer. 3. The method of claim 2, wherein the second contact hole of the second step is larger than the first contact hole as a region where the upper electrode of the capacitor is patterned. 3. The method of claim 2, wherein the method of patterning the first conductive layer in the third step comprises patterning a trench in the first semiconductor substrate by overetching in a region having a second contact hole. A method of manufacturing an SOI DRAM having a buried capacitor. The method of claim 1, wherein the stacking of the second conductive layer in the fourth step comprises stacking the first contact hole to completely fill the second contact hole and not to completely fill the second contact hole. Manufacturing method. The method of claim 1, wherein the method of planarizing the first insulating layer in the fifth step is planarized by chemical mechanical polishing (CMP). The SOI DRAM according to claim 1, further comprising: bonding a second semiconductor substrate to the top side of the first semiconductor substrate following the planarization process of the fifth step. Manufacturing method. The method of claim 1, wherein the fourth contact hole of the eighth step is formed above the region where the second contact hole is formed. The method of claim 1, wherein the trench of the ninth step is formed by over-etching the first insulating layer as an etch stop layer in a region where a fourth contact hole is formed so that the SOI semiconductor substrate and the upper electrode are bisected. A method of manufacturing an SOI DRAM having an investment capacitor, characterized in that. The trench forming method of claim 9, wherein the trench of the ninth step is formed by overetching the buried oxide layer as an etch stop layer in the region where the third contact hole is formed. Method of manufacturing SOI DRAM.