KR100301148B1 - Forming method for hard mask of semiconductor device - Google Patents

Forming method for hard mask of semiconductor device Download PDF

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KR100301148B1
KR100301148B1 KR1019990025385A KR19990025385A KR100301148B1 KR 100301148 B1 KR100301148 B1 KR 100301148B1 KR 1019990025385 A KR1019990025385 A KR 1019990025385A KR 19990025385 A KR19990025385 A KR 19990025385A KR 100301148 B1 KR100301148 B1 KR 100301148B1
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film
forming
hard mask
silicon
insulating film
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KR20010004682A (en
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김현곤
박진요
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박종섭
주식회사 하이닉스반도체
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
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    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
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    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H01L21/28132—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects conducting part of electrode is difined by a sidewall spacer or a similar technique, e.g. oxidation under mask, plating
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
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    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz

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Abstract

본 발명은 반도체소자의 하드마스크 형성방법에 관한 것으로, 반도체기판 상부에 게이트전극용 도전체를 형성하고 그 상부에 제1실리콘질화막 및 실리콘 리치 실리콘산화질화막의 적층구조의 하드마스크를 형성한 다음, 상기 게이트전극용 도전체와 하드마스크를 패터닝하여 게이트전극을 형성하고 상기 게이트전극 측벽에 제2실리콘질화막으로 절연막 스페이서를 형성한 다음, 전체표면상부에 층간절연막을 형성하고 상기 반도체기판 셀영역의 층간절연막을 자기정렬적으로 식각하여 콘택홀을 형성한 다음, 상기 콘택홀을 매립하는 콘택플러그용 도전체를 형성하고 상기 제1실리콘산화막이 노출될때까지 평탄화식각하여 상기 셀영역의 콘택영역에 콘택플러그를 형성하는 동시에 상기 게이트전극 사이를 층간절연막으로 매립하여 평탄화시켜 후속공정을 용이하게 실시할 수 있도록 함으로써 반도체소자의 고집적화를 가능하게 하는 기술이다.The present invention relates to a method for forming a hard mask of a semiconductor device, wherein a conductor for a gate electrode is formed on a semiconductor substrate, and a hard mask having a stacked structure of a first silicon nitride film and a silicon rich silicon oxynitride film is formed thereon. A gate electrode is formed by patterning the gate electrode conductor and the hard mask, and an insulating film spacer is formed on the sidewall of the gate electrode using a second silicon nitride film. Then, an interlayer insulating film is formed on the entire surface of the semiconductor substrate cell region. Contact holes are formed by self-aligning the insulating film, and then contact conductors for filling the contact holes are formed and planar etching is performed until the first silicon oxide film is exposed to form contact plugs in the contact region of the cell region. At the same time as the interlayer insulating film is buried and planarized It is a technology that enables high integration of semiconductor devices by making the process easy to perform.

Description

반도체소자의 하드마스크 형성방법{Forming method for hard mask of semiconductor device}Forming method for hard mask of semiconductor device

본 발명은 반도체소자의 하드마스크 형성방법에 관한 것으로, 특히 미세패턴을 형성하기 위해 피식각층 상부에 형성되는 하드마스크를 형성하는데 있어서 화학기계연마 공정시 연마공정의 균일성을 향상시킬 수 있는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a hard mask of a semiconductor device, and more particularly, to forming a hard mask formed on an etched layer to form a fine pattern. It is about.

일반적으로 감광막패턴을 마스크로 하여 피식각층을 식각하여 반도체소자에 필요한 패턴을 형성하였다.In general, an etching target layer is etched using the photoresist pattern as a mask to form a pattern required for a semiconductor device.

그러나, 반도체소자가 고집적화됨에 따라 두꺼운 감광막패턴을 마스크로 하여 피식각층을 패터닝하는 경우 패턴의 DICD 와 FICD 에 차이가 유발되고, 패턴의 상측과 하측의 CD 가 다르게 되는 현상이 발생된다.However, as semiconductor devices are highly integrated, when the etching layer is patterned using a thick photoresist pattern as a mask, a difference occurs in the DICD and the FICD of the pattern, and the upper and lower CDs of the pattern are different.

이러한 현상을 해결하기 위하여, 최근에는 피식각층 상부에 하드마스크를 형성하고 그 상부에 감광막패턴을 형성하되, 종래보다 얇게 형성하여 이를 이용한 식각공정으로 상기 감광막패턴과 가능한 똑같은 크기의 하드마스크 패턴을 형성한다.In order to solve this phenomenon, in recent years, a hard mask is formed on the etched layer and a photoresist pattern is formed on the upper part of the etching target layer, and a thinner mask is formed on the etching layer to form a hard mask pattern having the same size as that of the photoresist pattern. do.

그리고, 후속공정으로 상기 하드마스크 패턴을 마스크로 하여 피식각층을 식각함으로써 예정된 크기의 피식각층 패턴을 형성할 수 있도록 한다.In the subsequent process, the etching target layer may be etched using the hard mask pattern as a mask to form an etching target layer pattern having a predetermined size.

그러나, 화학기계연마 공정시 연마되는 물질의 밀도 및 물성에 따라 연마되는 정도에 차이를 갖게 된다.However, the degree of polishing depends on the density and physical properties of the material to be polished during the chemical mechanical polishing process.

도 1a 및 도 1b 는 종래기술에 따른 반도체소자의 하드마스크 형성방법을 도시한 단면도로서, 일측은 셀영역을 도시하며 일부는 주변회로부를 도시한다.1A and 1B are cross-sectional views illustrating a method of forming a hard mask of a semiconductor device according to the prior art, one side showing a cell region and one part showing a peripheral circuit portion.

먼저, 반도체기판(1) 상부에 게이트전극용 도전체(2)를 형성하고 그 상부에 하드마스크인 제1실리콘질화막(3)을 적층한다.First, a gate electrode conductor 2 is formed on the semiconductor substrate 1, and a first silicon nitride film 3, which is a hard mask, is stacked on the semiconductor substrate 1.

그 다음, 게이트전극 마스크(도시안됨)를 이용한 노광 및 현상공정으로 감광막패턴(도시안됨)을 형성하고 이를 마스크로하여 상기 적층구조를 식각한다.Next, a photoresist pattern (not shown) is formed by an exposure and development process using a gate electrode mask (not shown), and the laminate structure is etched using the mask as a mask.

이때, 상기 셀영역은 미세패턴이 주로 형성되어 밀도가 높으며, 상기 주변회로부는 패턴의 밀도가 낮게 형성된다.In this case, the cell region has a high density due to mainly forming a fine pattern, and the peripheral circuit portion has a low density of the pattern.

그 다음, 상기 적층구조 측벽에 제2실리콘질화막으로 절연막 스페이서(4)를 형성한다.Next, an insulating film spacer 4 is formed on the sidewalls of the stacked structure using a second silicon nitride film.

그 다음, 상기 전체표면상부에 층간절연막(5)을 형성한다. 이때, 상기 층간절연막(5)은 셀영역과 주변회로영역을 모두 도포하도록 형성한다.Then, an interlayer insulating film 5 is formed over the entire surface. In this case, the interlayer insulating film 5 is formed so as to coat both the cell region and the peripheral circuit region.

그리고, 상기 셀부의 콘택영역을 노출시킬 수 있는 마스크를 이용하여 상기 층간절연막(5)을 식각한다.The interlayer insulating film 5 is etched using a mask that can expose the contact region of the cell portion.

이때, 상기 하드마스크(3)와 절연막 스페이서(4)를 마스크로하여 상기 반도체기판을 노출시키도록 자기정렬적인 콘택홀(6)을 셀영역에 형성한다. (도 1a)In this case, a self-aligned contact hole 6 is formed in the cell region to expose the semiconductor substrate using the hard mask 3 and the insulating film spacer 4 as a mask. (FIG. 1A)

그 다음, 상기 콘택홀(6)을 매립하는 다결정실리콘막(7)을 전체표면상부에 형성하고 화학기계연마방법으로 상기 하드마스크가 노출되도록 연마함으로써 게이트전극간의 콘택영역을 각각 매립하는 콘택플러그를 다결정실리콘막으로 형성한다.Next, a contact plug for embedding the contact regions between the gate electrodes is formed by forming a polysilicon film 7 filling the contact hole 6 on the entire surface and polishing the hard mask to be exposed by chemical mechanical polishing. It is formed of a polycrystalline silicon film.

이때, 패턴 밀도가 낮은 주변회로영역의 하드마스크(3), 즉 제1실리콘질화막은 약간만 식각되거나 과도하게 식각되어 연마공정의 균일도가 낮아지게 된다.At this time, the hard mask 3 of the peripheral circuit region having a low pattern density, that is, the first silicon nitride layer is slightly etched or excessively etched to lower the uniformity of the polishing process.

그로인하여, 후속공정을 실시하기가 어려운 문제점이 있다. (도 1b)Therefore, there is a problem that it is difficult to carry out the subsequent process. (FIG. 1B)

여기서, 상기 하드마스크인 제1실리콘질화막(3) 상측에 반사방지막인 실리콘산화질화막이 형성되지만 게이트전극을 형성하기 위한 패터닝공정시 모두 제거된다.Here, a silicon oxynitride film, which is an antireflection film, is formed on the first silicon nitride film 3, which is the hard mask, but is removed during the patterning process for forming the gate electrode.

본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 패턴 밀도에 관계없이 화학기계연마공정의 균일성을 향상시켜 반도체소자의 후속공정을 용이하게 실시할 수 있도록 하는 반도체소자의 하드마스크 형성방법을 제공하는데 그 목적이 있다.The present invention provides a method for forming a hard mask of a semiconductor device to improve the uniformity of the chemical mechanical polishing process irrespective of the pattern density so that subsequent processes of the semiconductor device can be easily performed. The purpose is to provide.

도 1a 및 도 1b 는 종래기술에 따른 반도체소자의 하드마스크 형성방법을 도시한 단면도.1A and 1B are cross-sectional views illustrating a hard mask forming method of a semiconductor device according to the prior art.

도 2a 및 도 2b 는 본 발명의 실시예에 따른 반도체소자의 하드마스크 형성방법을 도시한 단면도.2A and 2B are cross-sectional views illustrating a hard mask forming method of a semiconductor device in accordance with an embodiment of the present invention.

< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>

1 : 반도체기판 2 : 게이트전극용 도전체1 semiconductor substrate 2 conductor for gate electrode

3 : 제1실리콘질화막3: first silicon nitride film

3' : 실리콘리치 산화질화막 ( Si-rich SiON )3 ': silicon rich oxynitride (Si-rich SiON)

4 : 제2실리콘질화막 5 : 층간절연막4: second silicon nitride film 5: interlayer insulating film

6 : 자기정렬적인 콘택홀 7 : 다결정실리콘막6 self-aligned contact hole 7 polysilicon film

이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 하드마스크 형성방법은,In order to achieve the above object, a hard mask forming method of a semiconductor device according to the present invention,

반도체기판 상부에 게이트전극용 도전체를 형성하고 그 상부에 제1실리콘질화막 및 실리콘 리치 실리콘산화질화막의 적층구조의 하드마스크를 형성하는 공정과,Forming a gate electrode conductor on the semiconductor substrate, and forming a hard mask on the semiconductor substrate, the hard mask having a lamination structure of a first silicon nitride film and a silicon rich silicon oxynitride film;

상기 게이트전극용 도전체와 하드마스크를 패터닝하여 게이트전극을 형성하는 공정과,Patterning the gate electrode conductor and the hard mask to form a gate electrode;

상기 게이트전극 측벽에 제2실리콘질화막으로 절연막 스페이서를 형성하는 공정과,Forming an insulating film spacer on the sidewalls of the gate electrode with a second silicon nitride film;

전체표면상부에 층간절연막을 형성하는 공정과,Forming an interlayer insulating film over the entire surface;

상기 반도체기판 셀영역의 층간절연막을 자기정렬적으로 식각하여 콘택홀을 형성하는 공정과,Forming a contact hole by self-aligning the interlayer insulating film of the semiconductor substrate cell region;

상기 콘택홀을 매립하는 콘택플러그용 도전체를 형성하는 공정과,Forming a contact plug conductor to fill the contact hole;

상기 제1실리콘산화막이 노출될때까지 평탄화식각하여 상기 셀영역의 콘택영역에 콘택플러그를 형성하는 동시에 상기 게이트전극 사이를 층간절연막으로 매립하여 평탄화시키는 공정을 포함하는 것을 특징으로한다.And forming a contact plug in the contact region of the cell region by planarization etching until the first silicon oxide layer is exposed, and simultaneously filling the planarity by interposing the gate electrodes with an interlayer insulating layer.

이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 2a 및 도 2b 는 본 발명의 실시예에 따른 반도체소자의 하드마스크 형성방법을 도시한 단면도로서, 일측은 셀영역을 도시하고 타측은 주변회로부를 도시한다.2A and 2B are cross-sectional views illustrating a hard mask forming method of a semiconductor device in accordance with an embodiment of the present invention, one side showing a cell region and the other side showing a peripheral circuit portion.

먼저, 반도체기판(1) 상부에 게이트전극용 도전체(2)를 형성하고 그 상부에 하드마스크를 형성하되, 제1실리콘질화막(3)과 실리콘 리치 실리콘산화질화막(3')을 형성하여 게이트전극용 도전체(2)/제1실리콘질화막(3)/실리콘 리치 실리콘산화질화막(3')의 적층구조를 형성한다.First, a gate electrode conductor 2 is formed on the semiconductor substrate 1, and a hard mask is formed on the gate substrate. The first silicon nitride film 3 and the silicon rich silicon oxynitride film 3 'are formed to form a gate. A laminated structure of an electrode conductor 2, a first silicon nitride film 3, and a silicon rich silicon oxynitride film 3 'is formed.

이때, 상기 제1실리콘질화막(3)은 플라즈마 화학기상증착 방벙, 저압화학기상증착방법 또는 MOCVD ( ) 방법으로 형성한다.In this case, the first silicon nitride film 3 is formed by plasma chemical vapor deposition, low pressure chemical vapor deposition, or MOCVD ().

그리고, 상기 실리콘 리치 실리콘산화질화막(3')은 실리콘을 전체 조성의 10 ∼ 40 부피비를 갖는다.The silicon rich silicon oxynitride film 3 'has a volume ratio of 10 to 40 of the total composition of silicon.

그리고, 도시되지않았으나 실리콘 산화질화막으로 반사방지막을 형성한다. 여기서, 상기 반사방지막은 실리콘 리치 실리콘산화질화막으로 형성할 수도 있다.Although not shown, an antireflection film is formed of a silicon oxynitride film. The antireflection film may be formed of a silicon rich silicon oxynitride film.

그 다음, 게이트전극 마스크(도시안됨)를 이용한 노광 및 현상공정으로 감광막패턴(도시안됨)을 형성하고 이를 마스크로하여 상기 적층구조를 식각한다.Next, a photoresist pattern (not shown) is formed by an exposure and development process using a gate electrode mask (not shown), and the laminate structure is etched using the mask as a mask.

이때, 상기 셀영역은 미세패턴이 주로 형성되어 밀도가 높으며, 상기 주변회로부는 패턴의 밀도가 낮게 형성된다.In this case, the cell region has a high density due to mainly forming a fine pattern, and the peripheral circuit portion has a low density of the pattern.

그 다음, 상기 적층구조 측벽에 제2실리콘질화막으로 절연막 스페이서(4)를 형성한다. 여기서, 상기 제2실리콘 질화막 대신에 실리콘 리치 실리콘산화질화막으로 형성할 수도 있다.Next, an insulating film spacer 4 is formed on the sidewalls of the stacked structure using a second silicon nitride film. The silicon rich silicon oxynitride layer may be formed instead of the second silicon nitride layer.

그 다음, 상기 전체표면상부에 층간절연막(5)을 형성한다. 이때, 상기 층간절연막(5)은 셀영역과 주변회로영역을 모두 도포하도록 형성한다. 그리고, 상기 층간절연막(5)은 저압화학기상증착방법, 대기압화학기상증착방법 또는 플라즈마화학기상증착방법으로 형성한 산화막, BPSG 산화막, 고밀도플라즈마증착 산화막 그리고 에스.오.지. ( spin on glass, SOG ) 막 등을 이용하여 형성할 수 있다.Then, an interlayer insulating film 5 is formed over the entire surface. In this case, the interlayer insulating film 5 is formed so as to coat both the cell region and the peripheral circuit region. The interlayer insulating film 5 may be formed of an oxide film, a BPSG oxide film, a high density plasma deposition oxide film, and an S. O. G. film formed by a low pressure chemical vapor deposition method, an atmospheric pressure chemical vapor deposition method, or a plasma chemical vapor deposition method. (spin on glass, SOG) film or the like.

그 다음, 상기 셀부의 콘택영역을 노출시킬 수 있는 마스크를 이용하여 상기 층간절연막(5)을 식각한다.Next, the interlayer insulating film 5 is etched using a mask that can expose the contact region of the cell portion.

이때, 상기 하드마스크(3)와 절연막 스페이서(4)를 마스크로하여 상기 반도체기판을 노출시키도록 자기정렬적인 콘택홀(6)을 셀영역에 형성한다. (도 2a)In this case, a self-aligned contact hole 6 is formed in the cell region to expose the semiconductor substrate using the hard mask 3 and the insulating film spacer 4 as a mask. (FIG. 2A)

그 다음, 상기 콘택홀(6)을 매립하는 다결정실리콘막(7)을 전체표면상부에 형성하고 화학기계연마방법으로 상기 하드마스크가 노출되도록 연마함으로써 게이트전극간의 콘택영역을 각각 매립하는 콘택플러그를 다결정실리콘막(7)으로 형성한다.Next, a contact plug for embedding the contact regions between the gate electrodes is formed by forming a polysilicon film 7 filling the contact hole 6 on the entire surface and polishing the hard mask to be exposed by chemical mechanical polishing. Polycrystalline silicon film 7 is formed.

이때, 패턴 밀도가 낮은 주변회로영역의 하드마스크는 셀영역과 같이 실리콘 리치 산화질화막(3')이 제거되고 제1실리콘질화막(3)이 노출됨으로써 셀영역에 콘택플러그가 형성되고 콘택플러그가 형성되지않는 부분은 상기 층간절연막(5)으로 매립되어 평탄화된다.(도 2b)In this case, in the hard mask of the peripheral circuit region having a low pattern density, the silicon rich oxynitride layer 3 'is removed like the cell region and the first silicon nitride layer 3 is exposed so that a contact plug is formed in the cell region and a contact plug is formed. The portion not to be filled is flattened by filling the interlayer insulating film 5 (FIG. 2B).

한편, 상기 절연막 스페이서(4)를 형성하고 전체표면상부에 얇은 실리콘 리치 실리콘산화질화막을 형성할 수도 있다.Meanwhile, the insulating film spacer 4 may be formed, and a thin silicon rich silicon oxynitride film may be formed on the entire surface.

그리고, 평탄화식각공정은 화학기계연마 외에 에치백이나 습식에치 방법으로 실시할 수 있다.The planar etching process may be performed by an etch back or wet etching method in addition to chemical mechanical polishing.

이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 하드마스크 형성방법은, 패턴의 크기나 밀도에 관계없이 균일한 평탄화식각공정을 실시할 수 있도록 하여 후속공정을 용이하게 실시할 수 있도록 하는 효과를 제공한다.As described above, the method for forming a hard mask of a semiconductor device according to the present invention provides an effect of easily performing a subsequent flattening etching process regardless of the size or density of a pattern. do.

Claims (6)

반도체기판 상부에 게이트전극용 도전체를 형성하고 그 상부에 제1실리콘질화막 및 실리콘 리치 실리콘산화질화막의 적층구조의 하드마스크를 형성하는 공정과,Forming a gate electrode conductor on the semiconductor substrate, and forming a hard mask on the semiconductor substrate, the hard mask having a lamination structure of a first silicon nitride film and a silicon rich silicon oxynitride film; 상기 게이트전극용 도전체와 하드마스크를 패터닝하여 게이트전극을 형성하는 공정과,Patterning the gate electrode conductor and the hard mask to form a gate electrode; 상기 게이트전극 측벽에 제2실리콘질화막으로 절연막 스페이서를 형성하는 공정과,Forming an insulating film spacer on the sidewalls of the gate electrode with a second silicon nitride film; 전체표면상부에 층간절연막을 형성하는 공정과,Forming an interlayer insulating film over the entire surface; 상기 반도체기판 셀영역의 층간절연막을 자기정렬적으로 식각하여 콘택홀을 형성하는 공정과,Forming a contact hole by self-aligning the interlayer insulating film of the semiconductor substrate cell region; 상기 콘택홀을 매립하는 콘택플러그용 도전체를 형성하는 공정과,Forming a contact plug conductor to fill the contact hole; 상기 제1실리콘산화막이 노출될때까지 평탄화식각하여 상기 셀영역의 콘택영역에 콘택플러그를 형성하는 동시에 상기 게이트전극 사이를 층간절연막으로 매립하여 평탄화시키는 공정을 포함하는 반도체소자의 하드마스크 형성방법.Forming a contact plug in the contact region of the cell region by planarization etching until the first silicon oxide layer is exposed, and simultaneously filling the planarity by interposing the gate electrodes with an interlayer insulating layer. 제 1 항에 있어서,The method of claim 1, 상기 하드마스크 상부에 실리콘산화질화막이나 실리콘리치산화질화막으로 반사방지막을 형성하는 것을 특징으로하는 반도체소자의 하드마스크 형성방법.And forming an anti-reflection film on the hard mask using a silicon oxynitride film or a silicon rich oxynitride film. 제 1 항에 있어서,The method of claim 1, 상기 제1실리콘산화막은 PECVD, LPCVD 또는 MOCVD 방법으로 형성하는 것을 특징으로하는 반도체소자의 하드마스크 형성방법.Wherein the first silicon oxide film is formed by PECVD, LPCVD, or MOCVD. 제 1 항에 있어서,The method of claim 1, 상기 절연막 스페이서인 제2실리콘질화막은 실리콘 리치 실리콘산화질화막으로 형성하는 것을 특징으로하는 반도체소자의 하드마스크 형성방법.And a second silicon nitride film as the insulating film spacer, a silicon rich silicon oxynitride film. 제 1 항에 있어서,The method of claim 1, 상기 층간절연막은 저압화학기상증착방법, 대기압화학기상증착방법 또는 플라즈마화학기상증착방법으로 형성한 산화막, BPSG 산화막, 고밀도플라즈마증착 산화막 또는 에스.오.지. ( spin on glass, SOG ) 막 등을 이용하여 형성하는 것을 특징으로 하는 반도체소자의 하드마스크 형성방법.The interlayer insulating film may be formed of an oxide film, a BPSG oxide film, a high density plasma deposition oxide film, or S. O. G. formed by a low pressure chemical vapor deposition method, an atmospheric pressure chemical vapor deposition method, or a plasma chemical vapor deposition method. A method of forming a hard mask of a semiconductor device, the method comprising forming a spin on glass (SOG) film. 제 1 항에 있어서,The method of claim 1, 상기 평탄화식각공정은 화학기계연마, 에치백 또는 습식식각방법으로 실시하는 것을 특징으로하는 반도체소자의 하드마스크 형성방법.The planarization etching process is a hard mask forming method of a semiconductor device, characterized in that performed by chemical mechanical polishing, etch back or wet etching method.
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